mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
omap3: remove typedefs for configuration structs
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
This commit is contained in:
Dirk Behme
Wolfgang Denk
parent
187af954cf
commit
97a099eaa4
19 changed files with 77 additions and 77 deletions
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@ -103,8 +103,8 @@ void beagle_identify(void)
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*/
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int misc_init_r(void)
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{
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gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
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gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
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struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
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struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
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twl4030_power_init();
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twl4030_led_init();
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@ -92,9 +92,9 @@ void set_muxconf_regs(void)
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*/
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static void setup_net_chip(void)
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{
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gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
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gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
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ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
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struct gpio *gpio3_base = (struct gpio *)OMAP34XX_GPIO3_BASE;
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struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
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struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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/* Configure GPMC registers */
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writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1);
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@ -60,10 +60,10 @@ int board_init(void)
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*/
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int misc_init_r(void)
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{
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gpio_t *gpio1_base = (gpio_t *)OMAP34XX_GPIO1_BASE;
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gpio_t *gpio4_base = (gpio_t *)OMAP34XX_GPIO4_BASE;
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gpio_t *gpio5_base = (gpio_t *)OMAP34XX_GPIO5_BASE;
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gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE;
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struct gpio *gpio1_base = (struct gpio *)OMAP34XX_GPIO1_BASE;
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struct gpio *gpio4_base = (struct gpio *)OMAP34XX_GPIO4_BASE;
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struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
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struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE;
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twl4030_power_init();
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twl4030_led_init();
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@ -123,7 +123,7 @@ void zoom2_identify(void)
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int board_init (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
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struct gpmc *gpmc = (struct gpmc *)GPMC_BASE;
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u32 *gpmc_config;
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gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
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@ -59,11 +59,11 @@ static inline void delay(unsigned long loops)
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*****************************************************************************/
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void secure_unlock_mem(void)
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{
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pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
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pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
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pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
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pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
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sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;
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struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
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struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
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struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
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struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
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struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
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/* Protection Module Register Target APE (PM_RT) */
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writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
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@ -234,7 +234,7 @@ void s_init(void)
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* Routine: wait_for_command_complete
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* Description: Wait for posting to finish on watchdog
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*****************************************************************************/
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void wait_for_command_complete(watchdog_t *wd_base)
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void wait_for_command_complete(struct watchdog *wd_base)
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{
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int pending = 1;
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do {
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@ -248,8 +248,8 @@ void wait_for_command_complete(watchdog_t *wd_base)
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*****************************************************************************/
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void watchdog_init(void)
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{
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watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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/*
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* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
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@ -41,10 +41,10 @@
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u32 get_osc_clk_speed(void)
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{
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u32 start, cstart, cend, cdiff, val;
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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prm_t *prm_base = (prm_t *)PRM_BASE;
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gptimer_t *gpt1_base = (gptimer_t *)OMAP34XX_GPT1;
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s32ktimer_t *s32k_base = (s32ktimer_t *)SYNC_32KTIMER_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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struct prm *prm_base = (struct prm *)PRM_BASE;
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struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
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struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
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val = readl(&prm_base->clksrc_ctrl);
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@ -133,8 +133,8 @@ void prcm_init(void)
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int xip_safe, p0, p1, p2, p3;
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u32 osc_clk = 0, sys_clkin_sel;
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u32 clk_index, sil_index = 0;
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prm_t *prm_base = (prm_t *)PRM_BASE;
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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struct prm *prm_base = (struct prm *)PRM_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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dpll_param *dpll_param_p;
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f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
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@ -341,7 +341,7 @@ void prcm_init(void)
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*****************************************************************************/
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void per_clocks_enable(void)
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{
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prcm_t *prcm_base = (prcm_t *)PRCM_BASE;
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struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
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/* Enable GP2 timer. */
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sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
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@ -51,7 +51,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
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M_NAND_GPMC_CONFIG6, 0
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};
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gpmc_t *gpmc_cfg_base;
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struct gpmc *gpmc_cfg;
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#if defined(CONFIG_ENV_IS_IN_NAND)
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#define GPMC_CS 0
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@ -79,7 +79,7 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = {
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#endif
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static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
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static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
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/**************************************************************************
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* make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow
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@ -146,12 +146,12 @@ void sdrc_init(void)
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void do_sdrc_init(u32 cs, u32 early)
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{
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sdrc_actim_t *sdrc_actim_base;
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struct sdrc_actim *sdrc_actim_base;
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if(cs)
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sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL1_BASE;
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sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
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else
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sdrc_actim_base = (sdrc_actim_t *)SDRC_ACTIM_CTRL0_BASE;
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sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
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if (early) {
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/* reset sdrc controller */
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@ -219,7 +219,7 @@ void gpmc_init(void)
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{
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/* putting a blanket check on GPMC based on ZeBu for now */
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u32 *gpmc_config = NULL;
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gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
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struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
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u32 base = 0;
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u32 size = 0;
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u32 f_off = CONFIG_SYS_MONITOR_LEN;
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@ -243,7 +243,7 @@ void gpmc_init(void)
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#if defined(CONFIG_CMD_NAND) /* CS 0 */
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gpmc_config = gpmc_m_nand;
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gpmc_cfg_base = gpmc_base;
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gpmc_cfg = gpmc_base;
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base = PISMO1_NAND_BASE;
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size = PISMO1_NAND_SIZE;
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@ -32,9 +32,9 @@
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#include <i2c.h>
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extern omap3_sysinfo sysinfo;
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static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
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static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
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static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
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static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
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static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
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static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
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static char *rev_s[CPU_3XX_MAX_REV] = {
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"1.0",
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"2.0",
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@ -47,7 +47,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
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*****************************************************************/
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void dieid_num_r(void)
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{
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ctrl_id_t *id_base = (ctrl_id_t *)OMAP34XX_ID_L4_IO_BASE;
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struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
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char *uid_s, die_id[34];
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u32 id[4];
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@ -82,7 +82,7 @@ u32 get_cpu_type(void)
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u32 get_cpu_rev(void)
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{
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u32 cpuid = 0;
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ctrl_id_t *id_base;
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struct ctrl_id *id_base;
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/*
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* On ES1.0 the IDCODE register is not exposed on L4
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@ -93,7 +93,7 @@ u32 get_cpu_rev(void)
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return CPU_3XX_ES10;
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else {
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/* Decode the IDs on > ES1.0 */
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id_base = (ctrl_id_t *) OMAP34XX_ID_L4_IO_BASE;
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id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
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cpuid = (readl(&id_base->idcode) >> CPU_3XX_ID_SHIFT) & 0xf;
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@ -37,7 +37,7 @@
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static ulong timestamp;
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static ulong lastinc;
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static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
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static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
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/*
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* Nothing really to do with interrupts, just starts up a counter.
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@ -30,7 +30,7 @@
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#include <nand.h>
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static uint8_t cs;
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static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
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static struct gpmc *gpmc_base = (struct gpmc *)GPMC_BASE;
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static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
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/*
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@ -28,7 +28,7 @@
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/* Register offsets of common modules */
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/* Control */
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#ifndef __ASSEMBLY__
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typedef struct ctrl {
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struct ctrl {
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unsigned char res1[0xC0];
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unsigned short gpmc_nadv_ale; /* 0xC0 */
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unsigned short gpmc_noe; /* 0xC2 */
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@ -49,7 +49,7 @@ typedef struct ctrl {
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unsigned int randkey_3; /* 0x324 */
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unsigned char res5[0x124];
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unsigned int ctrl_omap_stat; /* 0x44C */
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} ctrl_t;
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};
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#else /* __ASSEMBLY__ */
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#define CONTROL_STATUS 0x2F0
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#endif /* __ASSEMBLY__ */
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@ -61,7 +61,7 @@ typedef struct ctrl {
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#define OMAP3530 0x0c00
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#ifndef __ASSEMBLY__
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typedef struct ctrl_id {
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struct ctrl_id {
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unsigned char res1[0x4];
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unsigned int idcode; /* 0x04 */
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unsigned int prod_id; /* 0x08 */
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@ -70,7 +70,7 @@ typedef struct ctrl_id {
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unsigned int die_id_1; /* 0x1C */
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unsigned int die_id_2; /* 0x20 */
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unsigned int die_id_3; /* 0x24 */
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} ctrl_id_t;
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};
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#endif /* __ASSEMBLY__ */
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/* device type */
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@ -99,7 +99,7 @@ struct gpmc_cs {
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unsigned char res[8]; /* blow up to 0x30 byte */
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};
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typedef struct gpmc {
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struct gpmc {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned char res2[0x4];
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@ -125,7 +125,7 @@ typedef struct gpmc {
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unsigned int ecc7_result; /* 0x218 */
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unsigned int ecc8_result; /* 0x21C */
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unsigned int ecc9_result; /* 0x220 */
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} gpmc_t;
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};
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#else /* __ASSEMBLY__ */
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#define GPMC_CONFIG1 0x00
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#define GPMC_CONFIG2 0x04
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@ -151,21 +151,21 @@ typedef struct gpmc {
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/* (actual size small port) */
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/* SMS */
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#ifndef __ASSEMBLY__
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typedef struct sms {
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struct sms {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned char res2[0x34];
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unsigned int rg_att0; /* 0x48 */
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unsigned char res3[0x84];
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unsigned int class_arb0; /* 0xD0 */
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} sms_t;
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};
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#endif /* __ASSEMBLY__ */
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#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
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/* SDRC */
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#ifndef __ASSEMBLY__
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typedef struct sdrc_cs {
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struct sdrc_cs {
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unsigned int mcfg; /* 0x80 || 0xB0 */
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unsigned int mr; /* 0x84 || 0xB4 */
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unsigned char res1[0x4];
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@ -174,14 +174,14 @@ typedef struct sdrc_cs {
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unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
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unsigned int manual; /* 0xA8 || 0xD8 */
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unsigned char res3[0x4];
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} sdrc_cs_t;
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};
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typedef struct sdrc_actim {
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struct sdrc_actim {
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unsigned int ctrla; /* 0x9C || 0xC4 */
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unsigned int ctrlb; /* 0xA0 || 0xC8 */
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} sdrc_actim_t;
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};
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typedef struct sdrc {
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struct sdrc {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int status; /* 0x14 */
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@ -195,8 +195,8 @@ typedef struct sdrc {
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unsigned int dllb_status; /* 0x6C */
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unsigned int power; /* 0x70 */
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unsigned char res4[0xC];
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sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
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} sdrc_t;
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struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */
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};
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#endif /* __ASSEMBLY__ */
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#define DLLPHASE_90 (0x1 << 1)
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@ -240,7 +240,7 @@ typedef struct sdrc {
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/* timer regs offsets (32 bit regs) */
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#ifndef __ASSEMBLY__
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typedef struct gptimer {
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struct gptimer {
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unsigned int tidr; /* 0x00 r */
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unsigned char res[0xc];
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unsigned int tiocp_cfg; /* 0x10 rw */
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@ -257,7 +257,7 @@ typedef struct gptimer {
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unsigned int tcar1; /* 0x3c r */
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unsigned int tcicr; /* 0x40 rw */
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unsigned int tcar2; /* 0x44 r */
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} gptimer_t;
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};
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#endif /* __ASSEMBLY__ */
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/* enable sys_clk NO-prescale /1 */
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@ -265,12 +265,12 @@ typedef struct gptimer {
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/* Watchdog */
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#ifndef __ASSEMBLY__
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typedef struct watchdog {
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struct watchdog {
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unsigned char res1[0x34];
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unsigned int wwps; /* 0x34 r */
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unsigned char res2[0x10];
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unsigned int wspr; /* 0x48 rw */
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} watchdog_t;
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};
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#endif /* __ASSEMBLY__ */
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#define WD_UNLOCK1 0xAAAA
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@ -280,7 +280,7 @@ typedef struct watchdog {
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#define PRCM_BASE 0x48004000
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#ifndef __ASSEMBLY__
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typedef struct prcm {
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struct prcm {
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unsigned int fclken_iva2; /* 0x00 */
|
||||
unsigned int clken_pll_iva2; /* 0x04 */
|
||||
unsigned char res1[0x1c];
|
||||
|
|
@ -344,7 +344,7 @@ typedef struct prcm {
|
|||
unsigned int clksel_per; /* 0x1040 */
|
||||
unsigned char res28[0xfc];
|
||||
unsigned int clksel1_emu; /* 0x1140 */
|
||||
} prcm_t;
|
||||
};
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define CM_CLKSEL_CORE 0x48004a40
|
||||
#define CM_CLKSEL_GFX 0x48004b40
|
||||
|
|
@ -357,14 +357,14 @@ typedef struct prcm {
|
|||
#define PRM_BASE 0x48306000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct prm {
|
||||
struct prm {
|
||||
unsigned char res1[0xd40];
|
||||
unsigned int clksel; /* 0xd40 */
|
||||
unsigned char res2[0x50c];
|
||||
unsigned int rstctrl; /* 0x1250 */
|
||||
unsigned char res3[0x1c];
|
||||
unsigned int clksrc_ctrl; /* 0x1270 */
|
||||
} prm_t;
|
||||
};
|
||||
#else /* __ASSEMBLY__ */
|
||||
#define PRM_RSTCTRL 0x48307250
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
|
@ -400,7 +400,7 @@ typedef struct prm {
|
|||
#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct pm {
|
||||
struct pm {
|
||||
unsigned char res1[0x48];
|
||||
unsigned int req_info_permission_0; /* 0x48 */
|
||||
unsigned char res2[0x4];
|
||||
|
|
@ -413,7 +413,7 @@ typedef struct pm {
|
|||
unsigned int req_info_permission_1; /* 0x68 */
|
||||
unsigned char res6[0x14];
|
||||
unsigned int addr_match_2; /* 0x80 */
|
||||
} pm_t;
|
||||
};
|
||||
#endif /*__ASSEMBLY__ */
|
||||
|
||||
/* Permission values for registers -Full fledged permissions to all */
|
||||
|
|
|
|||
|
|
@ -29,12 +29,12 @@
|
|||
#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef enum {
|
||||
enum {
|
||||
STACKED = 0,
|
||||
IP_DDR = 1,
|
||||
COMBO_DDR = 2,
|
||||
IP_SDR = 3,
|
||||
} mem_t;
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define EARLY_INIT 1
|
||||
|
|
|
|||
|
|
@ -79,10 +79,10 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
typedef struct s32ktimer {
|
||||
struct s32ktimer {
|
||||
unsigned char res[0x10];
|
||||
unsigned int s32k_cr; /* 0x10 */
|
||||
} s32ktimer_t;
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
|
|
@ -95,14 +95,14 @@ typedef struct s32ktimer {
|
|||
#define OMAP34XX_GPIO6_BASE 0x49058000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef struct gpio {
|
||||
struct gpio {
|
||||
unsigned char res1[0x34];
|
||||
unsigned int oe; /* 0x34 */
|
||||
unsigned int datain; /* 0x38 */
|
||||
unsigned char res2[0x54];
|
||||
unsigned int cleardataout; /* 0x90 */
|
||||
unsigned int setdataout; /* 0x94 */
|
||||
} gpio_t;
|
||||
};
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#define GPIO0 (0x1 << 0)
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@
|
|||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern gpmc_t *gpmc_cfg_base;
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
|
|
|
|||
|
|
@ -292,7 +292,7 @@
|
|||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern gpmc_t *gpmc_cfg_base;
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
|
|
|
|||
|
|
@ -285,7 +285,7 @@
|
|||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern gpmc_t *gpmc_cfg_base;
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
|
|
|
|||
|
|
@ -289,7 +289,7 @@
|
|||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern gpmc_t *gpmc_cfg_base;
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
|
|
|
|||
|
|
@ -297,7 +297,7 @@
|
|||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern gpmc_t *gpmc_cfg_base;
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
|
|
|
|||
|
|
@ -252,7 +252,7 @@
|
|||
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern gpmc_t *gpmc_cfg_base;
|
||||
extern struct gpmc *gpmc_cfg;
|
||||
extern unsigned int boot_flash_base;
|
||||
extern volatile unsigned int boot_flash_env_addr;
|
||||
extern unsigned int boot_flash_off;
|
||||
|
|
|
|||
Loading…
Reference in a new issue