Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Enable FPGA full reconfiguration support with Intel FPGA SDM
Mailbox driver for Agilex.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver
because it is using generic SDM (Secure Device Manager) Mailbox
interface shared by other platform (e.g. Agilex) as well.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.
This fixed error below in SPL:
cache controller driver NOT found!
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add initial support for the ABB SECU board, which is an ArriaV-based
SoCFPGA system with ethernet and booting from Denali NAND.
Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The default implementation of ERR_PTR/PTR_ERR maps errno values at the
and of the address range (e.g. -EINVAL/-22 gets 0xFFFFFFEA).
For socfpga gen5 SPL, this doesn't really work, as the heap is nearly
at the end of the 32 bit address range.
This patch adjusts the ERR_PTR_OFFSET to map errno values into the range
of the Boot ROM, which should not be used for valid pointers.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The company Samtec was merged into Softing, migrate the board over to
the new name and update copyright headers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This is currently a decimal value which is not as convenient or
meaningful. Also U-Boot tends to use hex everywhere.
Convert this option to hex and add a comment for the size_check macro.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the typo in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present there is only one control for this and it is used for both SPL
and TPL. But SPL might have a lot more space than TPL so the extra cost of
a full printf() might be acceptable.
Split the option into two, providing separate SPL and TPL controls. The
TPL setting defaults to the same as SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This provides an SPL_SIZE_LIMIT that makes the build check that the SPL
binary loaded from flash fits into the SRAM (64 KiB) and leaves enough
room for global data, heap and stack (512 bytes assumed stack usage).
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK and MCVEVP baseboard. The board can boot
from eMMC. Ethernet and USB is supported.
The Aries Embedded boards have been removed with commit 03b54997d5
("board/aries: Remove"). I will now take care of them.
The device-tree files are from mainline Linux commit e93c9c99a629
("Linux v5.1)".
Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
CC: Marek Vasut <marex@denx.de>
CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.
On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).
To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
This commit moves common config options used in all socfpga boards
to select/imply in Kconfig. This both cleans up the defconfig files
as well as makes future changes easier.
Options implied/defaulted for all sub-arches:
- SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS
Options implied/defaulted for implied for A10 & gen5:
- FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE
Options implied/defaulted for gen5:
- SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Another round of sorting Kconfig entries aplhabetically.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Add build support for Stratix SoC
Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Conflicts:
arch/arm/Kconfig
arch/arm/mach-socfpga/Kconfig
The various Aries Embedded boards have been orphaned for a year and no
one has come forward to take care of them. Remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Shuffle the default Kconfig entries around so it is not such a mess.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Add support for a new boards from devboards.de , the DBM-SoC1 .
This board has one ethernet port, one USB OTG port and USB UART.
Signed-off-by: Marek Vasut <marex@denx.de>
This converts the following to Kconfig:
CONFIG_SPL_BOARD_INIT
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
[trini: Update the Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add support for the Terasic DE10-Nano board. The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Convert Altera DDR SDRAM driver to use Kconfig method.
Enable ALTERA_SDRAM by default if it is on Gen5 target.
Arria 10 will have different driver.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
the socfpga bootrom supports mmc booting from either a raw image
starting at 0x0, or from a partition of type 0xa2. This patch
adds support for locating the boot image in the first type 0xa2
partition found.
Assigned a partition number of -1 will cause a search for a
partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
and use it to find the u-boot image
Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
This option should not really be user selectable. Note that on PowerPC
we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be
conditional on that.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
Add CycloneV based Terasic DE1-SoC board. The board boots
from SD/MMC. Ethernet and USB host is supported.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>
Just sort the board entries, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This adds support for IS1 board. Pretty usual socfpga board,
256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two
additional ethernet ports connected to the FPGA.
Signed-off-by: Pavel Machek <pavel@denx.de>
Add support for board based on the popular Altera Cyclone V SoC.
This board has the following properties:
- 1 GiB of DRAM
- 1 Gigabit ethernet
- 1 USB gadget port
- 1 USB host port with an on-board hub
- 2 QSPI NORs connected to the Cadence QSPI core
- Multiple I2C EEPROMs and one I2C temperature sensor
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
---
V2: Update the defconfig as per Tom's request
In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check
for both AV || AV.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:
- SPI NOR
- eMMC
- Ethernet
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
