Commit graph

300 commits

Author SHA1 Message Date
Larry Johnson
c68f59fe3e Use definitions from "asm-ppc/mmu.h" in init.S for Sequoia
Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27 19:35:35 +01:00
Stefan Roese
bf8324e4a5 ppc4xx: Add fdt support to AMCC Katmai eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:34 +01:00
Stefan Roese
136288847e ppc4xx: Bring 4xx fdt support up-to-date
This patch update the 4xx fdt support. It enabled fdt booting
on the AMCC Kilauea and Sequoia for now. More can follow later
quite easily.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-27 19:35:32 +01:00
Stefan Roese
7cfc12a7dc ppc4xx: 405EX: Correctly enable USB pins
This patch selects the USB data pins in the 405EX GPIO and MFC (multi
function control) registers. This is done for the AMCC Kilauea and
Makalu eval boards.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-08 14:47:34 +01:00
Stefan Roese
a27044b14a ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards
This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by
setting the FIXD bit in the SDR0_MFR register. Here a description of the
symptoms:

Problem Description
------------------------------
If a DMA is performed between memory and PCI with the DMA 1 Controller
using prefetch, and as a result uses a special purpose buffer selected by
the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29),
the first part of the transfer sequence is performed twice. The
PPC440SPe PCI Controller requests more data than was needed such that in
the case of enforce memory protection, a host CPU  exception can occur.
No data is corrupted, because data transfer is stopped in the PCI
Controller. Prefetch enable is specified by setting DMA Configuration
Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0.

Behavior that may be observed in a running system
---------------------------------------------------------------------------

1. DMA performance is decreased because of the double access on the PCI bus
interface.
2. If an illegal access to some address on the PCI bus is detected at the
system level, a machine check or similar system error may occur.

Workarounds Available
----------------------------------

1. Do not program prefetch. Note that a prefetch command cannot be programmed
without selecting a special purpose buffer.
2. To avoid crossing a physical boundary of the PCI slave device, add 512
bytes of address to the PCI address range.

This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com>
from AMCC and slighly changed.

Signed-off-by: Pravin M. Bathija <pbathija@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-06 05:58:43 +01:00
Stefan Roese
e15e33433e ppc4xx: Kilauea: Add PCIe reset assertion upon power-up
This manual PCIe reset triggering solves the problem seen with the
Intel EPRO/1000 card, which was not detected (link not established)
upon power-up reset.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-30 07:15:41 +01:00
Stefan Roese
ecdcbd4f8c ppc4xx: Update AMCC Makalu for board rev 1.1
This patch adds changes needed for Makalu rev 1.1:

- Enable 2nd DDR2 bank resulting in 256MByte of SDRAM
- Enable 2nd ethernet port EMAC1
- Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE)
- Reset PCIe ports via GPIO upon bootup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-16 14:00:59 +01:00
Stefan Roese
c9672f81f1 ppc4xx: Small AMCC Kilauea cleanup
Remove not needed pci_target_init() function.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-15 14:25:09 +01:00
Stefan Roese
654f38b3a3 ppc4xx: Make output a little shorter on PCIe detection
Now not max 3 lines but 2 lines are printed per PCIe port.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-05 07:43:05 +01:00
Stefan Roese
3d6cb3b24a ppc4xx: Add AMCC Kilauea/Haleakala NAND booting support
This patch adds NAND booting support for the AMCC 405EX(r) eval boards.
Again, only one image supports both targets.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-03 12:08:28 +01:00
Stefan Roese
ea2e142843 ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files
and to the Sequoia TLB init code. Now the cache can be enabled on 44x
boards by defining CONFIG_4xx_DCACHE in the board config file. This
option will disappear, when more boards use is successfully and no
more known problems exist.

This is tested successfully on Sequoia and Katmai. The only problem that
needs to be fixed is, that USB is not working on Sequoia right now, since
it will need some cache handling code too, similar to the 4xx EMAC driver.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:47 +01:00
Stefan Roese
353f2688b4 ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board support
The Haleakala is nearly identical with the Kilauea eval board. The only
difference is that the 405EXr only supports one EMAC and one PCIe
interface. This patch adds support for the Haleakala board by using
the identical image for Kilauea and Haleakala. The distinction is done
by comparing the PVR.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Eugene O'Brien
9f798766aa ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAM
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting:

Note:
As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed
DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM
modules are still plugged in. So it is recommended to remove the DIMM
modules while using the NAND booting code with the fixed SDRAM setup!

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
882ae41274 ppc4xx: Rework of 4xx serial driver (2)
Change all linker scripts to reference the changed driver name 4xx_uart.o.

Note: In most cased all these explicit referencing of these object files
in the linker scripts is not neccessary. Only for manually embedded
environment into the U-Boot image, which is not done is most cases.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:51 +01:00
Stefan Roese
211ea91ac6 ppc4xx: Add initial AMCC Makalu 405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
087dfdb79b ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
770c7af580 ppc4xx: Fix size setup in Kilauea DDR2 init routine
The size was initilized wrong. Instead of 256MB, the DDR2 controller
was setup to 512MB. Now the correct values is used.

This patch also does a little cleanup and adds a comment here.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
d4cb2d1794 ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode
This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.

This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:

pcie_mode=RP:EP:EP

This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.

Per default Yucca will be configured as:
pcie_mode=RP:EP:EP

Per default Katmai will be configured as:
pcie_mode=RP:RP:REP

Per default Kilauea will be configured as:
pcie_mode=RP:RP

Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
fd671802b6 ppc4xx: Enable device tree support (fdt) on Kilauea per default
This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.

This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
566806ca1a ppc4xx: Add initial AMCC Kilauea 405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
026f711068 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(2) This patch renames the functions from 440spe_ to 4xx_ with a
    little additional cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
c7c6da2302 ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.

(1) This patch renames the files from 440spe_pcie to 4xx_pcie

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:48 +01:00
Stefan Roese
3e11ae80fe ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap command
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-18 07:44:56 +02:00
Stefan Roese
e2e93442e5 ppc4xx: Fix bug in I2C bootstrap values for Sequoia/Rainier
The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.

This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.

Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:

AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz

33MHz async PCI frequency:
PLB = 133:
=>      32 <= 44.3 <= 65        (div = 3)

PLB = 166:
=>      32 <= 55.3 <= 65        (div = 3)

66MHz async PCI frequency:
PLB = 133:
=>      65 <= 66.5 <= 132       (div = 2)

PLB = 166:
=>      65 <= 83 <= 132         (div = 2)

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-15 11:39:00 +02:00
Stefan Roese
5a5958b7de ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & Yosemite
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.

This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-15 11:29:33 +02:00
Stefan Roese
738815c0cc ppc4xx: Coding style cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-02 11:44:46 +02:00
Grzegorz Bernacki
2db6478406 Program EPLD to force full duplex mode for PHY.
EPLD forces modes of PHY operation. By default full duplex is turned off.
This fix turns it on.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-10-02 11:30:37 +02:00
Wolfgang Denk
1218abf1b5 Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as global
Signed-off-by: Wolfgang Denk <wd@denx.de>
2007-09-15 20:48:41 +02:00
Grzegorz Bernacki
6efc1fc0b6 [PPC440SPe] PCIe environment settings for Katmai and Yucca
- 'pciconfighost' is set by default in order to be able to scan bridges
behind the primary host/PCIe

- 'pciscandelay' env variable is recognized to allow for user-controlled
delay before the PCIe bus enumeration; some peripheral devices require a
significant delay before they can be scanned (e.g. LSI8408E); without the
delay they are not detected

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-07 18:35:37 +02:00
Grzegorz Bernacki
7f19139389 [PPC440SPe] Improve PCIe configuration space access
- correct configuration space mapping
- correct bus numbering
- better access to config space

Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-09-07 18:20:23 +02:00
Gary Jennejohn
81b73dec16 ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx Sequoia
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.

Here the details of this patch:

o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
  board-specific settings. As an example the sequoia board requires 0.
  Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
  PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
  CFG_PCI_CACHE_LINE_SIZE to 0.

Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-31 15:21:46 +02:00
Stefan Roese
02ba7022f6 ppc4xx: Update Sequoia/Rainier bootstrap command
As suggested by David Mitchell, here an update for the Sequoia/Rainier
bootstrap command.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-16 09:52:29 +02:00
Stefan Roese
34886bbea2 Merge with /home/stefan/git/u-boot/zeus 2007-08-14 15:00:42 +02:00
Stefan Roese
779e975117 ppc4xx: Add initial Zeus (PPC405EP) board support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-14 14:44:41 +02:00
Eugene OBrien
d2f6800662 ppc4xx: Update AMCC Bamboo 440EP support
Changed storage type of cfg_simulate_spd_eeprom to const
Changed storage type of gpio_tab to stack storage
(Cannot access global data declarations in .bss until afer code relocation)

Improved SDRAM tests to catch problems where data is not uniquely addressable
(e.g. incorrectly programmed SDRAM row or columns)

Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules
Fixed AM29LV320DT (OpCode Flash) sector map

Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-31 10:24:56 +02:00
John Otken
d4024bb72d ppc4xx: Add support for AMCC 405EP Taihu board
Signed-off-by: John Otken <john@softadvances.com>
2007-07-26 17:49:11 +02:00
Stefan Roese
2a49fc17d0 ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 10:01:38 +02:00
Stefan Roese
df3f17422a ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c
The new boardspecific DDR2 controller configuration is used for the Yucca
board. Now the Yucca board with 440SPe Rev. A chips is also supported.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 10:00:43 +02:00
Niklaus Giger
f780b83316 resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX
Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
2007-07-04 10:14:07 +02:00
Stefan Roese
e4feb7638c Merge with git://www.denx.de/git/u-boot.git 2007-06-25 20:20:30 +02:00
Stefan Roese
466fff1a7b ppc4xx: Add pci_pre_init() for 405 boards
This patch removes the CFG_PCI_PRE_INIT option completely, since
it's not needed anymore with the patch from Matthias Fuchs with
the "weak" pci_pre_init() implementation.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-25 15:57:39 +02:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Igor Lisitsin
a11e06965e Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.

Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
2007-06-22 23:21:01 +02:00
Stefan Roese
b3f9ec86e3 ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval board
This patch adds a board command to configure the I2C bootstrap EEPROM
values. Right now 533 and 667MHz are supported for booting either via NOR
or NAND FLASH. Here the usage:

=> bootstrap 533 nor        ;to configure the board for 533MHz NOR booting
=> bootstrap 667 nand       ;to configure the board for 667MHz NNAND booting

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-19 17:22:44 +02:00
Stefan Roese
df8a24cdd3 [ppc4xx] Fix problem with NAND booting on AMCC Acadia
The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-19 16:42:31 +02:00
Stefan Roese
86ba99e341 [ppc4xx] Change board/amcc/acadia/cpr.c to pll.c
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-19 16:40:58 +02:00
Stefan Roese
c440bfe6d6 ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.

Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.

I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:

=> bootstrap 267 nor	;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand	;to configure the board for 267MHz NNAND booting

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-06 11:42:13 +02:00
Stefan Roese
18d156eb37 ppc4xx: Add missing file for Bamboo NAND booting support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 16:18:17 +02:00
Stefan Roese
f3679aa13d Merge with /home/stefan/git/u-boot/bamboo-nand 2007-06-01 16:15:34 +02:00
Stefan Roese
155a96478a ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHz
This patch undoes the patch by Jeff Mann with commit-id ada4697d. As
suggested by AMCC it is not recommended to dynamically change the EBC
speed after bootup. So we undo this change to be on the safe side.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:58:19 +02:00
Stefan Roese
9d9096043e ppc4xx: Update Sequoia NAND booting support with ECC
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:29:04 +02:00
Stefan Roese
a471db07fb ppc4xx: Prepare Bamboo port for NAND booting support
This patch updates the "normal" Bamboo NOR booting port, so
that it is compatible with the coming soon NAND booting
Bamboo port.

It also enables the 2nd NAND flash on the Bamboo.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:19:29 +02:00
Stefan Roese
5d4a179013 ppc4xx: Update AMCC Acadia support for board revision 1.1
This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.

Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-24 08:22:09 +02:00
Jeffrey Mann
ada4697d02 [PATCH] Run new sequoia boards with an EBC speed of 83MHz
Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.

This allows for maximum clocking speeds  to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.

Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
2007-05-16 13:23:10 +02:00
Stefan Roese
f544ff6656 ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND booting
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
for the 4k NAND boot image so define bus_frequency to 133MHz here
which is save for the refresh counter setup.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-05 08:29:01 +02:00
Stefan Roese
8b39501d28 ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driver
Signed-off-by: Stefan Roese <sr@denx.de>
2007-04-29 14:13:01 +02:00
Stefan Roese
e673226ff9 ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROM
Signed-off-by: Stefan Roese <sr@denx.de>
2007-04-18 12:07:47 +02:00
Stefan Roese
a65c5768e5 ppc4xx: Change SysACE address on Katmai
With this new base address of the Xilinx SystemACE controller
the Linux driver will be easier to adapt, since it can now be
mapped via the "normal" ioremap() call.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-04-02 10:09:30 +02:00
Stefan Roese
0e7d4916af Merge with git://www.denx.de/git/u-boot.git 2007-03-31 13:44:12 +02:00
Stefan Roese
da6ebc1bc0 ppc4xx: Update Katmai bootstrap command
Now the DDR2 frequency is also 2*PLB frequency when 166MHz PLB
is selected.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-31 13:16:23 +02:00
Stefan Roese
490e5730c6 ppc4xx: Fix "bootstrap" command for Katmai board
The board specific "bootstrap" command is now fixed and can
be used for the AMCC Katmai board to configure different
CPU/PLB/OPB frequencies.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-31 08:47:34 +02:00
Stefan Roese
e50b791b3f Merge with /home/stefan/git/u-boot/acadia 2007-03-24 15:59:23 +01:00
Stefan Roese
0d974d5297 [PATCH] Add 4xx GPIO functions
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-24 15:57:09 +01:00
Stefan Roese
2db633658b [PATCH] Small Sequoia cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-24 15:55:58 +01:00
Stefan Roese
3cb86f3e40 [PATCH] Clean up 40EZ/Acadia support
This patch cleans up all the open issue of the preliminary
Acadia support.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-24 15:45:34 +01:00
Wolfgang Denk
2a8dfe0835 Code cleanup. Update CHANGELOG 2007-03-21 23:26:15 +01:00
Stefan Roese
fc1e45ce6e Merge with /home/stefan/git/u-boot/acadia 2007-03-21 14:38:25 +01:00
Stefan Roese
16c0cc1c82 [PATCH] Add AMCC Acadia (405EZ) eval board support
This patch adds support for the new AMCC Acadia eval board.

Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-21 13:39:57 +01:00
Stefan Roese
8423e5e31a [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval board
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-16 21:11:42 +01:00
Stefan Roese
992423ab43 ppc4xx: Fix file mode of sequoia.c
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 23:00:08 +01:00
John Otken john@softadvances.com
8ce16f55c7 ppc4xx: Clear Sequoia/Rainier security engine reset bits
Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
2007-03-08 22:49:22 +01:00
Wolfgang Denk
35ded29fd9 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-08 11:38:58 +01:00
Stefan Roese
cd84528f20 Merge with /home/stefan/git/u-boot/yucca-ddr2 2007-03-08 10:32:45 +01:00
Stefan Roese
00cdb4ce5e [PATCH] Update AMCC Luan 440SP eval board support
The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.

This patch also enables the cache in FLASH for the startup
phase of U-Boot (while running from FLASH). After relocating to
SDRAM the cache is disabled again. This will speed up the boot
process, especially the SDRAM setup, since there are some loops
for memory testing (auto calibration).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:13:16 +01:00
Stefan Roese
2f5df47351 [PATCH] Update AMCC Yucca 440SPe eval board support
The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:10:18 +01:00
Stefan Roese
2721a68a9e ppc4xx: Small AMCC Katmai 440SPe update
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:07:18 +01:00
Wolfgang Denk
46270c2851 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-07 16:50:34 +01:00
Stefan Roese
fa1aef15bc [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 16:43:00 +01:00
Stefan Roese
07b7b0037a [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.

For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06 07:47:04 +01:00
Stefan Roese
ba58e4c9a9 [PATCH] Update AMCC Katmai 440SPe eval board support
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.

Please note, that still some problems are left with some memory
configurations. See the driver for more details.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-01 21:11:36 +01:00
Stefan Roese
874bb7b88f [PATCH] Clean up Katmai (440SPe) linker script
Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 13:15:40 +01:00
Stefan Roese
4745acaa1a [PATCH] Add support for the AMCC Katmai (440SPe) eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:57:08 +01:00
Wolfgang Denk
c105f4c660 Merge with /home/sr/git/u-boot/denx-merge-sr 2007-01-30 17:32:15 +01:00
Stefan Roese
700200c67e [PATCH] Merge Yosemite & Yellowstone board ports
Now the AMCC eval boards Yosemite (440EP) and Yellowstone (440GR)
share one config file and all board specific files. This way we
don't have to maintain two different sets of files for nearly
identical boards.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-30 17:04:19 +01:00
Wolfgang Denk
a401239664 Minor code cleanup. 2007-01-19 23:08:39 +01:00
Stefan Roese
5fb692cae5 [PATCH] Add support for AMCC Taishan PPC440GX eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-18 10:25:34 +01:00
Wolfgang Denk
f11033e739 Merge with /home/hs/SC3/u-boot
Some code cleanup.
2007-01-15 13:41:04 +01:00
Stefan Roese
77ddc5b9af [PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.

Also the EBC initialising is now done via defines in the board config
file.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-13 07:59:56 +01:00
Stefan Roese
36adff362c [PATCH] Update Yosemite (440EP) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.

Also the EBC initialising is now done via defines in the board config
file.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-13 07:59:19 +01:00
Stefan Roese
e0b9ea8c8a [PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speed
Now the board revision and the current PCI bus speed are printed after
the board message.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-13 07:57:51 +01:00
Stefan Roese
a78bc443ae [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)
This fix will make the MAL burst disabling patch for the Linux
EMAC driver obsolete.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05 10:40:36 +01:00
Stefan Roese
0238898382 [PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
This code will optimize the DDR2 controller setup on a board specific
basis.

Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05 10:38:05 +01:00
Stefan Roese
1b3c360c23 [PATCH] Fix sequoia flash autodetection (finally correct)
Now 32MByte and 64MByte FLASH is know to work and other
configurations should work too.

Signed-off-by: Stefan Roese <sr@denx.de>
2006-12-22 14:29:40 +01:00
Stefan Roese
dfc8a9ee00 Merge with /home/stefan/git/u-boot/denx 2006-11-10 07:48:47 +01:00
Marian Balakowicz
8318fbf8cc Fix sequoia separate object direcory building problems. 2006-10-23 22:17:05 +02:00
Wolfgang Denk
2b208f5308 Move "ar" flags to config.mk to allow for silent "make -s"
Based on patch by Mike Frysinger, 20 Jun 2006
2006-10-09 01:02:05 +02:00
Wolfgang Denk
511d0c72b8 Coding style cleanup 2006-10-09 00:42:01 +02:00
Stefan Roese
f3443867e9 Add CONFIG_BOARD_RESET to configure board specific reset function
Patch by Stefan Roese, 07 Oct 2006
2006-10-07 11:30:52 +02:00
Stefan Roese
56fb6ba179 Fix TLB setup for Ocotea board
Patch by Stefan Roese, 30 Sep 2006
2006-10-04 07:12:49 +02:00
Stefan Roese
d373325efd Fix reset problem in sequoia sdram init code
Patch by Stefan Roese, 23 Sep 2006
2006-10-04 07:12:27 +02:00
Stefan Roese
854bc8da75 Add support for AMCC Rainier PPX440GRx eval board
Patch by Stefan Roese, 13 Sep 2006
2006-09-13 13:56:49 +02:00
Stefan Roese
d12ae80889 Add NAND environment support for PPC440EPx Sequoia NAND boot config
Patch by Stefan Roese, 12 Sep 2006
2006-09-12 20:19:10 +02:00
Stefan Roese
887e2ec9ec Add support for AMCC Sequoia PPC440EPx eval board
- Add support for PPC440EPx & PPC440GRx
- Add support for PPC440EP(x)/GR(x) NAND controller
  in cpu/ppc4xx directory
- Add NAND boot functionality for Sequoia board,
  please see doc/README.nand-boot-ppc440 for details
- This Sequoia NAND image doesn't support environment
  in NAND for now. This will be added in a short while.
Patch by Stefan Roese, 07 Sep 2006
2006-09-07 11:51:23 +02:00
Wolfgang Denk
6741ae92f3 Merge with /home/m8/git/u-boot 2006-09-04 01:03:57 +02:00
Marian Balakowicz
f93286397e Add support for a saving build objects in a separate directory.
Modifications are based on the linux kernel approach and
support two use cases:

  1) Add O= to the make command line
  'make O=/tmp/build all'

  2) Set environement variable BUILD_DIR to point to the desired location
  'export BUILD_DIR=/tmp/build'
  'make'

The second approach can also be used with a MAKEALL script
'export BUILD_DIR=/tmp/build'
'./MAKEALL'

Command line 'O=' setting overrides BUILD_DIR environent variable.

When none of the above methods is used the local build is performed and
the object files are placed in the source directory.
2006-09-01 19:49:50 +02:00
Stefan Roese
2b393b0f0a PCIe endpoint support for AMCC Yucca 440SPe board
Patch by Tirumala R Marri, 26 Aug 2006
2006-08-29 08:05:15 +02:00
Stefan Roese
f5577aae4a Improve DIMM detection for AMCC Yucca 440SPe board
Improved the memory DIMM detection for the Yucca 440SPe board for
the case where a memory DIMM is falsely detected as present.

This issue is seen on some AMCC Yucca 440SPe validation boards if
only one 512MB memory DIMM is installed, i.e. DIMM slot 0 is
populated and DIMM slot 1 is empty.  In this case, U-Boot does
not correctly detect that there is only one DIMM memory module
installed and will falsely detect two DIMM memory modules are
present and therefore U-Boot will not calculate the correct amount
of total memory and u-boot will not booting up.

Patch by Adam Graham, 24 Aug 2006
2006-08-29 08:04:32 +02:00
Wolfgang Denk
16850919ff Code cleanup 2006-08-27 18:10:01 +02:00
Wolfgang Denk
c72d9c5285 Merge with /home/sr/git/u-boot/denx 2006-08-13 02:25:32 +02:00
Wolfgang Denk
7213859d11 Merge with /home/raj/git/u-boot 2006-08-11 18:19:53 +02:00
Rafal Jaworowski
36b904a7fd Fix PCI-Express on PPC440SPe rev. A. 2006-08-11 12:35:52 +02:00
Wolfgang Denk
d10afb3916 Merge with /home/raj/git/u-boot 2006-08-10 15:40:49 +02:00
Rafal Jaworowski
692519b1ed Add support for PCI-Express on PPC440SPe (Yucca board). 2006-08-10 12:43:17 +02:00
Stefan Roese
9ede3cc511 Add Macronix MXLV320T flash support for AMCC Bamboo
Patch by Stefan Roese, 07 Aug 2006
2006-08-07 14:31:21 +02:00
Stefan Roese
a2c95a7224 PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
2006-07-28 18:34:58 +02:00
Stefan Roese
193dd95834 AMCC bamboo (440EP) U-Boot image reduced to 384kbyte
Please see doc/README.bamboo for details.
Patch by Stefan Roese, 27 Jul 2006
2006-07-27 16:14:05 +02:00
Wolfgang Denk
b87dfd2854 Add support for TB5200 board
The TB5200 ("Tinybox") is a small baseboard for the TQM5200 module
integrated in a little aluminium case.
Patch by Martin Krause, 8 Jun 2006

Some code cleanup
2006-07-19 13:50:38 +02:00
Marian Balakowicz
d19206b9a5 Fix AMCC bamboo eval board compilation errors. 2006-07-04 01:27:46 +02:00
Marian Balakowicz
fe84b48a94 Cleanup config file and bootup output for Yucca board. 2006-07-03 23:42:36 +02:00
Marian Balakowicz
f6e5739a68 Merge: Add support for AMCC 440SPe CPU based eval board (Yucca). 2006-06-30 18:19:42 +02:00
Marian Balakowicz
6c5879f380 Add support for AMCC 440SPe CPU based eval board (Yucca). 2006-06-30 16:30:46 +02:00
Wolfgang Denk
b9b2480f4f Correct GPIO setup (UART1/IRQ's) on yosemite & yellowstone
Patch by Stefan Roese, 29 May 2006
2006-05-30 17:45:30 +02:00
Wolfgang Denk
b28a31ca02 Merge with /home/m8/git/u-boot 2006-04-12 12:26:32 +02:00
Marian Balakowicz
6db3970811 Fix JFFS2 support for legacy NAND driver.
Some more NAND cleanup and small fixes.
2006-04-08 19:08:06 +02:00
Wolfgang Denk
d87080b721 GCC-4.x fixes: clean up global data pointer initialization for all boards. 2006-03-31 18:32:53 +02:00
Wolfgang Denk
bfc81252c0 Minor code cleanup 2006-03-06 13:03:37 +01:00
Bartlomiej Sieka
addb2e1650 Re-factoring the legacy NAND code (legacy NAND now only in board-specific
code and in SoC code). Boards using the old way have CFG_NAND_LEGACY and
BOARDLIBS = drivers/nand_legacy/libnand_legacy.a added. Build breakage for
NETTA.ERR and NETTA_ISDN - will go away when the new NAND support is
implemented for these boards.
2006-03-05 18:57:33 +01:00
Stefan Roese
81a3170b15 Changes to Yellowstone & Yosemite 440EP/GR eval boards:
- Changed GPIO setup to enable another address line in order to
  address 64M of FLASH.
- Added function sdram_tr1_set to auto calculate the tr1 value for
  the DDR.
Patch by Steven Blakeslee, 12 Dec 2005
2005-12-15 09:43:12 +01:00
Wolfgang Denk
7481266e4e 2005-12-12 16:06:05 +01:00
Stefan Roese
6e7fb6eaa5 Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
Patch by John Otken, 23 Nov 2005
2005-11-29 18:18:21 +01:00
Stefan Roese
1178a412d2 Minor AMCC 4xx board cleanups
Patch by Stefan Roese, 27 Nov 2005
2005-11-29 18:17:41 +01:00
Stefan Roese
3d9569b232 Changed PPC44x startup message (cpu info, speed...) to common style:
On PPC44x platforms, the startup message generated in "cpu.c" only
comprised the ppc type and revision but not additional informations
like speed etc. Those speed infos where printed in the board specific
code. This new implementation now prints all CPU infos in the common
cpu specific code. No board specific code is needed anymore and
therefore removed from all current 44x implementations.

Patch by Stefan Roese, 27 Nov 2005
2005-11-27 19:36:26 +01:00
Stefan Roese
fd49bf0214 Fix Bamboo DDR SDRAM initialization (problem with onboard SDRAM)
Patch by Stefan Roese, 15 Nov 2005
2005-11-15 16:04:58 +01:00
Stefan Roese
f190c11b1f Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
Patch by Stefan Roese, 05 Nov 2005
2005-11-05 15:50:16 +01:00
Stefan Roese
ef04a0aa26 Additional fix for external IRQ config on Yellowstone & Yosemite
Patch by Stefan Roese, 03 Nov 2005
2005-11-03 08:31:33 +01:00
Stefan Roese
57275b69c6 Add support for Ocotea pass 3 with 440GX Rev. F
Patch by Stefan Roese, 01 Nov 2005
2005-11-01 10:08:03 +01:00
Stefan Roese
e190290ba4 Fix external IRQ configuration on Yellowstone & Yosemite
The multiplexed signals Ext IRQ0...3 have to be configured as IRQ,
because they default to GPIOx (440EP/GR).

Patch by Stefan Roese, 28 Oct 2005
2005-10-28 12:21:06 +02:00
Wolfgang Denk
77ddac9480 Cleanup for GCC-4.x 2005-10-13 16:45:02 +02:00
Stefan Roese
93b17ec382 Change board message on AMCC Yosemite & Yellowstone to common style
Patch by Stefan Roese, 3 Oct 2005
2005-10-03 15:27:50 +02:00
Wolfgang Denk
0c8721a466 Cleanup (PPC4xx is AMCC now) 2005-09-23 11:05:55 +02:00
Stefan Roese
34c0a5e98b Update AMCC Yosemite to get a consistent setup for all AMCC eval
boards (baudrate, environment...). Flash driver fixed.
Patch by Stefan Roese, 15 Sep 2005
2005-09-15 11:34:07 +02:00
Wolfgang Denk
807d5d7319 Fix problems with ld version 2.16 (dot outside sections problem)
Pointed out by Gerhard Jaeger, 31 Aug 2005;
cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
2005-08-31 12:28:00 +02:00
Stefan Roese
d6c61aabc4 Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
now handling all 4xx cpu's.
Patch by Stefan Roese, 16 Aug 2005
2005-08-16 18:18:00 +02:00
Stefan Roese
84286386a8 Update AMCC Yosemite to get a consistent setup for all AMCC eval
boards (baudrate, environment...). Flash driver fixed.
Patch by Stefan Roese, 11 Aug 2005
2005-08-11 18:03:14 +02:00
Stefan Roese
c57c7980ff Add NAND FLASH support for AMCC Bamboo 440EP eval board
Patch by Stefan Roese, 11 Aug 2005
2005-08-11 17:56:56 +02:00
Wolfgang Denk
f901a83b70 Add support for ep8248 board
Patch by Yuli Barcohen, 12 Dec 2004

Minor code cleanup.
2005-08-06 01:42:58 +02:00
Stefan Roese
17f50f22bc Add support for AMCC Bamboo PPC440EP eval board
Patch by Stefan Roese, 04 Aug 2005
2005-08-04 17:09:16 +02:00
Wolfgang Denk
dc17fb6dc2 Cleanup build problems (on Fedora Core x86_64 build host) 2005-08-03 22:32:02 +02:00
Stefan Roese
8a316c9b62 Major cleanup for AMCC PPC4xx eval boards.
Patch by Stefan Roese, 01 Aug 2005
2005-08-01 16:49:12 +02:00
Stefan Roese
c157d8e219 Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone.
Patch by Steven Blakeslee, 27 Jul 2005
2005-08-01 16:41:48 +02:00