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[PPC440SPe] PCIe environment settings for Katmai and Yucca
- 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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7f19139389
commit
6efc1fc0b6
4 changed files with 28 additions and 2 deletions
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@ -396,6 +396,8 @@ void pcie_setup_hoses(int busno)
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{
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struct pci_controller *hose;
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int i, bus;
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char *env;
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unsigned int delay;
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/*
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* assume we're called after the PCIX hose is initialized, which takes
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@ -439,6 +441,16 @@ void pcie_setup_hoses(int busno)
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*/
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#else
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ppc440spe_setup_pcie_rootpoint(hose, i);
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env = getenv ("pciscandelay");
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if (env != NULL) {
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delay = simple_strtoul (env, NULL, 10);
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if (delay > 5)
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printf ("Warning, expect noticable delay before PCIe"
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"scan due to 'pciscandelay' value!\n");
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mdelay (delay * 1000);
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}
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/*
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* Config access can only go down stream
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*/
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@ -850,6 +850,8 @@ void pcie_setup_hoses(int busno)
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{
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struct pci_controller *hose;
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int i, bus;
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char *env;
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unsigned int delay;
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/*
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* assume we're called after the PCIX hose is initialized, which takes
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@ -895,6 +897,16 @@ void pcie_setup_hoses(int busno)
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*/
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#else
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ppc440spe_setup_pcie_rootpoint(hose, i);
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env = getenv ("pciscandelay");
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if (env != NULL) {
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delay = simple_strtoul (env, NULL, 10);
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if (delay > 5)
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printf ("Warning, expect noticable delay before PCIe"
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"scan due to 'pciscandelay' value!\n");
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mdelay (delay * 1000);
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}
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/*
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* Config access can only go down stream
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*/
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@ -201,6 +201,7 @@
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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"kozio=bootm ffc60000\0" \
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"pciconfighost=1\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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@ -322,7 +323,7 @@
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT /* let board init pci target */
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@ -182,6 +182,7 @@
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"cp.b ${fileaddr} FFFB0000 ${filesize};" \
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"setenv filesize;saveenv\0" \
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"upd=run load;run update\0" \
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"pciconfighost=1\0" \
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""
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#define CONFIG_BOOTCOMMAND "run flash_self"
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@ -297,7 +298,7 @@
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT /* let board init pci target */
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