Extend the padding process of u-boot-nand.imx target by adding 10k bytes
of zeros to the end of the binary using the 'dd' command.
The existing padding method did not generate a functional binary,
as discussed in more detail in this thread [1]. Instead, we adopt the
end-padding calculation method documented in 'board/doc/colibri_imx7.rst'
as a reference, which is relevant for iMX7 with NAND storage.
Adding 10k bytes of zeros provides an approximate value that makes the
proper padding for these NAND devices.
[1] https://lore.kernel.org/all/CAC4tdFUqffQzRQFv5AGe_xtbFy1agr2SEpn_FzEdexhwjdryyw@mail.gmail.com/
Signed-off-by: Hiago De Franco <hiago.franco@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
These IS_ENABLED(CONFIG_SPL_LOAD_FIT) cases can no longer be reached,
and thus get_fit_image_size() is also redundant.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Currently, spl_imx_romapi uses a somewhat tricky workaround for the
fact that a FIT image with external data doesn't directly allow one to
know the full size of the file: It does a dummy spl_load_simple_fit(),
having the ->read callback remember the largest offset requested, and
then does a last call to rom_api_download_image() to fetch the
remaining part of the full FIT image.
We can avoid that by just keeping track of how much we have downloaded
already, and if the ->read() requests something outside the current
valid buffer, fetch up to the end of the current request.
The current method also suffers from not working when CONFIG_IMX_HAB
is enabled: While in that case u-boot.itb is not built with external
data, so the fdt header does contain the full size of the dtb
structure. However, it does not account for the extra CONFIG_CSF_SIZE
added by board_spl_fit_size_align(). And also, the data it hands out
during the first dummy spl_load_simple_fit() is of course garbage, and
wouldn't pass the verification.
So we really need to call spl_load_simple_fit() only once, let that
figure out just how big the FIT image is (including whatever data, CSF
or "ordinary" external data, has been tacked on beyond the fdt
structure), and always provide valid data from the ->read callback.
This only affects the CONFIG_SPL_LOAD_FIT case - I don't have any
hardware or experience with the CONFIG_SPL_LOAD_IMX_CONTAINER case, so
I leave that alone for now.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
The hab signing script doc/imx/habv4/csf_examples/mx8m/csf.sh does
fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset
to figure out the offset of u-boot.itb inside flash.bin. That works
fine for imx8mm, imx8mn, imx8mq, but fails for imx8mp because in that
case 'uboot' is merely a label and not actually the node name.
Homogenize these cases and make imx8mp the same as the other imx8m*
variants. The binman type is explicitly given and no longer derived
from the node name, and the csf.sh script will work for all four SOCs.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
If optee is detected configure it in the Linux device-tree:
- add /firmware/optee node
- add /reserved-memory nodes for optee_core and optee_shm
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Move the crypto and sec_jr* nodes from board-specific
u-boot.dtsi files into the common files. Additionally protect the
nodes with ifdef CONFIG_FSL_CAAM as they don't serve any purpose if
that is not enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
There is no need to include the firmware/optee node if the optee
driver is not enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Move the firmware/optee node to the common imx8mp-u-boot.dtsi and
protect it with an ifdef CONFIG_OPTEE as it is a meaningless node
without the optee driver enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Move the firmware/optee node to the common imx8mm-u-boot.dtsi and
protect it with an ifdef CONFIG_OPTEE as it is a meaningless node
without the optee driver enabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Enable USB SDP SPL aka serial downloader recovery mode support.
While at it also enable fastboot support which may be used to
subsequently load further stages like a Toradex Easy Installer FIT
image.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Update the imx8mp-venice-gw74xx for revB:
- add CAN1
- add TIS-TPM on SPI2
- add FAN controller
- fix PMIC I2C bus (revA PMIC I2C was non-functional so no need for
backward compatible option)
- M2 socket GPIO's moved
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mm-venice-gw7905-0x consists of a SOM + baseboard.
The GW700x SOM contains the following:
- i.MX8M Mini SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- RGMII PHY
- PMIC
- SOM connector providing:
- FEC GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 2.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW7905 Baseboard contains the following:
- GPS
- microSD
- off-board I/O connector with I2C, SPI, GPIO
- EERPOM
- PCIe clock generator
- 1x full-length miniPCIe socket with PCI/USB3 (via mux) and USB2.0
- 1x half-length miniPCIe socket with USB2.0 and USB3.0
- USB 3.0 HUB
- USB Type-C with USB PD Sink capability and peripheral support
- USB Type-C with USB 3.0 host support
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mp-venice-gw73xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW73xx Baseboard contains the following:
- 1x RJ45 GbE (eQoS from SOM)
- 1x RJ45 GbE (PCI)
- off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
- off-board I/O connector with RS232/RS485
- off-board I/O connector with SPI
- off-board I/O connector with I2C, UART, and GPIO
I2C, I2S and GPIO
- microSD (1.8V/3.3V)
- GPS
- Accelerometer
- EERPOM
- USB 3.0 Hub
- Front Panel bi-color LED
- re-chargeable battery (for RTC)
- PCIe clock generator
- PCIe switch
- on-board 802.11abgnac 1x1 WiFi and Bluetooth 5.2
- 1x USB Type-A host socket with USB 3.0 support
- 1x USB OTG with USB 2.0 support
- 2x MiniPCIe socket with PCI and USB 2.0
- 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks imx8mp-venice-gw72xx-2x consists of a SOM + baseboard.
The GW702x SOM contains the following:
- i.MX8M Plus SoC
- LPDDR4 memory
- eMMC Boot device
- Gateworks System Controller (GSC) with integrated EEPROM, button
controller, and ADC's
- PMIC
- SOM connector providing:
- eQoS GbE MII
- 1x SPI
- 2x I2C
- 4x UART
- 2x USB 3.0
- 1x PCI
- 1x SDIO (4-bit 3.3V)
- 1x SDIO (4-bit 3.3V/1.8V)
- GPIO
The GW72xx Baseboard contains the following:
- 1x RJ45 GbE (eQoS from SOM)
- 1x RJ45 GbE (PCI)
- off-board I/O connector with MIPI-CSI (3-lane), MIPI-DSI (4-lane),
- off-board I/O connector with RS232/RS485
- off-board I/O connector with SPI
- off-board I/O connector with I2C, UART, and GPIO
I2C, I2S and GPIO
- microSD (1.8V/3.3V)
- GPS
- Accelerometer
- EERPOM
- USB 3.0 Hub
- Front Panel bi-color LED
- re-chargeable battery (for RTC)
- PCIe clock generator
- PCIe switch
- 1x USB Type-A host socket with USB 3.0 support
- 1x USB OTG with USB 2.0 support
- 1x MiniPCIe socket with PCI and USB 2.0
- 1x MiniPCIe socket with SIM, PCI/USB 3.0 (mux), and USB 2.0
- Wide range DC input supply
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Linux microPlatform uses an rngb device in optee-os in boot scheme
SPL -> OPTEE -> U-Boot. To make rngb available for optee-os, enable
it in SPL.
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
With enabled SKIP_LOWLEVEL_INIT, the weak function timer_init() is
used in the SPL build. For iMX6 SoC, this leads MMC to fail once
u-boot proper is booted due to a timing issue.
Always use iMX-specific timer_init() in SPL to fix timing issues.
Fixes: be277c3a89 ("imx: mx7: avoid some initialization if low level is skipped")
Signed-off-by: Michael Scott <mike@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Now we have to use UCLASS_SM driver instead of
raw smc_call() function call.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921081346.22157-9-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
The common.h header should always be first, followed
by other headers in order, then headers with directories,
then local files.
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230921081346.22157-8-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
scan all entries in multi-device boot_targets
EFI empty-capsule support
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Merge tag 'dm-pull-13oct23' of https://source.denx.de/u-boot/custodians/u-boot-dm
improvements with dev_read_addr_..._ptr()
scan all entries in multi-device boot_targets
EFI empty-capsule support
SCMI base protocol is mandatory and doesn't need to be listed in a device
tree.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Adding SCMI base protocol makes it inconvenient to hold the agent instance
(udevice) locally since the agent device will be re-created per each test.
Just remove it and simplify the test flows.
The test scenario is not changed at all.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Any SCMI protocol may have its own channel.
Test this feature on sandbox as the necessary framework was added
in a prior commit.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
In sandbox scmi agent, channels are not used at all. But in this patch,
dummy channels are supported in order to test protocol-specific channels.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
A follow-up to commit 842fb5de42
("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer")
and commit 320a1938b6
("drivers: use devfdt_get_addr_index_ptr when cast to pointer").
In addition to using the *_ptr variants of these functions where the
address is cast to a pointer, this also changes devfdt_get_addr_*() to
dev_read_addr_*() in a few places. Some variable and field types are
changed from fdt_addr_t or phys_addr_t to void* where the cast was
happening later.
This patch fixes a number of compile warnings when building a 32bit
U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error
handling where the return value of dev_read_addr() etc. was checked for
NULL instead of FDT_ADDR_T_NONE.
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
sandbox_spl_defconfig with CONFIG_SPL_UNIT_TEST=n fails to build.
in function `spl_board_init':
arch/sandbox/cpu/spl.c:134:(.text.spl_board_init+0x4a):
undefined reference to `ut_run_list'
Add the missing configuration check.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
clk:
- remove additional compatible strings for Versal NET
net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies
pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration
test:
- add test case for pxe get
Xilinx:
- describe SelectMAP boot mode
Zynq:
- Fix nand description in DT
ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
description for other SC based boards
- k24 psu_init cleanup
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Merge tag 'xilinx-for-v2024.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2024.01-rc1 v3
clk:
- remove additional compatible strings for Versal NET
net:
- zynq_gem: Fix clock calculation for MDC for higher frequencies
pinctrl:
- core: Extend pinmux status buffere size
- zynqmp driver: Show also tristate configuration
test:
- add test case for pxe get
Xilinx:
- describe SelectMAP boot mode
Zynq:
- Fix nand description in DT
ZynqMP:
- DTS sync patches with kernel and also W=1 related fixes
- Add support for KD240, zcu670, e-a2197 with x-prc cards, SC revB/C with i2c
description for other SC based boards
- k24 psu_init cleanup
Make that condition more generic by checking if the memory controller
driver is enabled instead of using the EVM's config.
Signed-off-by: Dominik Haller <d.haller@phytec.de>
The following commit syncs the device tree from Linux tag
v6.6-rc1 to U-boot and fixes the following to be compatible with
the future syncs -
- Include k3-am68-sk-base-board.dts file
Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
include k3-am68-sk-base-board.dts for Linux fixes to propagate
to U-boot.
- Fixing the mcu_timer0
Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
- Fixing secure proxy nodes
Linux DT now have these nodes defined so remove them and rename to
use the Linux DT ones.
- Remove cpsw node
The compatible is now fixed and the node is not required in
-u-boot specifically
- Remove aliases and chosen node
Use these from Linux and don't override when not required.
- Remove /delete-property/ from sdhci nodes
We have the necessary clock and dev data so remove these.
- Remove dummy_clocks and fs_loader0
These weren't being used anywhere so remove it.
- Remove mcu_ringacc override
All these have been put in a single commit to not break the
bisectability.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
The following commit syncs the device tree from Linux tag
v6.6-rc1 to U-boot and fixes the following to be compatible with
the future syncs -
- Include k3-j721s2-common-proc-board.dts file
Remove the duplicated pinmuxes from r5 and -u-boot.dtsi files and
include k3-j721s2-common-proc-board.dts for Linux fixes to propagate
to U-boot.
- Fixing the mcu_timer0
Remove timer0 and use the mcu_timer0 defined in mcu-wakeup.dtsi
- Fixing secure proxy nodes
Linux DT now have these nodes defined so remove them and rename to
use the Linux DT ones.
- Remove cpsw node
The compatible is now fixed and the node is not required in
-u-boot specifically
- Remove aliases and chosen node
Use these from Linux and don't override when not required.
- Remove /delete-property/ from sdhci nodes
We have the necessary clock and dev data so remove these.
- Remove dummy_clocks and fs_loader0
These weren't being used anywhere so remove it.
- Remove mcu_ringacc override
All these have been put in a single commit to not break the
bisectability.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
mcu_timer0 is used by u-boot as the tick-timer. Add it to the soc
devices lsit so it an be enabled via the k3 power controller.
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
The update causes instability in am68-sk boards so revert the patch in
the meantime till fix is available.
This reverts commit f1edf4bb6a.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Sync j7200 dts with Linux 6.6-rc1
- k3-j7200-r5-common-proc-board.dts now inherits from
k3-j7200-common-proc-board.dts instead of k3-j7200-som-p0.dtsi. This
allows us to trim down the r5 file considerably by using existing
properties
- remove pimux nodes from r5 file
- remove duplicate nodes & node properties from r5/u-boot files
- mcu_timer0 now used instead of timer1
mcu_timer0 device id added to dev-data.c file in order to work
- remove cpsw node
This node is no longer required since the compatible is now fixed
- remove dummy_clock_19_2_mhz
This node wasn't being used anyhere, so it was removed
- remove dummy_clock_200mhz
main_sdhci0 & main_sdhci1 no longer need dummy clock for eMMC/SD
- fix secure proxy node
mcu_secproxy changed to used secure_prxy_mcu which is already
defined in k3-j7200-mcu-wakeup.dtsi
- removed &mcu_ringacc property override since they're present in
v6.6-rc1
Signed-off-by: Reid Tonking <reidt@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
mcu_timer0 is now used as the tick timer in u-boot, so this adds the
timer to the soc device list so it can be enabled via the k3 power
controller.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Reid Tonking <reidt@ti.com>
ao-secure node can be used to get information about the board,
so, for example, using show_board_info() we can get following
information for board with Meson A1 SoC:
SoC: Amlogic Meson A1 (A113L) Revision 2c:a (1:a)
Signed-off-by: Alexey Romanov <avromanov@salutedevices.com>
Link: https://lore.kernel.org/r/20231010100623.74475-3-avromanov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This patch adds basic clock driver for Amlogic A1 Family which supports
enabling/disabling some gates, getting frequencies and setting rate
with limited reparenting.
Signed-off-by: Igor Prusov <ivprusov@salutedevices.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230925155209.130671-3-ivprusov@salutedevices.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
All K3 boards now are secure by default, instead of setting this in each
defconfig, make it implied by the ARCH config.
The only exception is IOT2050, which I do not believe will have any
problems with being a TI_SECURE_DEVICE, but for now turn it off to keep
its config the same.
Signed-off-by: Andrew Davis <afd@ti.com>
Tested-by: Tom Rini <trini@konsulko.com>
As the code to switch an ARM core from secure to the non-secure state
needs to know the base address of the Generic Interrupt Controller
(GIC), we read an Arm Cortex defined system register that is supposed to
hold that base address. However there are SoCs out there that get this
wrong, and this CBAR register either reads as 0 or points to the wrong
address. To accommodate those systems, so far we use a macro defined in
some platform specific header files, for affected boards.
To simplify future extensions, replace that macro with a Kconfig variable
that holds this override address, and define a default value for SoCs
that need it.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Sam Edwards <CFSworks@gmail.com>
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.
Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.
Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.
Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Jan Kiszka <jan.kiszka@siemens.com>
Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.
Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Apple's M2 Ultra SoC are somewhat similar to the M1 Ultra but needs
a tweaked memory map as the M2 Pro/Max SoCs. USB, NVMe, UART, WDT
and PCIe are working with the existing drivers.
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
The ARMv8.5 architecture extension defines architectural RNDR/RNDRRS
system registers, that provide 64 bits worth of randomness on every
read. Since it's an extension, and implementing it is optional, there is
a field in the ID_AA64ISAR0_EL1 ID register to query the availability
of those registers.
Add a UCLASS_RNG driver that returns entropy via repeated reads from
those system registers, if the extension is implemented.
The driver always binds, but checks the availability in the probe()
routine.
This helps systems which suffer from low boot entropy, since U-Boot can
provide entropy via the generic UEFI entropy gathering protocol to the OS,
at an early stage.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
A53 U-Boot proper got broken because nodes marked as 'bootph-pre-ram'
are no longer available in U-Boot proper before relocation.
Fix this by marking all nodes in u-boot.dtsi as 'bootph-all'.
Fixes: 9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Since commit 9e644284ab ("dm: core: Report bootph-pre-ram/sram node
as pre-reloc after relocation") A53 u-boot proper is broken. This is
because nodes marked as 'bootph-pre-ram' are not available at u-boot
proper before relocation.
To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
Fixes: 69b19ca67b ("arm: dts: k3-j721e: Sync with v6.6-rc1")
Cc: Neha Francis <n-francis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Tom Rini <trini@konsulko.com> # J721E-EVM GP
Tested-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
This is now done using binman but this file was leftover and is now
unused, remove it.
Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Since commit 9e644284ab ("dm: core: Report bootph-pre-ram/sram node
as pre-reloc after relocation") A53 u-boot proper is broken. This is
because nodes marked as 'bootph-pre-ram' are not available at u-boot
proper before relocation.
To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Some functions are not used outside this file, so make them static.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
PPA was a secure firmware developed in-house which is no longer
supported and replaced by TF-A quite some years ago. Drop support
for it.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Use uintptr_t instead of phys_addr_t where appropriate, so passing the
addresses to writel() doesn't result in compile warnings when PHYS_64BIT
is set for 32bit builds (which is actually a useful configuration, as
the K3 SoC family boots from an R5 SPL, which may pass bank information
based on gd->bd->bi_dram to fdt_fixup_memory_banks() etc., so PHYS_64BIT
is needed for fixing up the upper bank).
Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
- None of the callers perform error checking and based on the non-empty
versions of this function, there's no checking to be done, so make
this a void.
- Add a default weak version of the function.
- Remove the empty versions of exynos_init now that we have a weak
version.
Signed-off-by: Tom Rini <trini@konsulko.com>
The SelectMAP configuration interface provides an 8-bit,
16-bit or 32-bit bidirectional data bus interface to the Versal FPGA
configuration logic that can be used for both configuration and readback.
A connected microcontoller to the SelectMAP interface can load boot
image with bitstream, TF-A (ARM Trusted Firmware) and U-Boot.
This commit adds the missing identification of the SelectMAP mode.
Signed-off-by: Polak, Leszek <LPolak@arri.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Michal Simek <michal.simek@amd.com>
Cc: Stefan Roese <sr@denx.de>
Link: https://lore.kernel.org/r/DU0PR07MB8419F7765892CDBCE7D559C5C8CFA@DU0PR07MB8419.eurprd07.prod.outlook.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
The board is sharing a lot of components with zcu208 but it contains
differet silicon and also several components are done differently.
The board has 4GB memory connected to PS and additional 4GB connected to
PL. Compare to zcu208 sata support has been dropped and only USB3.0 is
using GTR (lane2). Others GTRs are routed to connectors.
MIO configuration is also shared with zcu111.
The board is using si5381 chip compare to si5341 which is normally used.
And as of now there is no Linux driver for this chip. PS reference clock is
generated out of si570 chip which is also new approach compare to zcu208.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3b296ef0f52bd94e32bdeb6d1beee29ac85f00a2.1695808407.git.michal.simek@amd.com
VPXA2785(vp-x-a2785-00) is evaluation board which contains two PCIe-Edge
fingers, one for PCIe-B(gen5x8) and one for CPM(dual gen5x8, gen5x16).
Each of the ports can operate in endpoint or root port mode. This allows
the single card to be used for both root port, endpoint, and switch modes.
The board is designed in the similar manner as others Versal boards. It
means board also have ZynqMP Zu4 System Controller which is described in a
separate file.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/59d3b1f7e785bc65518b465e5122fd2787616a93.1695808407.git.michal.simek@amd.com
System controller revC is using ADI ethernet phy instead of TI because of
supply chain issues.
Describe reset assert and de-assert times to 10us and 5ms respectively
according to the datasheet. Also setup RGMII RX and TX delay values to
2400ps as per board bring up observations.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2790f6cede7485556d581ab8270dda477fa21522.1695808407.git.michal.simek@amd.com
System controllers are pretty much the same on the all boards that's why
use autodetection based on i2c eeprom. This should end up with having only
one BSP for all SCs with only DT overlays to cover different i2c
structures.
All MIOs are fixed by the spec that's why not a problem to description
pinctrl setting.
Apart from eth phy reset, it also set proper phy delays.
The TI DP83867 PHY datasheet says:
T1: Post RESET stabilization time == 195us
T3: Hardware configuration pins transition to output drivers == 64us
T4: RESET pulse width == 1us
So with a little overhead set 'reset-assert-us' to 100us (T4) and
'reset-deassert-us' to 280us (T1+T3).
NOTE: The tuning of TI DP83867 phy reset delay is derived from linux
upstream commit: 5dbadc848259(arm64: dts: fsl: add support for Kontron
pitx-imx8m board).
i2c structure on Xilinx Versal evaluation platforms contain a lot of
devices but also connection to connectors like SFP. Because of this
complicated structure with also all level shifters, i2c muxes, etc. not all
devices are able to reliably work on 400kHz even if they are compatible
with this speed. That's why set i2c frequency to 100KHz to increase
reliability of the i2c bus.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8092340f92144f0cc9096194198f227015bc013.1695808407.git.michal.simek@amd.com
Linux requires to describe nand structure under nand controller.
If it is not described nand device is not detected by Linux.
Error shown by Linux kernel:
pl35x-nand-controller e1000000.nand-controller: Incorrect number of NAND chips (0)
pl35x-nand-controller: probe of e1000000.nand-controller failed with error -22
When wired:
nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xda
nand: Micron MT29F2G08ABAEAWP
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/3fcd68ccdfed5e6c079681e3b29e06583ec8a375.1695378830.git.michal.simek@amd.com
The DPSUB DT bindings now specify ports to model the connections with
the programmable logic and the DisplayPort output. Add them to the
device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1c91420e90bc823d7529834c33438216857c7161.1695378830.git.michal.simek@amd.com
Some boards are using one mdio bus which holds multiple phys and also
boards are using mdio node for bus description. That's why there are cases
where address/size-cells are unnecessary which is also reported by make W=1
dtbs. That's why remove them from zynqmp.dtsi and let board DTSes to handle
it based on used description.
Error log:
/axi/ethernet@ff0e0000: unnecessary #address-cells/#size-cells without
"ranges" or child "reg" property
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/02f308c774d4f2a798a9a8c066824114a19841a7.1695378830.git.michal.simek@amd.com
All zynqmp boards have been already described via mdio node that's why also
convert the rest of the boards. With using mdio node there is an option to
add reset property for the whole mdio bus which is reflected by
's/phy-reset-gpios/reset-gpios/g' for some boards.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ff165281a70a38e2b76fee91e6255ce95ce8021b.1695378830.git.michal.simek@amd.com
- Add Board: rk3568 Bananapi R2Pro;
- Update pcie bifurcation support;
- dwc_eth_qos controller support for rk3568 and rk3588;
- Compressed binary support for U-Boot on rockchip platform;
- dts and config updates for different board and soc;
[ trini: Fix conflict on include/spl.h ]
Signed-off-by: Tom Rini <trini@konsulko.com>
A RK8XX PMIC is typically using i2c0 on RK356x devices. Add bootph-all
to required pinctrl nodes to simplify use of the prevent booting on
power plug-in option in SPL.
With the following Kconfig options and nodes in u-boot.dtsi the prevent
booting on power plug-in option can work in SPL.
CONFIG_ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_PINCTRL=y
CONFIG_SPL_PMIC_RK8XX=y
&i2c0 {
bootph-pre-ram;
};
&rk817 {
bootph-pre-ram;
regulators {
bootph-pre-ram;
};
};
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Sync the device tree for RK3588 series with Linux 6.6-rc1.
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add Bananapi R2 Pro board.
tested:
- sdcard
- both front usb-ports
- sata
- wan-port
lan-ports are connected to mt7531 switch where driver needs to be
separated from mtk ethernet-driver.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Add support for generating a LZMA-compressed U-boot binary with the
help of binman, if CONFIG_SPL_LZMA is selected.
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add support for generating a GZIP-compressed U-boot binary with the
help of binman, if CONFIG_SPL_GZIP is selected.
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
There is no support to initialize DRAM on rk3308 SoC using U-Boot
TPL or SPL, and therefore an external TPL binary must be used to
package a bootable u-boot-rockchip.bin image.
Default ROCKCHIP_EXTERNAL_TPL to yes if ROCKCHIP_RK3308.
Remove useless TPL_SERIAL.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add a minimal generic RK3566/RK3568 board that only have eMMC and SDMMC
enabled. This defconfig can be used to boot from eMMC or SD-card on most
RK3566/RK3568 boards that follow reference board design.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Enable missing PCIe Kconfig options now that PCIe bifurcation is fixed
to make use of the two on-board RTL8125B and the M.2 slot on NanoPi R5C
and NanoPi R5S.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Update and sync Kconfig options for NanoPi R5C and NanoPi R5S with other
RK3568 boards.
SPL_FIT_SIGNATURE is enabled to add a checksum validation of the FIT
payload, also add LEGACY_IMAGE_FORMAT to keep boot scripts working.
OF_SPL_REMOVE_PROPS, SPL_DM_SEQ_ALIAS and SPL_PINCTRL change ensure
pinctrl for eMMC, SD-card and UART2 is applied in SPL.
MMC_HS200_SUPPORT and SPL counterpart is enabled to speed up eMMC load
times from on-board eMMC 5.1 modules.
Drop remaining unused or unsupported options to sync with other RK3568
boards.
Also sync device tree from linux v6.4 and drop u-boot,spl-boot-order and
use the default from rk356x-u-boot.dtsi.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
The PCI helpers read only the base address for a PCI region. In some cases
the size is needed as well, e.g. to pass along to a driver which needs to
know the size of its register area.
Update the functions to allow the size to be returned. For serial, record
the information and provided it with the serial_info() call.
A limitation still exists in that the size is not available when OF_LIVE
is enabled, so take account of that in the tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
We should not read this unless requested. Make it conditional on the
option being provided.
Add some debugging to show the state being written.
Signed-off-by: Simon Glass <sjg@chromium.org>
This should not happen in the argument-parsing function. Move it to the
main program.
Add some debugging for reading/writing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Use the new SPL/TPL/VPL_SYS_MALLOC_F symbols to determine whether the
malloc pool exists.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Enable CONFIG_TPL_SYS_MALLOC_F for boards which have a non-zero value
for CONFIG_TPL_SYS_MALLOC_F_LEN
Note that the default is yes in most cases, so no changes are needed to
board defconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Enable CONFIG_SPL_SYS_MALLOC_F for boards which have a non-zero value
for CONFIG_SPL_SYS_MALLOC_F_LEN
Note that the default is yes in most cases, so no changes are needed to
board defconfig options.
Signed-off-by: Simon Glass <sjg@chromium.org>
Rename this so that SPL is first, as per U-Boot convention. Also add
PAYLOAD_ since this is where in memory the parameters for the payload
have been stored.
Signed-off-by: Simon Glass <sjg@chromium.org>
We like to put the SPL first so it is clear that it relates to SPL. Rename
various malloc-related options which have crept in, to stick to this
convention.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
+ ae350: modify memory layout and target name
+ ae350: use generic RISC-V timer driver in S-mode
+ Support bootstage report for RISC-V
+ Support C extension exception command for RISC-V
+ Add Starfive timer support
Sync k3-j721e DTS with kernel.org v6.6-rc1.
* Use mcu_timer0 defined in k3-j721e-mcu-wakeup.dtsi and remove
timer0, we have its clocks set up in clk-data now
* Remove hbmc node as support is buggy and needs to be fixed
* Remove aliases and chosen node, use them from Kernel
* Remove /delete-property/ and clock-frequency from sdhci,
usbss, and mcu_uart nodes as we have them in clk and dev data
* Remove dummy_clocks as they are not needed
* Remove cpsw node as it is not required since it has been fixed
in U-Boot
* Remove pcie nodes, they are not needed
* Remove mcu_i2c0 as it is used for tps659413 PMIC in j721e-sk
for which support is not yet added
* Change secproxy nodes to their Linux definitions
* Remove overriding of ti,cluster-mode in MAIN R5 to default to
lockstep mode same as Kernel
* Retain tps6594 node as TPS6594 PMIC support is still under
review in the Kernel [1], cleanup will be taken post its merge
[1] https://lore.kernel.org/all/20230810-tps6594-v6-0-2b2e2399e2ef@ti.com/
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Get rid of k3-j721e-r5-*-u-boot.dtsi as it is not
necessary. Change the inclusion hierarchy to be as follows:
k3-j721e-<board>.dts---
-
-->k3-j721e-r5-<board>.dts
-
k3-j721e-<board>-u-boot.dtsi---
Reason for explicitly mentioning the inclusion of -u-boot.dtsi in code
although it could've been automatically done by U-Boot is to resolve
some of the dependencies that R5 file requires.
Also remove duplicate phandles while making this shift as well as remove
firmware-loader as it serves no purpose without "phandlepart" property.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
When setting boot media to load the TIFS binary in legacy boot flow
(followed by J721E), get_timer() is called which eventually calls
dm_timer_init() to grab the tick-timer, which is mcu_timer0. Since we
need to set up the clocks before using the timer, move clk_k3 driver
probe before k3_sysfw_loader to ensure we have all necessary clocks set
up before.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
U-Boot uses mcu_timer0 as the tick-timer, so add it to device list.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since commit [1] A53 u-boot proper is broken. This is because nodes
marked as 'bootph-pre-ram' are not available at u-boot proper before
relocation.
To fix this we mark all nodes in u-boot.dtsi as 'bootph-all'.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Reported-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes below dts warnings:
<stdout>: Warning (reg_format): /bus@f4000/ethernet@8000000/mdio@f00/ethernet-phy@1:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
<stdout>: Warning (unit_address_vs_reg): /bus@f4000/ethernet@8000000/mdio@f00: node has a unit name, but no reg or ranges property
<stdout>: Warning (pci_device_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
<stdout>: Warning (simple_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
<stdout>: Warning (avoid_default_addr_size): /bus@f4000/ethernet@8000000/mdio@f00/ethernet-phy@1: Relying on default #address-cells value
<stdout>: Warning (avoid_default_addr_size): /bus@f4000/ethernet@8000000/mdio@f00/ethernet-phy@1: Relying on default #size-cells value
<stdout>: Warning (avoid_unnecessary_addr_size): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (unique_unit_address): Failed prerequisite 'avoid_default_addr_size'
<stdout>: Warning (msi_parent_property): /bus@f4000/bus@48000000/dma-controller@485c0100:msi-parent: Could not get phandle node for (cell 0)
<stdout>: Warning (msi_parent_property): /bus@f4000/bus@48000000/dma-controller@485c0000:msi-parent: Could not get phandle node for (cell 0)
<stdout>: Warning (phys_property): /bus@f4000/ethernet@8000000/ethernet-ports/port@2:phys: Could not get phandle node for (cell 0)
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move cbass_mcu node to -r5-sk.dts as it is only required
for R5 SPL.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
CPSW node needs PHY, MDIO, pinmux, DMA and INTC nodes.
USB and MMC nodes need pinmux.
Mark them as 'bootph-all' so they are available in all
pre-relocation phases.
Fixes below dts warning:
<stdout>: Warning (dmas_property): /bus@f4000/ethernet@8000000:dmas: Could not get phandle node for (cell 0)
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since commit [1] A53 u-boot proper is broken.
This is because nodes marked as 'bootph-pre-ram' are
not available at u-boot proper before relocation.
To fix this we mark all nodes in sk-u-boot.dtsi as
'bootph-all'.
Move vtt_supply and cbass_mcu node to -r5-evm.dts as
it is only required for R5 SPL.
[1]
9e644284ab ("dm: core: Report bootph-pre-ram/sram node as pre-reloc after relocation")
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
_ alignment with kernel DT v6.5 for stm32f429 and stm32f746
_ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco
STM32 MPU:
_ alignment with kernel DT v6.6-rc1
_ add RNG support for stm32mp13
_ add USB, USB boot and stm32prog command support for stm32mp13
_ add support of USART1 clock for stm32mp1
_ only print RAM and board code with SPL_DISPLAY_PRINT flag for
stm32mp1
_ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
for stm32mp15xx DHCOR
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Merge tag 'u-boot-stm32-20231004' of https://source.denx.de/u-boot/custodians/u-boot-stm
STM32 MCU:
_ alignment with kernel DT v6.5 for stm32f429 and stm32f746
_ rework way of displaying ST logo for stm32f746-disco and stm32f769-disco
STM32 MPU:
_ alignment with kernel DT v6.6-rc1
_ add RNG support for stm32mp13
_ add USB, USB boot and stm32prog command support for stm32mp13
_ add support of USART1 clock for stm32mp1
_ only print RAM and board code with SPL_DISPLAY_PRINT flag for
stm32mp1
_ rename update_sf to dh_update_sd_to_sf and add dh_update_sd_to_emmc
for stm32mp15xx DHCOR
[ Fix merge conflict at board/st/common/stm32mp_dfu.c ]
Signed-off-by: Tom Rini <trini@konsulko.com>
stm32mp135f-dk board has a type-c connector to retrieve the connection
state. For now, simply force an active peripheral mode in u-boot for
flashing.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Device tree alignment with Linux kernel v6.6.rc1.
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
commit 6b443faa313c519db755ff90be32758fd9c66453 Linux upstream.
This is a preparation patch for the upcoming support to manage CAN
peripherals in single configuration.
The addition ensures backwards compatibility.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230427204540.3126234-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 559a6e75b4bcf0fc9e41d34865e72cf742f67d8e Linux upstream.
Add pin configurations for using CAN controller on stm32f469-disco
board. They are located on the Arduino compatible connector CN5 (CAN1)
and on the extension connector CN12 (CAN2).
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230328073328.3949796-5-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 7355ad1950f41e755e6dc451834be3b94f82acd4 Linux upstream.
Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The
chip contains two CAN peripherals, CAN1 the primary and CAN2 the secondary,
that share some of the required logic like clock and filters. This means
that the secondary CAN can't be used without the primary CAN.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230328073328.3949796-4-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The patch applies the changes from Linux commit 10a970bc3ebfa ("ARM: dts:
stm32: support display on stm32f746-disco board") and removes the same
settings from stm32f746-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit e4e724099f04072053cf411456e3e9aae48c4af1 Linux upstream.
In the schematics of document UM1907, the power supply for the micro SD
card is the same 3v3 voltage that is used to power other devices on the
board. By generalizing the name of the voltage regulator, it can be
referenced by other nodes in the device tree without creating
misunderstandings.
This patch is preparatory for future developments.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The patch applies the changes from Linux commit 008ef8b3a1a00 ("Add LTDC
(Lcd-tft Display Controller) support") and removes the same settings
from stm32f746-disco-u-boot.dtsi.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit f0215440069c4fb12958d2d321e05faa2708a11d Linux upstream.
The patch adds support for touchscreen on the stm32f746-disco board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 7a5f349e592c254f3c1ac34665b6c3905576efc2 Linux upstream.
The patch replaces the number 12 with the appropriate numerical constant
already defined in the file stm32f7-rcc.h.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 0920ccdf41e3078a4dd2567eb905ea154bc826e6 Linux upstream.
Add support for bxcan (Basic eXtended CAN controller) to STM32F746. The
chip contains three CAN peripherals, CAN1 and CAN2 in dual peripheral
configuration and CAN3 in single peripheral configuration:
- Dual CAN peripheral configuration:
* CAN1: Primary bxCAN for managing the communication between a secondary
bxCAN and the 512-byte SRAM memory.
* CAN2: Secondary bxCAN with no direct access to the SRAM memory.
This means that the two bxCAN cells share the 512-byte SRAM memory and
CAN2 can't be used without enabling CAN1.
- Single CAN peripheral configuration:
* CAN3: Primary bxCAN with dedicated Memory Access Controller unit and
512-byte SRAM memory.
-------------------------------------------------------------------------
| features | CAN1 | CAN2 | CAN 3 |
-------------------------------------------------------------------------
| SRAM | 512-byte shared between CAN1 & CAN2 | 512-byte |
-------------------------------------------------------------------------
| Filters | 26 filters shared between CAN1 & CAN2 | 14 filters |
-------------------------------------------------------------------------
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230427204540.3126234-6-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
commit 011644249686f2675e142519cd59e81e04cfc231 Linux upstream.
Add pin configurations for using CAN controller on stm32f7.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/all/20230427204540.3126234-4-dario.binacchi@amarulasolutions.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
The Andes PLMT driver directly accesses the mtime MMIO region,
indicating its intended use in the M-mode boot stage. However,
since U-Boot proper (S-mode) also uses the PLMT driver, we need
to specifically mark the region as readable through PMPCFGx (or
S/U-mode read-only shared data region for Smepmp) in OpenSBI.
Granting permission for this case doesn't make sense. Instead,
we should use the generic RISC-V timer driver to read the mtime
through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER
config, which ensures that the PLMT driver is linked exclusively
against M-mode U-Boot or U-Boot SPL binaries.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Most boards don't enable the pre-console buffer. So we will not see any
early messages. OpenSBI 1.3 provides us with the debug console extension
that can fill this gap.
For S-Mode U-Boot enable CONFIG_DEBUG_UART by default.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Below warning can be occurred when CONFIG_BOOTSTAGE and
!CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED
for SPL build.
arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of
function 'bootstage_report'
46 | bootstage_report();
| ^~~~~~~~~~~~~~~~
| bootstage_error
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Synchronize RZ R8A774E1 RZ/G2H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize RZ R8A774C0 RZ/G2E DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize RZ R8A774B1 RZ/G2N DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Adam Ford <aford173@gmail.com>
Synchronize RZ R7S72100 RZ/A1 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A779G0 V4H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A779F0 S4 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A779A0 E3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77995 D3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Synchronize R-Car R8A77990 E3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
