Commit graph

88 commits

Author SHA1 Message Date
Scott Wood
dcc87dd58d ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.
Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-09-15 21:30:08 -05:00
Poonam Aggrwal
58442dc01e ppc/85xx,86xx: Handling Unknown SOC version
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Kumar Gala
26f4cdba6b 85xx: Add support for setting IVORs to fixed offset defaults
In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets.  The IVPR will continue to exist to allow
for relocation of the interrupt vectors.

This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Poonam Aggrwal
a713ba926b 85xx: Added single core members of FSL P1xx/P2xx processors series
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Poonam Aggrwal
87c7661b42 85xx: Added P1020 Processor Support.
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Poonam Aggrwal
0e870980a6 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Stefan Roese
89bcc48750 ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chips
This patch is based on a diff created by Phong Vo from AMCC.

Signed-off-by: Phong Vo <pvo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-30 07:22:18 +02:00
Matthias Fuchs
58ea142fb2 ppc4xx: Replace 4xx lowercase SPR references
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-24 06:47:17 +02:00
Kumar Gala
480f617905 86xx: Add CPU_TYPE_ENTRY support
Unify with 83xx and 85xx and use CPU_TYPE_ENTRY.  We are going to use
this to convey the # of cores and DDR width in the near future so its
good to keep in sync.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-30 08:24:22 -05:00
Kumar Gala
71b358cc26 85xx: Added MPC8535/E identifiers
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12 17:16:26 -05:00
Peter Tyser
0f89860494 83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xx
Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-06-12 20:47:17 +02:00
Haiying Wang
22b6dbc169 MPC85xx: Add MPC8569 CPU support
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30 13:33:51 -05:00
Peter Tyser
a1c8a71926 86xx: Update CPU info output on bootup
- Update style of 86xx CPU information on boot to more closely
  match 85xx boards
- Fix detection of 8641/8641D
- Use strmhz() to display frequencies
- Display L1 information
- Display L2 cache size
- Fixed CPU/SVR version output

== Before ==
Freescale PowerPC
CPU:
    Core: E600 Core 0, Version: 0.2, (0x80040202)
    System: Unknown, Version: 2.1, (0x80900121)
    Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz
    L2: Enabled
Board: X-ES XPedite5170 3U VPX SBC

== After ==
CPU:   8641D, Version: 2.1, (0x80900121)
Core:  E600 Core 0, Version: 2.2, (0x80040202)
Clock Configuration:
       CPU:1066.667 MHz, MPX:533.333 MHz
       DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz
L1:    D-cache 32 KB enabled
       I-cache 32 KB enabled
L2:    512 KB enabled
Board: X-ES XPedite5170 3U VPX SBC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
2009-02-16 18:05:57 -06:00
Srikanth Srinivasan
8d949aff38 mpc85xx: Add support for the P2020
Added various p2020 processor specific details:
* SVR for p2020, p2020E
* immap updates for LAWs and DDR on p2020
* LAW defines related to p2020

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:55 -06:00
Kumar Gala
f8523cb081 85xx: Fix how we map DDR memory
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-16 18:05:51 -06:00
Kumar Gala
ef50d6c06e mpc85xx: Add support for the MPC8536
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Dejan Minic <minic@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-08-27 11:43:54 -05:00
Ricardo Ribalda Delgado
d865fd0980 ppc4xx: CPU PPC440x5 on Virtex5 FX
-This patchs gives support for the embbedded ppc440
 on the Virtex5 FPGAs
-interrupts.c divided in uic.c and interrupts.c
-xilinx_irq.c for xilinx interrupt controller
-Include modifications propossed by  Stefan Roese

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Acked-by: Stefan Roese <sr@denx.de>
2008-07-18 12:30:50 +02:00
Stefan Roese
42246dacf6 Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next 2008-07-17 10:41:06 +02:00
Kumar Gala
7f9f4347cf 85xx: Add some L1/L2 SPR register definitions
Add new L1/L2 SPRs related to e500mc cache config and control.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14 20:19:59 -05:00
Kim Phillips
6b70ffb9d1 fdt: add crypto node handling for MPC8{3, 5}xxE processors
Delete the crypto node if not on an E-processor.  If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-07-14 17:01:29 -05:00
Feng Kan
96e5fc0e6a ppc4xx: Add initial 460SX reference board (redwood) config file and defines.
Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:12 +02:00
Kim Phillips
4890246a2c mpc83xx: move CPU_TYPE_ENTRY over to processor.h
to avoid this:

cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined
In file included from cpu.c:33:
/home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-06-25 16:34:29 -05:00
Anatolij Gustschin
96026d42fa Fix 4xx build issue
Building for 4xx doesn't work since commit 4dbdb768:

In file included from 4xx_pcie.c:28:
include/asm/processor.h:971: error: expected ')' before 'ver'
make[1]: *** [4xx_pcie.o] Error 1

This patch fixes the problem.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-19 22:48:45 +02:00
Wolfgang Denk
1730edf76c Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx 2008-06-11 22:13:07 +02:00
Kumar Gala
4dbdb7681e 85xx: expose cpu identification
The current cpu identification code is used just to return the name
of the processor at boot.  There are some other locations that the name
is useful (device tree setup).  Expose the functionality to other bits
of code.

Also, drop the 'E' suffix and add it on by looking at the SVR version
when we print this out.  This is mainly to allow the most flexible use
of the name.  The device tree code tends to not care about the 'E' suffix.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-10 18:22:25 -05:00
Grant Erickson
c821b5f120 ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling
This patch (Part 1 of 2):

* Rolls up a suite of changes to enable correct primordial stack and
  global data handling when the data cache is used for such a purpose
  for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by
  eliminating redundant ECC initialization implementations and moving
  redundant SDRAM initialization out of board code into shared 4xx
  code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on
  both AMCC's Kilauea and Makalu and removes a redundant
  CFG_POST_MEMORY flag from each board's CONFIG_POST value.

  - Removed, per Stefan Roese's request, defunct memory.c file for
    Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:20:50 +02:00
Stefan Roese
70fab1908f ppc4xx: Add 405EX(r) revision C PVR definitions and detection code
Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-13 20:22:01 +02:00
Wolfgang Denk
e6dfed705e ppc: Get rid of unused machine type definitions
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-13 10:03:54 -07:00
Wolfgang Denk
1aeed8d71a Coding Style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-04-13 09:59:26 -07:00
Andy Fleming
1ced121600 Update SVR numbers to expand support
FSL has taken to using SVR[16:23] as an SOC sub-version field.  This
is used to distinguish certain variants within an SOC family.  To
account for this, we add the SVR_SOC_VER() macro, and update the SVR_*
constants to reflect the larger value.  We also add SVR numbers for all
of the current variants.  Finally, to make things neater, rather than
use an enormous switch statement to print out the CPU type, we create
and array of SVR/name pairs (using a macro), and print out the CPU name
that matches the SVR SOC version.

Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26 11:43:04 -05:00
Stefan Roese
999ecd5aca ppc4xx: Add basic support for AMCC 460EX/460GT (3/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:04 +01:00
Kumar Gala
b009f3eca9 85xx: Remove cache config from configs.h
Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.

Also, minor cleanup in cache.h to make the code a bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-01-09 16:25:04 -06:00
Jon Loeliger
2c3536425d Merge commit 'wd/master' 2008-01-03 09:46:55 -06:00
Eugene O'Brien
f6ba9b5660 ppc4xx: Define CONFIG_BOOKE for all PPC440 based processors
CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
number is used to access system registers.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
dbbd125721 ppc4xx: Add PPC405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Jon Loeliger
9553df86d3 Initial mpc8610hpcd cpu/, README and include/ files.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-10-17 15:01:47 -05:00
Andy Fleming
61a21e980a 85xx start.S cleanup and exception support
From: Ed Swarthout <Ed.Swarthout@freescale.com>

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:34:21 -05:00
Ed Swarthout
2e4d94f1e3 fsl_pci_init cleanup.
Do not enable normal errors created during probe (master abort, perr,
and pcie Invalid Configuration access).

Add CONFIG_PCI_NOSCAN board option to prevent bus scan.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-10 11:39:37 -05:00
Jon Loeliger
cfc7a7f5bb cpu/86xx fixes.
Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-10 11:02:32 -05:00
Rafal Jaworowski
1863cfb7b1 [PPC] Remove unused MSR_USER definition
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-07-27 14:22:04 +02:00
Rafal Jaworowski
cc3023b9f9 Fix breakage of 8xx boards from recent commit.
This patch fixes the negative consequences for 8xx of the recent
"ppc4xx: Clean up 440 exceptions handling" commit.

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-07-19 17:12:28 +02:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Grzegorz Bernacki
efa35cf12d ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 11:19:28 +02:00
Grzegorz Wianecki
a9d87e2707 [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
message. Use PVR to distinguish between the two variants, and print proper CPU
information.

Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com>
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2007-05-05 21:35:03 +02:00
Andy Fleming
6743105988 Add support for the 8568 MDS board
This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-05-02 15:50:02 -05:00
Andy Fleming
81f481ca70 Enable 8544 support
* Add support to the Makefile
* Add 8544 configuration support to the tsec driver
* Add 8544 SVR numbers to processor.h

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-04-23 19:58:28 -05:00
Stefan Roese
e01bd218b0 [PATCH] Add AMCC PPC405EZ support
This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.

Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-21 13:38:59 +01:00
Stefan Roese
2902fadade [PATCH] Update 440EPx/440GRx cpu detection
Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-31 16:56:10 +01:00
Stefan Roese
95981778cf [PATCH] Update 440SP(e) cpu revisions
Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-13 08:01:03 +01:00
Stefan Roese
e732faec95 [PATCH] PPC4xx: 440SP Rev. C detection added
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-28 16:09:24 +01:00