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https://github.com/AsahiLinux/u-boot
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cpu/86xx fixes.
Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Jon Loeliger
parent
99c2fdab91
commit
cfc7a7f5bb
6 changed files with 65 additions and 102 deletions
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@ -104,8 +104,8 @@ void cpu_init_f(void)
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/* enable the timebase bit in HID0 */
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set_hid0(get_hid0() | 0x4000000);
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/* enable SYNCBE | ABE bits in HID1 */
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set_hid1(get_hid1() | 0x00000C00);
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/* enable EMCP, SYNCBE | ABE bits in HID1 */
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set_hid1(get_hid1() | 0x80000C00);
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}
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/*
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@ -8,7 +8,7 @@
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* (C) Copyright 2003 Motorola Inc. (MPC85xx port)
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2004 Freescale Semiconductor. (MPC86xx Port)
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* (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port)
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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@ -80,25 +80,10 @@ int interrupt_init(void)
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{
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int ret;
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/*
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* The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to
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* implement PEX10 errata. As INT is active high, it
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* will cause core to take 0x500 interrupt.
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*
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* Due to the PIC's default pass through mode, as soon
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* as interrupts are enabled (MSR[EE] = 1), an interrupt
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* will be taken and u-boot will hang. This is due to a
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* hardware change (per an errata fix) on new revisions
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* of the board with Rev 2.x parts.
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*
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* Setting the PIC to mixed mode prevents the hang.
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*/
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if ((get_svr() & 0xf0) == 0x20) {
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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immr->im_pic.gcr = MPC86xx_PICGCR_RST;
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while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
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immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
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}
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volatile immap_t *immr = (immap_t *)CFG_IMMR;
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immr->im_pic.gcr = MPC86xx_PICGCR_RST;
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while (immr->im_pic.gcr & MPC86xx_PICGCR_RST);
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immr->im_pic.gcr = MPC86xx_PICGCR_MODE;
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/* call cpu specific function from $(CPU)/interrupts.c */
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ret = interrupt_init_cpu(&decrementer_count);
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@ -119,6 +104,30 @@ int interrupt_init(void)
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get_msr(),
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get_dec());
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#ifdef CONFIG_INTERRUPTS
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volatile ccsr_pic_t *pic = &immr->im_pic;
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pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
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debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
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pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
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debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2);
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pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
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debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3);
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#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
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pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
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debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8);
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#endif
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#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
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pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
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debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9);
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#endif
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pic->ctpr = 0; /* 40080 clear current task priority register */
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#endif
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return 0;
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}
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@ -158,8 +167,6 @@ void timer_interrupt(struct pt_regs *regs)
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timestamp++;
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ppcDcbf((unsigned long)×tamp);
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/* Restore Decrementer Count */
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set_dec(decrementer_count);
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@ -1,5 +1,5 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright 2004, 2007 Freescale Semiconductor.
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* Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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@ -44,11 +44,9 @@
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#define CONFIG_IDENT_STRING ""
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#endif
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/* We don't want the MMU yet.
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*/
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#undef MSR_KERNEL
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/* Machine Check and Recoverable Interr. */
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#define MSR_KERNEL ( MSR_ME | MSR_RI )
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/*
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* Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
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*/
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/*
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* Set up GOT: Global Offset Table
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@ -195,17 +193,21 @@ boot_warm:
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bl secondary_cpu_setup
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#endif
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1:
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#ifdef CFG_RAMBOOT
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/* disable everything */
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1: li r0, 0
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li r0, 0
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mtspr HID0, r0
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sync
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mtmsr 0
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#endif
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bl invalidate_bats
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sync
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#ifdef CFG_L2
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/* init the L2 cache */
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addis r3, r0, L2_INIT@h
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lis r3, L2_INIT@h
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ori r3, r3, L2_INIT@l
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mtspr l2cr, r3
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/* invalidate the L2 cache */
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@ -241,69 +243,9 @@ in_flash:
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bl setup_ccsrbar
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#endif
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/* -- MPC8641 Rev 1.0 MCM Errata fixups -- */
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/* skip fixups if not Rev 1.0 */
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mfspr r4, SVR
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rlwinm r4,r4,0,24,31
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cmpwi r4,0x10
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bne 1f
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lis r3,MCM_ABCR@ha
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lwz r4,MCM_ABCR@l(r3) /* ABCR -> r4 */
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/* set ABCR[A_STRM_CNT] = 0 */
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rlwinm r4,r4,0,0,29
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/* set ABCR[ARB_POLICY] to 0x1 (round-robin) */
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addi r0,r0,1
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rlwimi r4,r0,12,18,19
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stw r4,MCM_ABCR@l(r3) /* r4 -> ABCR */
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sync
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/* Set DBCR[ERD_DIS] */
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lis r3,MCM_DBCR@ha
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lwz r4,MCM_DBCR@l(r3)
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oris r4, r4, 0x4000
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stw r4,MCM_DBCR@l(r3)
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sync
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1:
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/* setup the law entries */
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bl law_entry
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sync
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#if (EMULATOR_RUN == 1)
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/* On the emulator we want to adjust these ASAP */
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/* otherwise things are sloooow */
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/* Setup OR0 (LALE FIX)*/
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lis r3, CFG_CCSRBAR@h
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ori r3, r3, 0x5004
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li r4, 0x0FF3
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stw r4, 0(r3)
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sync
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/* Setup LCRR */
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lis r3, CFG_CCSRBAR@h
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ori r3, r3, 0x50D4
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lis r4, 0x8000
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ori r4, r4, 0x0002
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stw r4, 0(r3)
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sync
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#endif
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#if 1
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/* make sure timer enabled in guts register too */
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lis r3, CFG_CCSRBAR@h
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oris r3,r3, 0xE
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ori r3,r3,0x0070
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lwz r4, 0(r3)
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lis r5,0xFFFC
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ori r5,r5,0x5FFF
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and r4,r4,r5
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stw r4,0(r3)
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#endif
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/*
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* Cache must be enabled here for stack-in-cache trick.
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* This means we need to enable the BATS.
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@ -346,8 +288,6 @@ in_flash:
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#ifdef RUN_DIAG
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/* Sri: Code to run the diagnostic automatically */
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/* Load PX_AUX register address in r4 */
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lis r4, 0xf810
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ori r4, r4, 0x6
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@ -392,6 +332,7 @@ diag_done:
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.globl invalidate_bats
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invalidate_bats:
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li r0, 0
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/* invalidate BATs */
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mtspr IBAT0U, r0
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mtspr IBAT1U, r0
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@ -1040,6 +981,7 @@ trap_init:
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mfmsr r7
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li r8,MSR_IP
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andc r7,r7,r8
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ori r7,r7,MSR_ME /* Enable Machine Check */
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mtmsr r7
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mtlr r4 /* restore link register */
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@ -1224,8 +1166,9 @@ secondary_cpu_setup:
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sync
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isync
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/*SYNCBE|ABE in HID1*/
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/* MCP|SYNCBE|ABE in HID1 */
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mfspr r4, HID1
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oris r4, r4, 0x8000
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ori r4, r4, 0x0C00
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mtspr HID1, r4
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sync
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@ -130,8 +130,11 @@ MachineCheckException(struct pt_regs *regs)
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printf("Machine check in kernel mode.\n");
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printf("Caused by (from msr): ");
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printf("regs %p ", regs);
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switch (regs->msr & 0x000F0000) {
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case (0x80000000 >> 12):
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switch ( regs->msr & 0x001F0000) {
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case (0x80000000>>11):
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printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0));
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break;
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case (0x80000000>>12):
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printf("Machine check signal - probably due to mm fault\n"
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"with mmu off\n");
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break;
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@ -209,6 +212,7 @@ UnknownException(struct pt_regs *regs)
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if (debugger_exception_handler && (*debugger_exception_handler) (regs))
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return;
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#endif
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printf("UnknownException regs@%x\n", regs);
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printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
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regs->nip, regs->msr, regs->trap);
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_exception(0, regs);
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@ -1257,9 +1257,12 @@ typedef struct ccsr_gur {
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uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
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uint porbmsr; /* 0xe0004 - POR boot mode status register */
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#define MPC86xx_PORBMSR_HA 0x00060000
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#define MPC85xx_PORBMSR_HA 0x00070000
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uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
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uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
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#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
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#define MPC86xx_PORDEVSR_IO_SEL 0x000F0000
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#define MPC85xx_PORDEVSR_IO_SEL 0x00380000 /* 85xx platform type */
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#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */
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uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
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char res1[12];
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uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
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@ -1273,8 +1276,11 @@ typedef struct ccsr_gur {
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uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
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char res6[12];
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uint devdisr; /* 0xe0070 - Device disable control */
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#define MPC86xx_DEVDISR_PCIEX1 0x80000000
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#define MPC86xx_DEVDISR_PCIEX2 0x40000000
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#define MPC86xx_DEVDISR_PCIEX1 0x80000000
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#define MPC86xx_DEVDISR_PCIEX2 0x40000000
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#define MPC86xx_DEVDISR_PCI1 0x80000000
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#define MPC86xx_DEVDISR_PCIE1 0x40000000
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#define MPC86xx_DEVDISR_PCIE2 0x20000000
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char res7[12];
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uint powmgtcsr; /* 0xe0080 - Power management status and control register */
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char res8[12];
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@ -1282,7 +1288,9 @@ typedef struct ccsr_gur {
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char res9[12];
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uint pvr; /* 0xe00a0 - Processor version register */
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uint svr; /* 0xe00a4 - System version register */
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char res10[3416];
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char res10a[1880];
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uint clkdvdr; /* 0xe0800 - Clock Divide register */
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char res10b[1532];
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uint clkocr; /* 0xe0e00 - Clock out select register */
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char res11[12];
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uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
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@ -464,7 +464,8 @@
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#define ESR_ST 0x00800000 /* Store Operation */
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#if defined(CONFIG_MPC86xx)
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#define SPRN_MSSCRO 0x3f6
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#define SPRN_MSSCR0 0x3f6
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#define SPRN_MSSSR0 0x3f7
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#endif
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