mirror of
https://github.com/AsahiLinux/u-boot
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Coding Style cleanup; update CHANGELOG
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
parent
8c8428a576
commit
1aeed8d71a
22 changed files with 2130 additions and 291 deletions
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@ -29,4 +29,3 @@
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#
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TEXT_BASE = 0x8FFC0000
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@ -42,7 +42,6 @@
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.align 2
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lowlevel_init:
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mov.l CCR_A, r1 ! Address of Cache Control Register
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mov.l CCR_D, r0 ! Instruction Cache Invalidate
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mov.l r0, @r1
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@ -100,7 +99,6 @@ lowlevel_init:
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mov.l r0, @r1
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bsc_init:
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mov.l CMNCR_A, r1 ! CMNCR address -> R1
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mov.l CMNCR_D, r0 ! CMNCR data -> R0
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mov.l r0, @r1 ! CMNCR set
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@ -188,8 +186,6 @@ bsc_init:
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rts
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mov #0, r0
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.align 4
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CCR_A: .long CCR
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@ -266,4 +262,3 @@ PSCR_D: .word 0x0000
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RWTCSR_D_1: .word 0xA507
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RWTCSR_D_2: .word 0xA504 ! 20080115
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RWTCNT_D: .word 0x5A00
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@ -51,4 +51,3 @@ int dram_init (void)
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void led_set_state (unsigned short value)
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{
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}
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@ -103,4 +103,3 @@ SECTIONS
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PROVIDE (_end = .);
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}
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@ -50,11 +50,11 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
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}
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} else {
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if (info->iobase == CFG_FEC0_IOBASE) {
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gpio->par_feci2c &= ~0x0F00;
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gpio->par_fec0hl &= ~0xC0;
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gpio->par_feci2c &= ~0x0F00;
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gpio->par_fec0hl &= ~0xC0;
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} else {
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gpio->par_feci2c &= ~0x00A0;
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gpio->par_fec1hl &= ~0xC0;
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gpio->par_feci2c &= ~0x00A0;
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gpio->par_fec1hl &= ~0xC0;
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}
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}
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@ -67,7 +67,7 @@ int board_init(void)
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/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
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__raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
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/* OTH: (00) Other fuction
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* GPO: (01) General Purpose Output
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* GPI: (11) General Purpose Input
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@ -159,4 +159,3 @@ int dram_init(void)
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printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
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return 0;
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}
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@ -7,7 +7,7 @@
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*
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* Copyright (C) 2008
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* Mark Jonas <mark.jonas@de.bosch.com>
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*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -33,11 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
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/* We put these variables into .data section so that they are zero
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* when entering the AMBA Plug & Play routines (in cpu/cpu/ambapp.c)
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* the first time. BSS is not garantueed to be zero since BSS
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* the first time. BSS is not garantueed to be zero since BSS
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* hasn't been cleared the first times entering the CPU AMBA functions.
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*
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* The AMBA PnP routines call these functions if ambapp_???_print is set.
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*
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*
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*/
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int ambapp_apb_print __attribute__ ((section(".data"))) = 0;
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int ambapp_ahb_print __attribute__ ((section(".data"))) = 0;
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@ -199,7 +199,7 @@ int usb_stor_info(void)
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}
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return 0;
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}
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printf("No storage devices, perhaps not 'usb start'ed..?\n");
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return 1;
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}
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@ -118,7 +118,7 @@ _trap_table:
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TRAPI(13); ! 1d IRQ level 13
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TRAPI(14); ! 1e IRQ level 14
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TRAP(_nmi_trap); ! 1f IRQ level 15 /
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! NMI (non maskable interrupt)
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! NMI (non maskable interrupt)
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BAD_TRAP; ! 20 r_register_access_error
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BAD_TRAP; ! 21 instruction access error
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BAD_TRAP; ! 22
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@ -213,9 +213,9 @@ _hardreset:
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nop
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/* Init Cache */
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set (LEON2_PREGS+LEON_REG_CACHECTRL_OFFSET), %g1
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set 0x0081000f, %g2
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st %g2, [%g1]
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set (LEON2_PREGS+LEON_REG_CACHECTRL_OFFSET), %g1
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set 0x0081000f, %g2
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st %g2, [%g1]
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mov %g0, %y
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clr %g1
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@ -584,7 +584,7 @@ trap_setup:
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or %t_wim, %g2, %g2
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and %g2, 0xff, %g2
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save %g0, %g0, %g0 ! get in window to be saved
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save %g0, %g0, %g0 ! get in window to be saved
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/* Set new %wim value */
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wr %g2, 0x0, %wim
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@ -359,8 +359,8 @@ prom_relocate_loop:
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nop
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nop
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nop
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/* If CACHE snooping is available in hardware the
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/* If CACHE snooping is available in hardware the
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* variable leon3_snooping_avail will be set to
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* 0x800000 else 0.
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*/
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@ -67,11 +67,13 @@ int get_clocks (void)
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#if defined(CONFIG_M5275)
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volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
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/* Setup PLL */
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pll->syncr = 0x01080000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK));
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pll->syncr = 0x01000000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK));
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/* Setup PLL */
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pll->syncr = 0x01080000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK)
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;
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pll->syncr = 0x01000000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK))
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;
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#endif
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gd->cpu_clk = CFG_CLK;
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@ -21,7 +21,7 @@ tested on both gig copper and gig fiber boards
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59
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Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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The full GNU General Public License is included in this distribution in the
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file called LICENSE.
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@ -52,7 +52,7 @@ tested on both gig copper and gig fiber boards
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#undef virt_to_bus
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#define virt_to_bus(x) ((unsigned long)x)
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#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
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#define mdelay(n) udelay((n)*1000)
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#define mdelay(n) udelay((n)*1000)
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#define E1000_DEFAULT_PBA 0x00000030
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@ -646,8 +646,8 @@ e1000_set_mac_type(struct e1000_hw *hw)
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hw->mac_type = e1000_82546;
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break;
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case E1000_DEV_ID_82541ER:
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hw->mac_type = e1000_82541_rev_2;
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break;
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hw->mac_type = e1000_82541_rev_2;
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break;
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default:
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/* Should never have loaded on this device */
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return -E1000_ERR_MAC_TYPE;
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@ -1061,12 +1061,12 @@ e1000_setup_fiber_link(struct eth_device *nic)
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* configure the two flow control enable bits in the CTRL register.
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*
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* The possible values of the "fc" parameter are:
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames, but
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* not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames but we do
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* not support receiving pause frames).
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* 3: Both Rx and TX flow control (symmetric) are enabled.
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames, but
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* not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames but we do
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* not support receiving pause frames).
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* 3: Both Rx and TX flow control (symmetric) are enabled.
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*/
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switch (hw->fc) {
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case e1000_fc_none:
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@ -1229,7 +1229,7 @@ e1000_setup_copper_link(struct eth_device *nic)
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#if 0
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/* Options:
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* disable_polarity_correction = 0 (default)
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* Automatic Correction for Reversed Cable Polarity
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* Automatic Correction for Reversed Cable Polarity
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* 0 - Disabled
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* 1 - Enabled
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*/
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@ -1271,14 +1271,14 @@ e1000_setup_copper_link(struct eth_device *nic)
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/* Options:
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* autoneg = 1 (default)
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* PHY will advertise value(s) parsed from
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* autoneg_advertised and fc
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* PHY will advertise value(s) parsed from
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* autoneg_advertised and fc
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* autoneg = 0
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* PHY will be set to 10H, 10F, 100H, or 100F
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* depending on value parsed from forced_speed_duplex.
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* PHY will be set to 10H, 10F, 100H, or 100F
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* depending on value parsed from forced_speed_duplex.
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*/
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/* Is autoneg enabled? This is enabled by default or by software override.
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/* Is autoneg enabled? This is enabled by default or by software override.
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* If so, call e1000_phy_setup_autoneg routine to parse the
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* autoneg_advertised and fc options. If autoneg is NOT enabled, then the
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* user should have provided a speed/duplex override. If so, then call
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@ -1353,11 +1353,11 @@ e1000_setup_copper_link(struct eth_device *nic)
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if (phy_data & MII_SR_LINK_STATUS) {
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/* We have link, so we need to finish the config process:
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* 1) Set up the MAC to the current PHY speed/duplex
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* if we are on 82543. If we
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* are on newer silicon, we only need to configure
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* collision distance in the Transmit Control Register.
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* if we are on 82543. If we
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* are on newer silicon, we only need to configure
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* collision distance in the Transmit Control Register.
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* 2) Set up flow control on the MAC to that established with
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* the link partner.
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* the link partner.
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*/
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if (hw->mac_type >= e1000_82544) {
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e1000_config_collision_dist(hw);
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@ -1418,7 +1418,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
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/* First we clear all the 10/100 mb speed bits in the Auto-Neg
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* Advertisement Register (Address 4) and the 1000 mb speed bits in
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* the 1000Base-T Control Register (Address 9).
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* the 1000Base-T Control Register (Address 9).
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*/
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mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
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mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
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@ -1468,14 +1468,14 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
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* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
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*
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* The possible values of the "fc" parameter are:
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames
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* but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames
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* but we do not support receiving pause frames).
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* 3: Both Rx and TX flow control (symmetric) are enabled.
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause frames
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* but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames
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* but we do not support receiving pause frames).
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* 3: Both Rx and TX flow control (symmetric) are enabled.
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* other: No software override. The flow control configuration
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* in the EEPROM is used.
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* in the EEPROM is used.
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*/
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switch (hw->fc) {
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case e1000_fc_none: /* 0 */
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@ -1630,12 +1630,12 @@ e1000_force_mac_fc(struct e1000_hw *hw)
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* according to the "hw->fc" parameter.
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*
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* The possible values of the "fc" parameter are:
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause
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* frames but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames
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* frames but we do not receive pause frames).
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* 3: Both Rx and TX flow control (symmetric) is enabled.
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* 0: Flow control is completely disabled
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* 1: Rx flow control is enabled (we can receive pause
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* frames but not send pause frames).
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* 2: Tx flow control is enabled (we can send pause frames
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* frames but we do not receive pause frames).
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* 3: Both Rx and TX flow control (symmetric) is enabled.
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* other: No other values should be possible at this point.
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*/
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@ -1752,14 +1752,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
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* LOCAL DEVICE | LINK PARTNER
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
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*-------|---------|-------|---------|--------------------
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* 0 | 0 | DC | DC | e1000_fc_none
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* 0 | 1 | 0 | DC | e1000_fc_none
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* 0 | 1 | 1 | 0 | e1000_fc_none
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* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
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* 1 | 0 | 0 | DC | e1000_fc_none
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* 1 | DC | 1 | DC | e1000_fc_full
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* 1 | 1 | 0 | 0 | e1000_fc_none
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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* 0 | 0 | DC | DC | e1000_fc_none
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* 0 | 1 | 0 | DC | e1000_fc_none
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* 0 | 1 | 1 | 0 | e1000_fc_none
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* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
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* 1 | 0 | 0 | DC | e1000_fc_none
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* 1 | DC | 1 | DC | e1000_fc_full
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* 1 | 1 | 0 | 0 | e1000_fc_none
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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*
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*/
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/* Are both PAUSE bits set to 1? If so, this implies
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@ -1771,7 +1771,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
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* LOCAL DEVICE | LINK PARTNER
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
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*-------|---------|-------|---------|--------------------
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* 1 | DC | 1 | DC | e1000_fc_full
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* 1 | DC | 1 | DC | e1000_fc_full
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*
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*/
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if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
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@ -1796,7 +1796,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
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* LOCAL DEVICE | LINK PARTNER
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
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*-------|---------|-------|---------|--------------------
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* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
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* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
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*
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*/
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else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
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@ -1813,7 +1813,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
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* LOCAL DEVICE | LINK PARTNER
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* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
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*-------|---------|-------|---------|--------------------
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
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*
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*/
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else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
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@ -1855,7 +1855,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
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("Flow Control = RX PAUSE frames only.\r\n");
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}
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/* Now we need to do one last check... If we auto-
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/* Now we need to do one last check... If we auto-
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* negotiated to HALF DUPLEX, flow control should not be
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* enabled per IEEE 802.3 spec.
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*/
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@ -1919,7 +1919,7 @@ e1000_check_for_link(struct eth_device *nic)
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/* If we have a copper PHY then we only want to go out to the PHY
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* registers to see if Auto-Neg has completed and/or if our link
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* status has changed. The get_link_status flag will be set if we
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* status has changed. The get_link_status flag will be set if we
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* receive a Link Status Change interrupt or we have Rx Sequence
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* Errors.
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*/
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@ -1976,7 +1976,7 @@ e1000_check_for_link(struct eth_device *nic)
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/* At this point we know that we are on copper and we have
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* auto-negotiated link. These are conditions for checking the link
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* parter capability register. We use the link partner capability to
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* parter capability register. We use the link partner capability to
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* determine if TBI Compatibility needs to be turned on or off. If
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* the link partner advertises any speed in addition to Gigabit, then
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* we assume that they are GMII-based, and TBI compatibility is not
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@ -2494,34 +2494,33 @@ e1000_phy_reset(struct e1000_hw *hw)
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return 0;
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}
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static int
|
||||
e1000_set_phy_type(struct e1000_hw *hw)
|
||||
static int e1000_set_phy_type (struct e1000_hw *hw)
|
||||
{
|
||||
DEBUGFUNC();
|
||||
DEBUGFUNC ();
|
||||
|
||||
if(hw->mac_type == e1000_undefined)
|
||||
return -E1000_ERR_PHY_TYPE;
|
||||
if (hw->mac_type == e1000_undefined)
|
||||
return -E1000_ERR_PHY_TYPE;
|
||||
|
||||
switch(hw->phy_id) {
|
||||
case M88E1000_E_PHY_ID:
|
||||
case M88E1000_I_PHY_ID:
|
||||
case M88E1011_I_PHY_ID:
|
||||
hw->phy_type = e1000_phy_m88;
|
||||
break;
|
||||
case IGP01E1000_I_PHY_ID:
|
||||
if(hw->mac_type == e1000_82541 ||
|
||||
hw->mac_type == e1000_82541_rev_2) {
|
||||
hw->phy_type = e1000_phy_igp;
|
||||
break;
|
||||
}
|
||||
/* Fall Through */
|
||||
default:
|
||||
/* Should never have loaded on this device */
|
||||
hw->phy_type = e1000_phy_undefined;
|
||||
return -E1000_ERR_PHY_TYPE;
|
||||
}
|
||||
switch (hw->phy_id) {
|
||||
case M88E1000_E_PHY_ID:
|
||||
case M88E1000_I_PHY_ID:
|
||||
case M88E1011_I_PHY_ID:
|
||||
hw->phy_type = e1000_phy_m88;
|
||||
break;
|
||||
case IGP01E1000_I_PHY_ID:
|
||||
if (hw->mac_type == e1000_82541 ||
|
||||
hw->mac_type == e1000_82541_rev_2) {
|
||||
hw->phy_type = e1000_phy_igp;
|
||||
break;
|
||||
}
|
||||
/* Fall Through */
|
||||
default:
|
||||
/* Should never have loaded on this device */
|
||||
hw->phy_type = e1000_phy_undefined;
|
||||
return -E1000_ERR_PHY_TYPE;
|
||||
}
|
||||
|
||||
return E1000_SUCCESS;
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
|
|
@ -2825,8 +2824,8 @@ e1000_configure_rx(struct e1000_hw *hw)
|
|||
#endif
|
||||
/* Set the interrupt throttling rate. Value is calculated
|
||||
* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
|
||||
#define MAX_INTS_PER_SEC 8000
|
||||
#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
|
||||
#define MAX_INTS_PER_SEC 8000
|
||||
#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
|
||||
E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@
|
|||
/* Max devices this software will support */
|
||||
#define LEON3_AHB_MASTERS 16
|
||||
#define LEON3_AHB_SLAVES 16
|
||||
/*#define LEON3_APB_MASTERS 1*//* Number of APB buses that has Plug&Play */
|
||||
/*#define LEON3_APB_MASTERS 1*/ /* Number of APB buses that has Plug&Play */
|
||||
#define LEON3_APB_SLAVES 16 /* Total number of APB slaves per APB bus */
|
||||
|
||||
/* Vendor codes */
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ typedef struct ccsr_local_ecm {
|
|||
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
|
||||
char res19[4];
|
||||
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
|
||||
char res20[780]; // XXX: LAW 8, LAW9 for 8572
|
||||
char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
|
||||
uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
|
||||
char res21[12];
|
||||
uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
|
||||
|
|
|
|||
|
|
@ -18,9 +18,9 @@
|
|||
#define MSR_SF (1<<63)
|
||||
#define MSR_ISF (1<<61)
|
||||
#endif /* CONFIG_PPC64BRIDGE */
|
||||
#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
|
||||
#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
|
||||
#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
|
||||
#define MSR_SPE (1<<25) /* Enable SPE(e500) */
|
||||
#define MSR_SPE (1<<25) /* Enable SPE(e500) */
|
||||
#define MSR_POW (1<<18) /* Enable Power Management */
|
||||
#define MSR_WE (1<<18) /* Wait State Enable */
|
||||
#define MSR_TGPR (1<<17) /* TLB Update registers in use */
|
||||
|
|
@ -32,19 +32,19 @@
|
|||
#define MSR_ME (1<<12) /* Machine Check Enable */
|
||||
#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
|
||||
#define MSR_SE (1<<10) /* Single Step */
|
||||
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
|
||||
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
|
||||
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
|
||||
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
|
||||
#define MSR_BE (1<<9) /* Branch Trace */
|
||||
#define MSR_DE (1<<9) /* Debug Exception Enable */
|
||||
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
|
||||
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
|
||||
#define MSR_IR (1<<5) /* Instruction Relocate */
|
||||
#define MSR_IS (1<<5) /* Book E Instruction space */
|
||||
#define MSR_IS (1<<5) /* Book E Instruction space */
|
||||
#define MSR_DR (1<<4) /* Data Relocate */
|
||||
#define MSR_DS (1<<4) /* Book E Data space */
|
||||
#define MSR_DS (1<<4) /* Book E Data space */
|
||||
#define MSR_PE (1<<3) /* Protection Enable */
|
||||
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
|
||||
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
|
||||
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
|
||||
#define MSR_RI (1<<1) /* Recoverable Exception */
|
||||
#define MSR_LE (1<<0) /* Little Endian */
|
||||
|
||||
|
|
@ -54,7 +54,7 @@
|
|||
#define MSR_ MSR_ME|MSR_RI
|
||||
#endif
|
||||
#ifndef CONFIG_E500
|
||||
#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
|
||||
#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
|
||||
#else
|
||||
#define MSR_KERNEL MSR_ME
|
||||
#endif
|
||||
|
|
@ -103,9 +103,9 @@
|
|||
#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
|
||||
#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
|
||||
#else
|
||||
#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
|
||||
#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
|
||||
#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define SPRN_DAR 0x013 /* Data Address Register */
|
||||
#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
|
||||
#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
|
||||
|
|
@ -115,14 +115,14 @@
|
|||
#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
|
||||
#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
|
||||
#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
|
||||
#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
|
||||
#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
|
||||
#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
|
||||
#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
|
||||
#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
|
||||
#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
|
||||
#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
|
||||
#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
|
||||
#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
|
||||
#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
|
||||
#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
|
||||
#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
|
||||
#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
|
||||
#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
|
||||
#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
|
||||
#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
|
||||
#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
|
||||
#define DBCR_EDM 0x80000000
|
||||
#define DBCR_IDM 0x40000000
|
||||
|
|
@ -157,18 +157,18 @@
|
|||
#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
|
||||
#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
|
||||
#ifndef CONFIG_BOOKE
|
||||
#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
|
||||
#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
|
||||
#else
|
||||
#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
|
||||
#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#ifndef CONFIG_BOOKE
|
||||
#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
|
||||
#define SPRN_DBSR 0x3F0 /* Debug Status Register */
|
||||
#else
|
||||
#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
|
||||
#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
|
||||
#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
|
||||
#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
|
||||
#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
|
||||
#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
|
||||
#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
|
||||
#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
|
||||
#define DCCR_NOCACHE 0 /* Noncacheable */
|
||||
|
|
@ -180,7 +180,7 @@
|
|||
#ifndef CONFIG_BOOKE
|
||||
#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
|
||||
#else
|
||||
#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
|
||||
#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define SPRN_DEC 0x016 /* Decrement Register */
|
||||
#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
|
||||
|
|
@ -189,7 +189,7 @@
|
|||
#ifndef CONFIG_BOOKE
|
||||
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
|
||||
#else
|
||||
#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
|
||||
#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
|
||||
#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
|
||||
|
|
@ -246,8 +246,8 @@
|
|||
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
|
||||
#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
|
||||
#else
|
||||
#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
|
||||
#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
|
||||
#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
|
||||
#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
|
||||
#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
|
||||
|
|
@ -257,14 +257,14 @@
|
|||
#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
|
||||
#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
|
||||
#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
|
||||
#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
|
||||
#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
|
||||
#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
|
||||
#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
|
||||
#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
|
||||
#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
|
||||
#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
|
||||
#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
|
||||
#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
|
||||
#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
|
||||
#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
|
||||
#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
|
||||
#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
|
||||
#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
|
||||
#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
|
||||
#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
|
||||
#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
|
||||
#define ICCR_NOCACHE 0 /* Noncacheable */
|
||||
#define ICCR_CACHE 1 /* Cacheable */
|
||||
|
|
@ -273,10 +273,10 @@
|
|||
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
|
||||
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
|
||||
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
|
||||
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
|
||||
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
|
||||
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
|
||||
#define SPRN_LR 0x008 /* Link Register */
|
||||
#define SPRN_MBAR 0x137 /* System memory base address */
|
||||
#define SPRN_MBAR 0x137 /* System memory base address */
|
||||
#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
|
||||
#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
|
||||
#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
|
||||
|
|
@ -287,8 +287,8 @@
|
|||
#define SPRN_PID 0x3B1 /* Process ID */
|
||||
#define SPRN_PIR 0x3FF /* Processor Identification Register */
|
||||
#else
|
||||
#define SPRN_PID 0x030 /* Book E Process ID */
|
||||
#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
|
||||
#define SPRN_PID 0x030 /* Book E Process ID */
|
||||
#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
|
||||
#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
|
||||
|
|
@ -331,7 +331,7 @@
|
|||
#ifndef CONFIG_BOOKE
|
||||
#define SPRN_TCR 0x3DA /* Timer Control Register */
|
||||
#else
|
||||
#define SPRN_TCR 0x154 /* Book E Timer Control Register */
|
||||
#define SPRN_TCR 0x154 /* Book E Timer Control Register */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
|
||||
#define WP_2_17 0 /* 2^17 clocks */
|
||||
|
|
@ -362,11 +362,11 @@
|
|||
#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
|
||||
#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
|
||||
#define THRM3_E (1<<31)
|
||||
#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
|
||||
#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
|
||||
#ifndef CONFIG_BOOKE
|
||||
#define SPRN_TSR 0x3D8 /* Timer Status Register */
|
||||
#else
|
||||
#define SPRN_TSR 0x150 /* Book E Timer Status Register */
|
||||
#define SPRN_TSR 0x150 /* Book E Timer Status Register */
|
||||
#endif /* CONFIG_BOOKE */
|
||||
#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
|
||||
#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
|
||||
|
|
@ -424,40 +424,40 @@
|
|||
#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
|
||||
|
||||
/* e500 definitions */
|
||||
#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
|
||||
#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
|
||||
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
|
||||
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
|
||||
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
|
||||
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
|
||||
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
|
||||
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
|
||||
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
|
||||
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
|
||||
#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
|
||||
#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
|
||||
#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
|
||||
#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
|
||||
#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
|
||||
#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
|
||||
#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
|
||||
#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
|
||||
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
|
||||
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
|
||||
|
||||
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
|
||||
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
|
||||
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
|
||||
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
|
||||
#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
|
||||
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
|
||||
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
|
||||
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
|
||||
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
|
||||
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
|
||||
#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
|
||||
#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
|
||||
#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
|
||||
#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
|
||||
#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
|
||||
#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
|
||||
|
||||
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
|
||||
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
|
||||
#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
|
||||
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
|
||||
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
|
||||
#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
|
||||
#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
|
||||
#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
|
||||
#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
|
||||
#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
|
||||
|
||||
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
|
||||
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
|
||||
#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
|
||||
#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
|
||||
#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
|
||||
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
|
||||
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
|
||||
#define SPRN_PID1 0x279 /* Process ID Register 1 */
|
||||
#define SPRN_PID2 0x27a /* Process ID Register 2 */
|
||||
#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
|
||||
#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
|
||||
#define SPRN_PID1 0x279 /* Process ID Register 1 */
|
||||
#define SPRN_PID2 0x27a /* Process ID Register 2 */
|
||||
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
|
||||
#define SPRN_MCAR 0x23d /* Machine Check Address register */
|
||||
#ifdef CONFIG_440
|
||||
|
|
@ -471,14 +471,13 @@
|
|||
#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
|
||||
#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
|
||||
#endif
|
||||
#define ESR_ST 0x00800000 /* Store Operation */
|
||||
#define ESR_ST 0x00800000 /* Store Operation */
|
||||
|
||||
#if defined(CONFIG_MPC86xx)
|
||||
#define SPRN_MSSCR0 0x3f6
|
||||
#define SPRN_MSSSR0 0x3f7
|
||||
#endif
|
||||
|
||||
|
||||
/* Short-hand versions for a number of the above SPRNs */
|
||||
|
||||
#define CTR SPRN_CTR /* Counter Register */
|
||||
|
|
@ -494,14 +493,14 @@
|
|||
#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
|
||||
#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
|
||||
#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
|
||||
#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
|
||||
#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
|
||||
#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
|
||||
#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
|
||||
#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
|
||||
#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
|
||||
#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
|
||||
#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
|
||||
#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
|
||||
#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
|
||||
#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
|
||||
#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
|
||||
#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
|
||||
#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
|
||||
#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
|
||||
#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
|
||||
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
|
||||
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
|
||||
#define DBSR SPRN_DBSR /* Debug Status Register */
|
||||
|
|
@ -537,10 +536,10 @@
|
|||
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
|
||||
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
|
||||
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
|
||||
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
|
||||
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
|
||||
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
|
||||
#define LR SPRN_LR
|
||||
#define MBAR SPRN_MBAR /* System memory base address */
|
||||
#define MBAR SPRN_MBAR /* System memory base address */
|
||||
#if defined(CONFIG_MPC86xx)
|
||||
#define MSSCR0 SPRN_MSSCR0
|
||||
#endif
|
||||
|
|
@ -555,14 +554,14 @@
|
|||
#define SPR1 SPRN_SPRG1
|
||||
#define SPR2 SPRN_SPRG2
|
||||
#define SPR3 SPRN_SPRG3
|
||||
#define SPRG0 SPRN_SPRG0
|
||||
#define SPRG1 SPRN_SPRG1
|
||||
#define SPRG2 SPRN_SPRG2
|
||||
#define SPRG3 SPRN_SPRG3
|
||||
#define SPRG4 SPRN_SPRG4
|
||||
#define SPRG5 SPRN_SPRG5
|
||||
#define SPRG6 SPRN_SPRG6
|
||||
#define SPRG7 SPRN_SPRG7
|
||||
#define SPRG0 SPRN_SPRG0
|
||||
#define SPRG1 SPRN_SPRG1
|
||||
#define SPRG2 SPRN_SPRG2
|
||||
#define SPRG3 SPRN_SPRG3
|
||||
#define SPRG4 SPRN_SPRG4
|
||||
#define SPRG5 SPRN_SPRG5
|
||||
#define SPRG6 SPRN_SPRG6
|
||||
#define SPRG7 SPRN_SPRG7
|
||||
#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
|
||||
#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
|
||||
#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
|
||||
|
|
@ -662,25 +661,25 @@
|
|||
#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
|
||||
#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
|
||||
#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
|
||||
#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
|
||||
#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
|
||||
#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
|
||||
#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
|
||||
#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
|
||||
#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
|
||||
#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
|
||||
#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
|
||||
#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
|
||||
#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
|
||||
#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
|
||||
#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
|
||||
#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
|
||||
#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
|
||||
#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
|
||||
#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
|
||||
#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
|
||||
#define DCRN_DMASR 0x0E0 /* DMA Status Register */
|
||||
#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
|
||||
#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
|
||||
#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
|
||||
#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
|
||||
#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
|
||||
#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
|
||||
#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
|
||||
#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
|
||||
#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
|
||||
#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
|
||||
#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
|
||||
#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
|
||||
#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
|
||||
#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
|
||||
#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
|
||||
#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
|
||||
#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
|
||||
#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
|
||||
#define DCRN_DMASR 0x0E0 /* DMA Status Register */
|
||||
#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
|
||||
#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
|
||||
#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
|
||||
#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
|
||||
|
|
@ -695,8 +694,8 @@
|
|||
#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
|
||||
#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
|
||||
#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
|
||||
#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
|
||||
#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
|
||||
#define DCRN_EXISR 0x040 /* External Interrupt Status Register */
|
||||
#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
|
||||
#define IOCR_E0TE 0x80000000
|
||||
#define IOCR_E0LP 0x40000000
|
||||
#define IOCR_E1TE 0x20000000
|
||||
|
|
@ -729,14 +728,13 @@
|
|||
#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
|
||||
#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
|
||||
|
||||
#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
|
||||
#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
|
||||
#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
|
||||
#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
|
||||
#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
|
||||
#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
|
||||
#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
|
||||
|
||||
#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
|
||||
#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
|
||||
#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
|
||||
#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
|
||||
#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
|
||||
#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
|
||||
#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
|
||||
|
||||
/* Processor Version Register */
|
||||
|
||||
|
|
@ -785,10 +783,10 @@
|
|||
#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
|
||||
#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
|
||||
#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
|
||||
#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
|
||||
#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
|
||||
#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
|
||||
#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
|
||||
#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
|
||||
#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
|
||||
#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
|
||||
#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
|
||||
#define PVR_440GX_RA 0x51B21850
|
||||
#define PVR_440GX_RB 0x51B21851
|
||||
#define PVR_440GX_RC 0x51B21892
|
||||
|
|
@ -802,9 +800,9 @@
|
|||
#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
|
||||
#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
|
||||
#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
|
||||
#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
|
||||
#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
|
||||
#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
|
||||
#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
|
||||
#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
|
||||
#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
|
||||
#define PVR_601 0x00010000
|
||||
#define PVR_602 0x00050000
|
||||
|
|
@ -820,9 +818,9 @@
|
|||
#define PVR_750 PVR_740
|
||||
#define PVR_740P 0x10080000
|
||||
#define PVR_750P PVR_740P
|
||||
#define PVR_7400 0x000C0000
|
||||
#define PVR_7410 0x800C0000
|
||||
#define PVR_7450 0x80000000
|
||||
#define PVR_7400 0x000C0000
|
||||
#define PVR_7410 0x800C0000
|
||||
#define PVR_7450 0x80000000
|
||||
|
||||
#define PVR_85xx 0x80200000
|
||||
#define PVR_85xx_REV1 (PVR_85xx | 0x0010)
|
||||
|
|
@ -848,10 +846,10 @@
|
|||
* PowerQUICC II family processors report different PVR values depending
|
||||
* on silicon process (HiP3, HiP4, HiP7, etc.)
|
||||
*/
|
||||
#define PVR_8260 PVR_8240
|
||||
#define PVR_8260_HIP3 0x00810101
|
||||
#define PVR_8260_HIP4 0x80811014
|
||||
#define PVR_8260_HIP7 0x80822011
|
||||
#define PVR_8260 PVR_8240
|
||||
#define PVR_8260_HIP3 0x00810101
|
||||
#define PVR_8260_HIP4 0x80811014
|
||||
#define PVR_8260_HIP7 0x80822011
|
||||
#define PVR_8260_HIP7R1 0x80822013
|
||||
#define PVR_8260_HIP7RA 0x80822014
|
||||
|
||||
|
|
@ -861,7 +859,6 @@
|
|||
#define PVR_5200 0x80822011
|
||||
#define PVR_5200B 0x80822014
|
||||
|
||||
|
||||
/*
|
||||
* System Version Register
|
||||
*/
|
||||
|
|
@ -882,7 +879,6 @@
|
|||
/* Some parts define SVR[0:23] as the SOC version */
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
|
||||
|
||||
|
||||
/*
|
||||
* SVR_SOC_VER() Version Values
|
||||
*/
|
||||
|
|
@ -915,8 +911,6 @@
|
|||
#define SVR_8641 0x809000
|
||||
#define SVR_8641D 0x809001
|
||||
|
||||
|
||||
|
||||
/* I am just adding a single entry for 8260 boards. I think we may be
|
||||
* able to combine mbx, fads, rpxlite, bseip, and classic into a single
|
||||
* generic 8xx as well. The boards containing these processors are either
|
||||
|
|
@ -944,7 +938,6 @@
|
|||
#define _MACH_tqm8xxL 0x00010000 /* TQM8xxL */
|
||||
#define _MACH_hidden_dragon 0x00020000 /* Motorola Hidden Dragon eval board */
|
||||
|
||||
|
||||
/* see residual.h for these */
|
||||
#define _PREP_Motorola 0x01 /* motorola prep */
|
||||
#define _PREP_Firm 0x02 /* firmworks prep */
|
||||
|
|
@ -1071,7 +1064,7 @@ struct thread_struct {
|
|||
struct pt_regs *regs; /* Pointer to saved register state */
|
||||
mm_segment_t fs; /* for get_fs() validation */
|
||||
void *pgdir; /* root of page-table tree */
|
||||
signed long last_syscall;
|
||||
signed long last_syscall;
|
||||
double fpr[32]; /* Complete floating point set */
|
||||
unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
|
||||
unsigned long fpscr; /* Floating point status */
|
||||
|
|
@ -1096,7 +1089,7 @@ struct thread_struct {
|
|||
|
||||
/*
|
||||
* Note: the vm_start and vm_end fields here should *not*
|
||||
* be in kernel space. (Could vm_end == vm_start perhaps?)
|
||||
* be in kernel space. (Could vm_end == vm_start perhaps?)
|
||||
*/
|
||||
#define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
|
||||
PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
|
||||
|
|
@ -1126,7 +1119,7 @@ unsigned long get_wchan(struct task_struct *p);
|
|||
#define alloc_task_struct() \
|
||||
((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
|
||||
#define free_task_struct(p) free_pages((unsigned long)(p),1)
|
||||
#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
|
||||
#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
|
||||
|
||||
/* in process.c - for early bootup debug -- Cort */
|
||||
int ll_printk(const char *, ...);
|
||||
|
|
|
|||
|
|
@ -7,28 +7,26 @@
|
|||
struct __large_struct { unsigned long buf[100]; };
|
||||
#define __m(x) (*(struct __large_struct *)(x))
|
||||
|
||||
void dcache_wback_range(u32 start, u32 end)
|
||||
void dcache_wback_range (u32 start, u32 end)
|
||||
{
|
||||
u32 v;
|
||||
u32 v;
|
||||
|
||||
start &= ~(L1_CACHE_BYTES-1);
|
||||
for (v = start; v < end; v+=L1_CACHE_BYTES) {
|
||||
asm volatile("ocbwb %0"
|
||||
: /* no output */
|
||||
: "m" (__m(v)));
|
||||
}
|
||||
start &= ~(L1_CACHE_BYTES - 1);
|
||||
for (v = start; v < end; v += L1_CACHE_BYTES) {
|
||||
asm volatile ("ocbwb %0": /* no output */
|
||||
:"m" (__m (v)));
|
||||
}
|
||||
}
|
||||
|
||||
void dcache_invalid_range(u32 start, u32 end)
|
||||
void dcache_invalid_range (u32 start, u32 end)
|
||||
{
|
||||
u32 v;
|
||||
u32 v;
|
||||
|
||||
start &= ~(L1_CACHE_BYTES-1);
|
||||
for (v = start; v < end; v+=L1_CACHE_BYTES) {
|
||||
asm volatile("ocbi %0"
|
||||
: /* no output */
|
||||
: "m" (__m(v)));
|
||||
}
|
||||
start &= ~(L1_CACHE_BYTES - 1);
|
||||
for (v = start; v < end; v += L1_CACHE_BYTES) {
|
||||
asm volatile ("ocbi %0": /* no output */
|
||||
:"m" (__m (v)));
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SH4 || CONFIG_SH4A */
|
||||
|
||||
|
|
|
|||
|
|
@ -28,10 +28,9 @@
|
|||
#error Include LEON3 header file only if LEON3 processor
|
||||
#endif
|
||||
|
||||
/* Not much to define, most is Plug and Play and GRLIB dependent
|
||||
* not LEON3 dependent. See <ambapp.h> for GRLIB timers, interrupt
|
||||
/* Not much to define, most is Plug and Play and GRLIB dependent
|
||||
* not LEON3 dependent. See <ambapp.h> for GRLIB timers, interrupt
|
||||
* ctrl, memory controllers etc.
|
||||
*/
|
||||
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -313,8 +313,8 @@
|
|||
|
||||
/*** LEON2 UART 1 ***/
|
||||
#define CFG_LEON2_UART1_SCALER \
|
||||
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
|
||||
|
||||
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
|
||||
|
||||
/* UART1 Define to 1 or 0 */
|
||||
#define LEON2_UART1_LOOPBACK_ENABLE 0
|
||||
#define LEON2_UART1_FLOWCTRL_ENABLE 0
|
||||
|
|
@ -324,7 +324,7 @@
|
|||
/*** LEON2 UART 2 ***/
|
||||
|
||||
#define CFG_LEON2_UART2_SCALER \
|
||||
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
|
||||
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
|
||||
|
||||
/* UART2 Define to 1 or 0 */
|
||||
#define LEON2_UART2_LOOPBACK_ENABLE 0
|
||||
|
|
|
|||
|
|
@ -2073,4 +2073,3 @@
|
|||
#define PCI_DEVICE_ID_MPC8641 0x7010
|
||||
#define PCI_DEVICE_ID_MPC8641D 0x7011
|
||||
#define PCI_DEVICE_ID_MPC8610 0x7018
|
||||
|
||||
|
|
|
|||
40
net/bootp.c
40
net/bootp.c
|
|
@ -163,21 +163,21 @@ static void BootpVendorFieldProcess (u8 * ext)
|
|||
|
||||
switch (*ext) {
|
||||
/* Fixed length fields */
|
||||
case 1: /* Subnet mask */
|
||||
case 1: /* Subnet mask */
|
||||
if (NetOurSubnetMask == 0)
|
||||
NetCopyIP (&NetOurSubnetMask, (IPaddr_t *) (ext + 2));
|
||||
break;
|
||||
case 2: /* Time offset - Not yet supported */
|
||||
case 2: /* Time offset - Not yet supported */
|
||||
break;
|
||||
/* Variable length fields */
|
||||
case 3: /* Gateways list */
|
||||
case 3: /* Gateways list */
|
||||
if (NetOurGatewayIP == 0) {
|
||||
NetCopyIP (&NetOurGatewayIP, (IPaddr_t *) (ext + 2));
|
||||
}
|
||||
break;
|
||||
case 4: /* Time server - Not yet supported */
|
||||
case 4: /* Time server - Not yet supported */
|
||||
break;
|
||||
case 5: /* IEN-116 name server - Not yet supported */
|
||||
case 5: /* IEN-116 name server - Not yet supported */
|
||||
break;
|
||||
case 6:
|
||||
if (NetOurDNSIP == 0) {
|
||||
|
|
@ -189,43 +189,43 @@ static void BootpVendorFieldProcess (u8 * ext)
|
|||
}
|
||||
#endif
|
||||
break;
|
||||
case 7: /* Log server - Not yet supported */
|
||||
case 7: /* Log server - Not yet supported */
|
||||
break;
|
||||
case 8: /* Cookie/Quote server - Not yet supported */
|
||||
case 8: /* Cookie/Quote server - Not yet supported */
|
||||
break;
|
||||
case 9: /* LPR server - Not yet supported */
|
||||
case 9: /* LPR server - Not yet supported */
|
||||
break;
|
||||
case 10: /* Impress server - Not yet supported */
|
||||
case 10: /* Impress server - Not yet supported */
|
||||
break;
|
||||
case 11: /* RPL server - Not yet supported */
|
||||
case 11: /* RPL server - Not yet supported */
|
||||
break;
|
||||
case 12: /* Host name */
|
||||
case 12: /* Host name */
|
||||
if (NetOurHostName[0] == 0) {
|
||||
size = truncate_sz ("Host Name", sizeof (NetOurHostName), size);
|
||||
memcpy (&NetOurHostName, ext + 2, size);
|
||||
NetOurHostName[size] = 0;
|
||||
}
|
||||
break;
|
||||
case 13: /* Boot file size */
|
||||
case 13: /* Boot file size */
|
||||
if (size == 2)
|
||||
NetBootFileSize = ntohs (*(ushort *) (ext + 2));
|
||||
else if (size == 4)
|
||||
NetBootFileSize = ntohl (*(ulong *) (ext + 2));
|
||||
break;
|
||||
case 14: /* Merit dump file - Not yet supported */
|
||||
case 14: /* Merit dump file - Not yet supported */
|
||||
break;
|
||||
case 15: /* Domain name - Not yet supported */
|
||||
case 15: /* Domain name - Not yet supported */
|
||||
break;
|
||||
case 16: /* Swap server - Not yet supported */
|
||||
case 16: /* Swap server - Not yet supported */
|
||||
break;
|
||||
case 17: /* Root path */
|
||||
case 17: /* Root path */
|
||||
if (NetOurRootPath[0] == 0) {
|
||||
size = truncate_sz ("Root Path", sizeof (NetOurRootPath), size);
|
||||
memcpy (&NetOurRootPath, ext + 2, size);
|
||||
NetOurRootPath[size] = 0;
|
||||
}
|
||||
break;
|
||||
case 18: /* Extension path - Not yet supported */
|
||||
case 18: /* Extension path - Not yet supported */
|
||||
/*
|
||||
* This can be used to send the information of the
|
||||
* vendor area in another file that the client can
|
||||
|
|
@ -233,7 +233,7 @@ static void BootpVendorFieldProcess (u8 * ext)
|
|||
*/
|
||||
break;
|
||||
/* IP host layer fields */
|
||||
case 40: /* NIS Domain name */
|
||||
case 40: /* NIS Domain name */
|
||||
if (NetOurNISDomain[0] == 0) {
|
||||
size = truncate_sz ("NIS Domain Name", sizeof (NetOurNISDomain), size);
|
||||
memcpy (&NetOurNISDomain, ext + 2, size);
|
||||
|
|
@ -241,7 +241,7 @@ static void BootpVendorFieldProcess (u8 * ext)
|
|||
}
|
||||
break;
|
||||
/* Application layer fields */
|
||||
case 43: /* Vendor specific info - Not yet supported */
|
||||
case 43: /* Vendor specific info - Not yet supported */
|
||||
/*
|
||||
* Binary information to exchange specific
|
||||
* product information.
|
||||
|
|
@ -879,7 +879,7 @@ static void DhcpSendRequestPkt(Bootp_t *bp_offer)
|
|||
iplen = BOOTP_HDR_SIZE - sizeof(bp->bp_vend) + extlen;
|
||||
NetSetIP(iphdr, 0xFFFFFFFFL, PORT_BOOTPS, PORT_BOOTPC, iplen);
|
||||
|
||||
debug ("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
|
||||
debug ("Transmitting DHCPREQUEST packet: len = %d\n", pktlen);
|
||||
#ifdef CONFIG_BOOTP_DHCP_REQUEST_DELAY
|
||||
udelay(CONFIG_BOOTP_DHCP_REQUEST_DELAY);
|
||||
#endif /* CONFIG_BOOTP_DHCP_REQUEST_DELAY */
|
||||
|
|
|
|||
Loading…
Reference in a new issue