Commit graph

2349 commits

Author SHA1 Message Date
Tom Rini
8a802a2eef Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchip
- some fix for rk3399-puma;
- rockchip script make_fit_atf.py cleanup
- Enable TPL for rk3399 orangepi and nanopi4;
- add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;
2019-05-31 07:17:09 -04:00
Neil Armstrong
32f2880641 ARM: dts: Add missing DT for Meson G12A support
The following DT nodes in the process on review for Linux 5.3,
until Linux 5.3 is tagged, add the missing DT nodes in u-boot specific
DTSI files that will be dropped when the v5.3-rc1 DT is synced again.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-05-31 10:04:15 +02:00
Neil Armstrong
b1e81e67ee ARM: dts: sync Amlogic G12A DT with Linux 5.2-rc1
Sync from Linux commit a188339ca5a3 ("Linux 5.2-rc1")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-05-31 09:57:49 +02:00
Jagan Teki
540c900dec rockchip: rk3399: Add Rock PI 4 support
Add initial support for Rock PI 4 board.

Specification
- Rockchip RK3399
- LPDDR4
- eMMC
- SD card slot
- RTL8211E 1Gbps
- HDMI In/Out, DP, MIPI DSI/CSI
- PCIe M.2
- USB 2.0, USB-3.0
- USB C Type

Commit details of rk3399-rock-pi-4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: add ROCK Pi 4 DTS support"
(sha1: 1b5715c602fda7b812af0e190eddcce2812e5417)

Signed-off-by: Akash Gajjar <akash@openedev.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Jagan Teki
001d6745e3 rockchip: rk3399: Add Rockpro64 board support
Add initial support for Rockpro64 board.

Specification
- Rockchip RK3399
- 2/4GB Dual-Channel LPDDR3
- SD card slot
- eMMC socket
- 128Mb SPI Flash
- Gigabit ethernet
- PCIe 4X slot
- WiFI/BT module socket
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A

Commit details of rk3399-rockpro64.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: rockpro64 dts add usb regulator"
(sha1: 6db644c79c8d45d73b56bc389aebd85fc3679beb)

'Akash' has sent an initial patch before, so I keep him as board
maintainer and I'm co-maintainer based on our conversation.

Signed-off-by: Akash Gajjar <akash@openedev.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Jagan Teki
48b5c25f99 rockchip: rk3399: Add Nanopi NEO4 board support
Add initial support for Nanopi NEO4 board.

Specification
- Rockchip RK3399
- 1GB DDR3-1866
- SD card slot
- eMMC Socket
- RTL8211E 1Gbps
- AP6212 WiFI/BT
- HDMI In/Out, DP, MIPI CSI
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 5V/3A

Commit details of rk3399-nanopi-neo4.dts sync from Linux:
"arm64: dts: rockchip: Add Nanopi NEO4 initial support"
(sha1: 092470b537f19788d957aed12d835a179b606014)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-30 18:22:35 +08:00
Tom Rini
696f02d99b Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA PL310 cleanup + A10 fix, A10 DT cleanup, DW GPIO fix.
2019-05-26 20:15:46 -04:00
Tien Fong Chee
ca9387e8b1 Arm: dts: socfpga: Remove invalid property from chose node
Finding bitstream from cff-file is no longer valid after bitstream is built
into FIT image and loaded by generic firmware loader. Remove cff-file
as this is legacy implementation from A10 downstream.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-24 14:29:51 +02:00
Patrick Delaunay
067a4c001d ARM: dts: stm32mp1: DDR config v1.44
Update DDR configuration with the latest update:

- PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
                        lane 2/3 in 16bit
- fix LPDDR2/3 timing_calc to step RL/WL in relaxed
  timings mode
- remove  LPDDR3 RL3 (optional) support vs  MR0[7]
  because MR0[7] can't be read instead  always apply
  worse RL/WL for LPDDR3 when freq < 166MHz)
- change  MR3 to 48ohm drive  for LPDDR2/3
- change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
  '0' is not allowed even when ODT not used
- use DQSTRN for LPDDR2/3 (it was not set in PIR)
- LPDDR3: set dqsge/dwsgx gate extension to 2,2
  like LPDDR2
-DDRCTRL.dfitmg0:
  + for LPDDR3 tphy_wrlat = WL (as LPDDR2)
  + improvement for relaxed mode vs  RL/Wl at corner case.
    For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
    and correction to MR2 accordingly
- DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
  for LTDC.
- DDR_PCFGWQOS0_0: change vpr level from
  11 to 12 in order to include the CPU on
  the variable priority queue.
- DDR_SCHED: fix to consider 13 levels  (13 levels - 1 = 0xC)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23 11:38:10 +02:00
Patrick Delaunay
c60fed14f6 stm32mp1: ram: change ddr speed to kHz
Allow fractional support in DDR tools.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-05-23 11:38:10 +02:00
Qiang Zhao
7e817c70ca arm: dts: fsl-ls1028a: add sp805 watchdog node
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Peng Ma
e765ee5c50 ARM: dts: Freescale: Add ecc addr for sata node
Move the ecc addr from driver to dts.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
f278a21749 armv8: ls1028aqds: Add support of LS1028AQDS
LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
353f36d96e armv8: ls1028ardb: Add support for LS1028ARDB
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Yuantian Tang
d4ad111dc4 armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
 ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.

Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Hou Zhiqiang
a8d6050543 armv8: lx2160a: add PCIe controller DT nodes
The LX2160A integrated 6 PCIe Gen4 controllers.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22 12:24:24 +05:30
Tom Rini
b9625abe03 - update for using splashfile instead of location->name
when loading the splash image from a FIT
 - updates for loading internal and external splash data from FIT
 - DM_GPIO/DM_VIDEO migration for mx53 cx9020 board
 - fix boot issue on mx6sabresd board after DM_VIDEO migration
 - increase the max preallocated framebuffer BPP to 32 in ipuv3
   driver to prepare for configurations with higher color depth
 - allow to use vidconsole_put_string() in board code for text
   output on LCD displays
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Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-video

- update for using splashfile instead of location->name
  when loading the splash image from a FIT
- updates for loading internal and external splash data from FIT
- DM_GPIO/DM_VIDEO migration for mx53 cx9020 board
- fix boot issue on mx6sabresd board after DM_VIDEO migration
- increase the max preallocated framebuffer BPP to 32 in ipuv3
  driver to prepare for configurations with higher color depth
- allow to use vidconsole_put_string() in board code for text
  output on LCD displays
2019-05-21 07:12:46 -04:00
Peng Fan
9002e735e7 imx: mx6sabresd: fix boot hang with video
Meet the following boot hang.
"
U-Boot SPL 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800)
Trying to boot from MMC1

U-Boot 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800)

CPU:   Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C)Reset cause: POR
Model: Freescale i.MX6 Quad SABRE Smart Device Board
Board: MX6-SabreSD
I2C:   ready
DRAM:  1 GiB
Video device 'ipu@2400000' cannot allocate frame buffer memory -ensure the device is set up before relocation
Error binding driver 'ipuv3_video': -28
Video device 'ipu@2800000' cannot allocate frame buffer memory -ensure the device is set up before relocation
Error binding driver 'ipuv3_video': -28
Some drivers failed to bind
Error binding driver 'generic_simple_bus': -28
Some drivers failed to bind
initcall sequence 4ffe4500 failed at call 1780dfb7 (err=-28)
"

1. fdtdec_get_alias_seq will use "video" as base, however in alias node,
   we use ipux, so add new alias for U-Boot dts.
2. DM_VIDEO is enabled, however reserve_video is called before
   relocation, so to make DM_VIDEO work before relocation, need to
   set SYS_MALLOC_F_LEN
3. defconfig is updated with savedefconfig

 Note: I do not have a video panel to test, but with this patch, U-Boot
       boots up again, below log.

"
U-Boot SPL 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800)
Trying to boot from MMC1

U-Boot 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800)

CPU:   Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
CPU:   Automotive temperature grade (-40C to 125C) at 34C
Reset cause: POR
Model: Freescale i.MX6 Quad SABRE Smart Device Board
Board: MX6-SabreSD
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 3
Loading Environment from MMC... *** Warning - bad CRC, using default environment

PCI:   pcie phy link never came up
In:    serial
Out:   serial
Err:   serial
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0
"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-05-20 11:58:01 +02:00
Steffen Dirkwinkel
c11599b473 arm: imx: add ipu to imx53.dts and set dm-pre-reloc
The ipu node in imx53 is needed for DM_VIDEO. We also need to set
u-boot,dm-pre-reloc to initialize before relocation.

Signed-off-by: Steffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
2019-05-20 11:57:24 +02:00
Stefan Roese
1718a9f3b7 arm: mvebu: armada-370-xp.dtsi: Add "u-boot, dm-pre-reloc" to "internal-regs"
Without this U-Boot specific property, booting on Armada XP theadorable
fails in SPL. All nodes in the "internal-regs" (simple-bus) DT node are
not scanned, so the UART node is missing (and others).

I'm not adding this property in an *u-boot.dtsi file, since there is
none matching the generic rules for all files including this dtsi
file. So to not miss any of the boards using this dtsi file, I'm
adding it to this file directly, which makes the Linux merge a less
easy unforunately.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
2019-05-20 09:27:36 +02:00
Philippe Reynes
ea1e9c04fd dt: bcm63158: watchdog should use a 50Mhz clock
The watchdog should use a clock at 50 Mhz, so
instead of using the clock osc (200 Mhz), we
define a reference clock at 50Mhz and use it
for both watchdog.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-05-18 12:31:59 -04:00
Philippe Reynes
a328ada441 dt: bcm6858: watchdog should use a 50Mhz clock
The watchdog should use a clock at 50 Mhz, so
instead of using the clock osc (200 Mhz), we
define a reference clock at 50Mhz and use it
for both watchdog.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-05-18 12:31:59 -04:00
Tom Rini
b51d103cab Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA DT and reset cleanup, AE MCVEVK board support.
2019-05-16 07:09:33 -04:00
Tom Rini
8b1d3d19be STM32 MCUs update:
_ Add MPU region for SPI NOR memory mapped region
 _ Add missing QSPI flash compatible for STM32 F7 boards
 _ Update spi-tx-bus-width and spi-rx-bus-width properties
 _ Add QSPI support for STM32F469 Discovery board
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Merge tag 'u-boot-stm32-mcu-20190514' of https://github.com/pchotard/u-boot

STM32 MCUs update:
_ Add MPU region for SPI NOR memory mapped region
_ Add missing QSPI flash compatible for STM32 F7 boards
_ Update spi-tx-bus-width and spi-rx-bus-width properties
_ Add QSPI support for STM32F469 Discovery board
2019-05-15 07:10:32 -04:00
Marek Vasut
9e6ed1a346 ARM: dts: socfpga: Keep FPGA bridge entries in SPL DT
Keep the FPGA bridge entries in SPL DT to let do_bridge_reset() toggle
the bridges on/off as needed according to the handoff file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-14 19:53:16 +02:00
Marek Vasut
917bd8a876 ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff files
Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi
into separate dtsi header file to make it easier to patch in custom handoff
dtsi files, without having to manually add the U-Boot bits. Shuffle the include
clauses in the A10 DT files to make it obvious what gets included where without
having to follow confusing long chain of includes, i.e. board DT file includes
everything it needs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-14 19:53:16 +02:00
Wolfgang Grandegger
990ed4452c arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board
Re-add support for Aries Embedded MCV SoM, which is CycloneV based
and the associated MCVEVK and MCVEVP baseboard. The board can boot
from eMMC. Ethernet and USB is supported.

The Aries Embedded boards have been removed with commit 03b54997d5
("board/aries: Remove"). I will now take care of them.

The device-tree files are from mainline Linux commit e93c9c99a629
("Linux v5.1)".

Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de>
CC: Marek Vasut <marex@denx.de>
CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-14 19:52:39 +02:00
Tien Fong Chee
0a42a132a4 ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2019-05-10 22:48:11 +02:00
Tom Rini
f30f268a07 Merge tag 'rockchip-for-v2019.07-rc1' of git://git.denx.de/u-boot-rockchip
Improvements and new features:
- split more rockchip pinctrl_core feature into per SoC
- enable TPL for evb-rk3399 board
- enable TPL/SPL for evb-px5 board
- enable TPL and OP-TEE support for evb-rk3229
- update fix in arm common assembly start code for rockchip header file
- update default SPL_FIT_GENERATOR for rockchip
- rk3399 boards update to use '-u-boot.dtsi'
- add new rk3399 boards: Nanopi M4, Nanopc T4
- enable sound for chromebook_minnie
2019-05-09 12:36:17 -04:00
Tom Rini
062aceb8bf Merge git://git.denx.de/u-boot-marvell
- DM updates for multiple MVEBU boards (Stefan)
- Add CRS305-1G-4S board (Luka)
- Enable MMC in SPL on clearfog (Baruch)
2019-05-09 07:12:25 -04:00
Jagan Teki
65cc7dcd77 rockchip: rk3399: Add Nanopc T4 board support
Add initial support for Nanopc T4 board.

Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- 16GB eMMC
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI, eDP
- USB 3.0, 2.0
- USB Type C power and data
- GPIO expansion ports
- DC 12V/2A

Commit details of rk3399-nanopc-t4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Add NanoPC-T4 IR receiver"
(sha1: 95658e21b1707ad7844f873db2fdaa295109a5a3)

Tested-by: Daniel Gröber <dxld@darkboxed.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-09 18:24:31 +08:00
Jagan Teki
b2f5da9dd0 rockchip: rk3399: Add Nanopi M4 board support
Add initial support for Nanopi M4 board.

Specification
- Rockchip RK3399
- Dual-Channel 4GB LPDDR3-1866
- SD card slot
- eMMC socket
- RTL8211E 1Gbps
- AP6356S WiFI/BT
- HDMI In/Out, DP, MIPI DSI/CSI
- USB 3.0 x4
- USB Type C power and data
- GPIO1, GPIO2 expansion ports
- DC5V/3A

Commit details of rk3399-nanopi-m4.dts sync from Linux 5.1-rc2:
"arm64: dts: rockchip: Refine nanopi4 differences"
(sha1: c62ffaf5026d0b7633e62b2cea8450b5543c349a)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-05-09 18:24:31 +08:00
Jagan Teki
adc91db0e6 rockchip: dts: rk3399: nanopi4: Use CD pin as RK_FUNC_1
Attaching GPIO functionality to SDMMC0_DET pin (which
does in Linux base dts) make dwmmc driver "fail to detect
the card".

  Card did not respond to voltage select!

It may be because the existing driver can't support gpio
card detection. So, change the pinctrl functionality from
RK_FUNC_GPIO to RK_FUNC_1 like other rk3399 dts does via
sdmmc_cd pin.

Cc: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-09 18:23:16 +08:00
Baruch Siach
13cba82b51 arm: mvebu: clearfog: add MMC to SPL DT
This allows SPL to load the main U-Boot image from MMC once DM_MMC is
enabled.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-05-09 07:35:04 +02:00
Luka Kovacic
22bb913fdf arm: mvebu: Add CRS305-1G-4S board
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and
like some of the other similar boards requires bin_hdr.
bin_hdr (DDR3 init stage) is currently retrieved from the stock
bootloader and compiled into the kwb image.

Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip
support and writing env to SPI flash.

Signed-off-by: Luka Kovacic <me@lukakovacic.xyz>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-05-09 07:35:04 +02:00
Tom Rini
eb511984e9 Merge branch 'master' of git://git.denx.de/u-boot-net
- Various PHY fixes / enhancements.
- TI K2G fixes
2019-05-08 22:46:31 -04:00
James Byrne
83f71ef558 net: phy: micrel: Use correct skew values on KSZ9021
Commit ff7bd212cb ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.

The preceding commit c16e69f702 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).

This commit sorts out the resulting confusion in a consistent way by
making the following changes:

- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.

- Update the Micrel PHY driver to select the appropriate divisor for
both parts.

- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).

Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08 17:27:01 -05:00
Tom Rini
504bf790da Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- H6 Beelink GS1 board (Clément)
- Olimex A64-Teres-I board (Jonas)
- sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej)
- Change include order (Jagan)
- EPHY clock changes (Jagan)
- EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
2019-05-08 16:21:43 -04:00
Jonas Smedegaard
997b857ae3 sun50i: a64: Add Olimex A64-Teres-I board initial support
Olimex A64-Teres-I board is a mainboard (the only one so far)
for Olimex Teres-I DIY laptop kit.

Key features:
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 2GB DDR3 RAM
- MicroSD Slot
- 16GB eMMC Flash
- eDP LCD display
- HDMI
- USB Host
- Battery management
- 5V DC power supply
- Certified Open Source Hardware (OSHW)

Works:
- i2C
- MMC/SD
- PWM backlight

Known broken:
- Internal keyboard (seems to be because the keyboard firmware loads a
bootloader first, and then disconnects bootloader and connect real
keyboard). External ones connected to the USB port work fine.

This patch enables support for the A64-Teres-I board to u-boot,
including enabling screen backlight (lacking from Linux device-tree).

Linux commit details about the sun50i-a64-teres-i.dts sync:
"arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins"
(sha1: d91ebb95b96c8840932dc3a10c9f243712555467)

Cosmetic warnings regarding whitespace and placement of SPDX notice for
dts file was ignored.

config and .dtsi file are adapted from pinebook files.

Tested-by: Jonas Smedegaard <dr@jones.dk>
Signed-off-by: Jonas Smedegaard <dr@jones.dk>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: move board entry in MAINTAINERS file at proper position]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09 00:44:13 +05:30
Jagan Teki
d364e6bdd7 rockchip: dts: rk3399: Sync rk3399-nanopi4.dtsi from Linux
Sync rk3399-nanopi4.dtsi from Linux 5.1-rc2 tag.

Linux commit details about the rk3399-nanopi4.dtsi sync:
"arm64: dts: rockchip: Add nanopi4 bluetooth"
(sha1: 3e2f0bb72be36aa6c14ee7f11ac4dd8014801030)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
e0bca2821f rockchip: dts: rk3399: Sync pwm2_pin_pull_down from Linux 5.1-rc2
To make successful build with dts(i) files syncing from Linux 5.1-rc2
the rk3399.dtsi would require pwm2_pin_pull_down.

So, sync the pwm2_pin_pull_down node from Linux 5.1-rc2.  Since this
node is strictly not part of any commit alone, I have mentioned
Linux 5.1-rc2 tag for future reference of where would this sync
coming from.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
90430fa895 arm64: rockchip: dts: rk3399: Use rk3399-u-boot.dtsi
Now we have
- board specific -u-boot.dtsi files for board specific u-boot
  dts changes.
- soc specific rk3399-u-boot.dtsi for soc specific u-boot
  dts changes.

So, include the rk3399-u-boot-dtsi on respective board -u-boot.dtsi
and drop the properties which are globally available in rk3399-u-boot.dtsi

Right now rk3399-u-boot.dtsi has sdmmc, spi1 u-boot,dm-pre-reloc
property and more properties and nodes can be move further based
on the requirements.

This would fix, the -u-boot.dtsi inclusion for evb, firefly, puma
boards that was accidentally merged on below commit.
"rockchip: dts: rk3399: Create initial rk3399-u-boot.dtsi"
(sha1: e05b4a4fa8)

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
b5f88913a6 rockchip: dts: rk3399-u-boot: Add u-boot, dm-pre-reloc for spi1
Add u-boot,dm-pre-reloc property for spi1, so-that the
subsequent rk3399 boards which boot from SPI.

This help to separate the u-boot specific properties away
from base dts files so-that the Linux sync become easy and
meaningful.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
ddf49cbf35 arm64: rockchip: dts: rk3399: Add board -u-boot.dtsi files
Devicetree files in RK3399 platform is synced from Linux, like other
platforms does. Apart from these u-boot in rk3399 would also require
some u-boot specific node like dmc.

dmc node has big chunk of DDR timing parameters which are specific
to specific board, and maintained with rk3399-sdram*.dtsi.

So, create board specific -u-boot.dtsi files and move these sdram dtsi
files accordingly. This would help of maintain u-boot specific changes
separately without touching Linux dts(i) files which indeed easy for
syncing from Linux between releases.

These board specific -u-boot.dtsi can be extendible to add more u-boot
specific nodes or properties in future.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Jagan Teki
82d08de9c5 dts: Makefile: Build rockchip dtbs based on SoC types
- Sometimes u-boot specific dtsi files are included
  automatically which would build for entire rockchip SoC,
  even-though the respective dtsi should used it for specific
  family of rockchip SoC.
- Sometimes u-boot specific dts nodes or properties can use
  config macros from respective rockchip family include/configs
  files, example CONFIG_SPL_PAD_TO.

So, it's better to compile the dtbs based on the respective
rockchip family types rather than rockchip itself to avoid
compilation issues.

This patch organize the existing dtb's based on the rockchip
family types.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:13 +08:00
Simon Glass
ec107f04b6 rockchip: chromebook_minnie: Enable sound
Enable sound for this board, which has the same codec as jerry.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
615e9b3cce rockchip: px5: add timer0 dts node as tick timer
Let's use rockchip timer before stimer patches can be merged.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
4d9dd40d68 rockchip: px5 update dts for spl/tpl
TPL need dmc to init ddr sdram, and emmc, boot-order.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08 17:34:12 +08:00
Kever Yang
d55dbfed16 rockchip: rk322x: dts: enable uart2 for SPL/TPL
When we use DM_SERIAL for serial driver, we need enable the
dts node for the debug console.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
Tom Rini
8d7f06bbbe Merge branch 'master' of git://git.denx.de/u-boot-sh
- RZ/A1 addition.
- Old board removal.
2019-05-07 09:38:00 -04:00