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28 commits

Author SHA1 Message Date
Poddar, Sourav
62d206dc31 armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,

f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)

fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07 17:55:51 +05:30
Matt Porter
c97a9b3275 omap5: add qspi support
Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-07 17:55:50 +05:30
Mugunthan V N
f986d97208 ARM: DRA7xx: Enable GMAC clock control
Enabling CPSW module by enabling GMAC clock control

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Lokesh Vutla
65e9d56fb9 ARM: DRA7xx: Lock DPLL_GMAC
Locking DPLL_GMAC

[mugunthanvnm@ti.com:Configure only if CPSW is selected]

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2013-07-26 16:39:11 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Axel Lin
87bd05d78f ARM: OMAP: GPIO: Fix valid range and enable usage of all GPIOs on OMAP5
The omap_gpio driver is used by AM33XX, OMAP3/4, OMAP54XX and DRA7XX SoCs.
These SoCs have different gpio count but currently omap_gpio driver uses hard
coded 192 which is wrong.

This patch fixes this issue by:
1. Move define of OMAP_MAX_GPIO to all arch/arm/include/asm/arch-omap*/gpio.h.
2. Update gpio bank settings and enable GPIO modules 7 & 8 clocks for OMAP5.

Thanks for Lubomir Popov to provide valuable comments to fix this issue.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Tested-by: Lubomir Popov <lpopov@mm-sol.com>
Acked-by: Heiko Schocher <hs@denx.de>
2013-07-02 09:21:16 -04:00
Sricharan R
92b0482c17 ARM: DRA7xx: EMIF: Change settings required for EVM board
DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
97405d843e ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-06-10 08:43:10 -04:00
Nishanth Menon
18c9d55ac6 ARM: OMAP5: DRA7xx: support class 0 optimized voltages
DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:10 -04:00
Lokesh Vutla
63fc0c775c ARM: DRA7xx: power Add support for tps659038 PMIC
TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
4ca94d8186 ARM: OMAP4+: pmic: Make generic bus init and write functions
Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Lokesh Vutla
af1d002f89 ARM: OMAP2+: Rename asm/arch/clocks.h asm/arch/clock.h
To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
Sricharan R
bcdd8f72f3 ARM: OMAP5: clocks: Do not enable sgx clocks
SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-06-10 08:43:09 -04:00
SRICHARAN R
f92f2277a6 ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
These defines are same across OMAP4/5. So move them to
omap_common.h. This is required for the patches that
follow.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
2013-05-10 08:25:56 -04:00
Lubomir Popov
2bcc785a1e OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work
USB TLL clocks do not support 'explicit_en', only 'hw_auto'
control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be
moved to the clk_modules_hw_auto_essential[] array in order
to make the clock work.

This fix is needed (but not sufficient) for USB EHCI operation
in U-Boot.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Lubomir Popov
3935277dbf OMAP5: I2C: Enable i2c5 clocks
I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The i2c5 clock was however not enabled; do this here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
2013-05-10 08:25:55 -04:00
Lokesh Vutla
7831419d7b arm: dra7xx: Add DDR related data for DRA752 ES1.0
DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
8b12f1779e arm: dra7xx: Add control module changes
Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
ea8eff1fe0 arm: dra7xx: clock: Add the dplls data
A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
d4e4129c31 arm: dra7xx: clock: Add the prcm changes
PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
2013-03-11 11:06:11 -04:00
Lokesh Vutla
9100edecf8 ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
47abc3df70 ARM: OMAP4/5: clocks: Add the required OPP settings as per the latest addendum
Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.

While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x

Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
afc2f9dcf1 ARM: OMAP5: clock: Add the prcm register changes required for ES2.0
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
ef1697e99f ARM: OMAP5: Clean up iosettings code
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
Lokesh Vutla
c43c8339fe ARM: OMAP4+: Make control module register structure generic
A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
3fcdd4a5f8 ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:10 -04:00
SRICHARAN R
ee9447bfe3 ARM: OMAP4+: Cleanup the clocks layer
Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-03-11 11:06:09 -04:00
SRICHARAN R
01b753ff7b ARM: OMAP4+: Change the PRCM structure prototype common for all Socs
The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.

Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-03-11 11:06:09 -04:00