PHYs on SGMII riser card are used in SGMII mode with different external
IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type
under ethernet node should be updated. Otherwise the PHY interrupt can not
be handled therefor PHY link state change can not be auto detected.
For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed
but it's still be kept to guarantee the sgmii mode could work with old
device tree.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.
Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.
Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add TLB mappings, board target options, and configuration items
need for SPI/SD boot.
Since P1022DS RevB board, the NOR flash have been changed to 16 bit/28bit
address flash, therefore, when SDHC/ESPI booting and access to eLBC,
the PMUXCR[0~1] must be set to 10b, and PMUXCR[9~10] must be set to
00b for them.
Configure the PX_BRDCFG0[0~1] to 10b which is connected to
SPI devices as SPI_CS(0:3)_B.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Jiang Yutang <b14898@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This patch adds SDRAM detection feature to km82xx boards.
To enable this feature, define CONFIG_SYS_SDRAM_LIST as the initializer
for an array of struct sdram_conf_s.
These structs will expose the bitfields within registers PSDMR and OR1 which
have to be different between configurations; common bitfields will be
defined, as usual, within CONFIG_SYS_PSDMR and CONFIG_SYS_OR1.
If CONFIG_SYS_SDRAM_LIST is not defined, then the usual behavior is retained.
Signed-off-by: Gerlando Falauto <gerlando.falauto@keymile.com>
* 'master' of git://git.denx.de/u-boot-i2c:
km/common: remove printfs for i2c deblocking code
CONFIG: SMDK5250: I2C: Enable I2C
I2C: Add support for Multi channel
I2C: Modify the I2C driver for EXYNOS5
I2C: Move struct s3c24x0_i2c to a common place.
EXYNOS: PINMUX: Add pinmux support for I2C
EXYNOS5: define EXYNOS5_I2C_SPACING
EXYNOS: Add I2C base address.
EXYNOS: CLK: Add i2c clock
mx6qsabrelite: add i2c multi-bus support
imx-common: add i2c.c for bus recovery support
i.mx53: add definition for I2C3_BASE_ADDR
i.mx: iomux-v3.c: move to imx-common directory
i.mx: iomux-v3.h: move to imx-common include directory
iomux-v3: remove include of mx6x_pins.h
mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS support
mxc_i2c: add bus recovery support
mxc_i2c: prep work for multiple busses support
mxc_i2c: add i2c_regs argument to i2c_imx_stop
mxc_i2c: add retries
mxc_i2c: check for arbitration lost
mxc_i2c: change slave addr if conflicts with destination.
mxc_i2c: don't disable controller after every transaction
mxc_i2c: place i2c_reset code inline
mxc_i2c: place imx_start code inline
mxc_i2c: remove redundant read
mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into wait_for_sr_state
mxc_i2c.c: code i2c_probe as a 0 length i2c_write
mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_write
mxc_i2c: create i2c_init_transfer
mxc_i2c: clear i2sr before waiting for bit
mxc_i2c: create tx_byte function
mxc_i2c: remove ifdef of CONFIG_HARD_I2C
mxc_i2c: fix i2c_imx_stop
i2c: deblock i2c bus also if accessed before realocation
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-microblaze:
microblaze: Wire up SPI driver
spi: microblaze: Adds driver for Xilinx SPI controller
microblaze: intc: Clear interrupt code
microblaze: Call serial multi initialization
microblaze: Move __udelay implementation
microblaze: Remove extern from board.c
microblaze: Wire up dts configuration
fdt: Add board specific dts inclusion
microblaze: Move individual board linker scripts to common script in cpu tree.
microblaze: Add gpio.h
microblaze: Add missing undefs for UBI and UBIFS
microblaze: Expand and correct configuration comments
microblaze: Enable ubi support
microblaze: Avoid compile error on systems without cfi flash
microblaze: Remove wrong define CONFIG_SYS_FLASH_PROTECTION
Conflicts:
drivers/spi/Makefile
Signed-off-by: Wolfgang Denk <wd@denx.de>
This code will also be used before reallocation and during this time we
are not allowed to do these printings.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Prafulla Wadaskar <Prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
This enables I2C support on smdk5250.
Pinmux setting moved to board file to avoid repeated setting of
gpio lines.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
* 'next' of git://git.denx.de/u-boot:
MPC8xx: Fixup warning in arch/powerpc/cpu/mpc8xx/cpu.c
doc: cleanup - move board READMEs into respective board directories
net: sh_eth: add support for SH7757's GETHER
net: sh_eth: modify the definitions of regsiter
net: sh_eth: add SH_ETH_TYPE_ condition
net: sh_eth: clean up for the SH7757's code
net: fec_mxc: Fix MDC for xMII
net: fec_mxc: Fix setting of RCR for xMII
net: nfs: make NFS_TIMEOUT configurable
net: Inline the new eth_setenv_enetaddr_by_index function
net: allow setting env enetaddr from net device setting
net/designware: Consecutive writes to the same register to be avoided
CACHE: net: asix: Fix asix driver to work with data cache on
net: phy: micrel: make ksz9021 phy accessible
net: abort network initialization if the PHY driver fails
phylib: phy_startup() should return an error code on failure
net: tftp: fix type of block arg to store_block
Signed-off-by: Wolfgang Denk <wd@denx.de>
Also drop a few files referring to no longer / not yet supported
boards.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
This fixes:
cmd_bc3450.c:55:0: warning: "CONFIG_SYS_CPU" redefined [enabled by default]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
In commit 1a89a217f5 we moved most of the
required pads and mux data for USB to the essential list so that later
on we could NOT enable anything that wasn't essential unless otherwise
configured. This was however missing a few pandaboard-specific parts
which left for example USB ethernet non-functional.
Tested this on OMAP4430 ES2.2, OMAP4460 ES1.1 PANDA boards.
(Reworded by Tom Rini to be more precise about what the problem was)
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Tested-by: Gary Thomas <gary@mlbassoc.com>
Tested-by: Tom Rini <trini@ti.com>
Add I2C support.
Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
- enable OF control and embedded OF
- set default device tree file name to 'microblaze'
- add CPP to dtc proxy: board/xilinx/dts/microblaze.dts
- add an empty but processable dts for microblaze-generic
Signed-off-by: Stephan Linz <linz@li-pro.net>
When Trimslice is booted from serial flash, the boot ROM does this, so
U-Boot doesn't need to. However, booting from the SD slot for recovery
purposes, the boot ROM does not set up the pinmux for serial flash. Add
code to U-Boot to set this up, so that an SD-based recovery U-Boot image
can upgrade the U-Boot in serial flash.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Boards can override this to set up the pinmux correctly to access serial
flash.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Missed some boards after my tegra2_mmc.* -> tegra_mmc.* change, and
one instance of CONFIG_TEGRA2_SPI. MAKEALL -s tegra2 AOK, Seaboard MMC
AOK. Didn't test Tamonten, Paz00 or TrimSlice, as I have none here.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
GPIO PI6 can be used to obtain the write-protect status of an SD card
inserted into the SD slot.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The PI4 GPIO is used on Tamonten to reset carrier board peripherals.
Power sequencing hardware on the carrier pulls the reset low before
powering up the Tegra, and the CPU is supposed to signal readiness,
and therefore bring peripherals out of reset by pulling PI4 high.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The new gpio_early_init() function, which does nothing by default, can
be overridden by boards to configure GPIOs at an early stage.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Device tree support is required for working USB host support, which in
turn enables ethernet support.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Device tree support is required for working USB host support, which in
turn enables ethernet support.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit uses the common Tegra board implementation instead of
duplicating a lot of the code. In addition, the Plutux and Medcom
specific board files can be removed as the MMC/SD setup is common
among all Tamonten-based boards.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
* 'master' of git://git.denx.de/u-boot-arm: (212 commits)
ARM: cache: Move the cp15 CR register read before flushing the cache.
ARM: introduce arch_early_init_r()
PXA: Enable CONFIG_PREBOOT on zipitz2
ARM: mx28: Remove CONFIG_ARCH_CPU_INIT
No need to define CONFIG_ARCH_CPU_INIT.
add new board vl_ma2sc
MTD: SPEAr SMI: Add write support for length < 4 bytes
i2c: designware_i2c.c: Add support for the "i2c probe" command
rtc/m41t62: Add support for M41T82 with HT (Halt Update)
SPL: ARM: spear: Add SPL support for SPEAr600 platform
Makefile: Add u-boot.spr build target (SPEAr)
SPL: ARM: spear: Remove some objects from SPL build
SPL: lib/Makefile: Add crc32.c to SPL build
SPL: common/Makefile: Add image.c to SPL build
arm: Don't use printf() in SPL builds
GPIO: Add SPEAr GPIO driver
net: Multiple updates/enhancements to designware.c
cleanup/SPEAr: Define configuration flags more elegantly
cleanup/SPEAr: Remove unnecessary parenthesis
SPEAr: Correct SoC ID offset in misc configuration space
SPEAr: explicitly select clk src for UART
SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access
SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb
SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro
SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE
SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION
SPEAr: Enable dcache for fast file transfer
SPEAr: Enable autoneg for ethernet
SPEAr: Enable udc and usb-console support only for usbtty configuration
SPEAr: Enable usb device high speed support
SPEAr: Initialize SNOR in early_board_init_f
SPEAr: Change the default environment variables
SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK)
SPEAr: Add configuration options for spear3xx and spear6xx boards
SPEAr: Add basic arch related support for SPEAr SoCs
SPEAr: Add interface information in initialization
SPEAr: Add macb driver support for spear310 and spear320
SPEAr: Configure network support for spear SoCs
SPEAr: Place ethaddr write and read within CONFIG_CMD_NET
SPEAr: Eliminate dependency on Xloader table
SPEAr: Fix ARM relocation support
st_smi: Fixed page size for Winbond W25Q128FV flash
st_smi: Change timeout loop implementation
st_smi: Fix bug in flash_print_info()
st_smi: Change the flash probing method
st_smi: Removed no needed dependency on ST_M25Pxx_ID
st_smi: Fix smi read status
st_smi: Move status register read before modifying ctrl register
st_smi: Read status until timeout happens
st_smi: Enhance the error handling
st_smi: Change SMI timeout values
st_smi: Return error in case TFF is not set
st_smi: Add support for SPEAr SMI driver
mtd/NAND: Remove obsolete SPEAr specific NAND drivers
SPEAr: Configure FSMC driver for NAND interface
mtd/NAND: Add FSMC driver support
arm/km: remove calls to kw_gpio_* in board_early_init_f
arm/km: add implementation for read_dip_switch
arm/km: support the 2 PCIe fpga resets
arm/km: skip FPGA config when already configured
arm/km: redefine piggy 4 reg names to avoid conflicts
arm/km: cleanup km_kirkwood boards
arm/km: enable BOCO2 FPGA download support
arm/km: remove portl2.h and use km_kirkwood instead
arm/km: convert mgcoge3un target to km_kirkwood
arm/km: add kmcoge5un board support
arm/km: add kmnusa board support
arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
cm-t35: fix incorrect NAND_ECC layout selection
ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls.
ARM: OMAP4/5: Move USB pads to essential list.
ARM: OMAP4/5: Move USB clocks to essential group.
ARM: OMAP4/5: Move gpmc clocks to essential group.
ARM: OMAP4+: Move external phy initialisations to arch specific place.
omap4: Use a smaller M,N couple for IVA DPLL
da850/omap-l138: Enable auto negotiation in RMII mode
omap: am33xx: accomodate input clocks other than 24 Mhz
omap: emif: fix bug in manufacturer code test
omap: emif: deal with rams that return duplicate mr data on all byte lanes
OMAP4+: Force DDR in self-refresh after warm reset
OMAP4+: Handle sdram init after warm reset
ARM: OMAP3+: Detect reset type
arm: bugfix: Move vector table before jumping relocated code
Kirkwood: Add support for Ka-Ro TK71
arm/km: use spi claim bus to switch between SPI and NAND
arm/kirkwood: protect the ENV_SPI #defines
ARM: don't probe PHY address for LaCie boards
lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2
lacie_kw: fix SDRAM banks number for net2big_v2
Kirkwood: add lschlv2 and lsxhl board support
net: add helper to generate random mac address
net: use common rand()/srand() functions
lib: add rand() function
kwboot: boot kirkwood SoCs over a serial link
kw_spi: add weak functions board_spi_claim/release_bus
kw_spi: support spi_claim/release_bus functions
kw_spi: backup and reset the MPP of the chosen CS pin
kirkwood: fix calls to kirkwood_mpp_conf
kirkwood: add save functionality kirkwood_mpp_conf function
km_arm: use filesize for erase in update command
arm/km: enable mii cmd
arm/km: remove CONFIG_RESET_PHY_R
arm/km: change maintainer for mgcoge3un
arm/km: fix wrong comment in SDRAM config for mgcoge3un
arm/km: use ARRAY_SIZE macro
arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE
arm/km: add piggy mac adress offset for mgcoge3un
arm/km: add board type to boards.cfg
AT91SAM9*: Change kernel address in dataflash to match u-boot's size
ATMEL/PIO: Enable new feature of PIO on Atmel device
ehci-atmel: fix compiler warning
AT91: at91sam9m10g45ek : Enable EHCI instead OHCI
Atmel : usb : add EHCI driver for Atmel SoC
Fix: AT91SAM9263 nor flash usage
Fix: broken boot message at serial line on AT91SAM9263-EK board
i.MX6 USDHC: Use the ESDHC clock
mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register
i.MX28: Add function to adjust memory parameters
mx28evk: Fix PSWITCH key position
mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition
mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition
mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition
mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition
imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
mx53ard: Remove unused CONFIG_MII_GASKET
mx6: Avoid writing to read-only bits in imximage.cfg
m28evk: use same notation to alloc the 128kB stack
...
Signed-off-by: Wolfgang Denk <wd@denx.de>
* add support for board VL+MA2SC
* adds vl_ma2sc_config for standard NOR boot configuration
* adds vl_ma2sc_ram_config for RAM load configuration
Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
Enable data cache with 1:1 mapping of DDR to enable fast file
transfer over tty which was doing lot of copy.
This feature is enabled only for flashing operation i.e. when
CONFIG_SPEAR_USBTTY is enabled.
This has been tested on SPEAr320, SPEAr600 and SPEAr900 evaluation
boards.
Following figures show an estimate on the performance improvements. The
test setup was a Linux host (not Windows) and involved measurement of
only binary transfer time, through kermit. The flash erase and flash
copy time would be unaffected by these patches.
Another thing is this that the timings remained more or less same across
ARM9 and Cortex based devices, hence reporting only one of the cases.
Before Enhancements
===================
$ time ukermit.small -p /dev/ttyACM0 -f spear320_uImage.img
Downloading file: 100.00% completed(2014080/2014080 bytes)
real 0m41.228s
user 0m0.002s
sys 0m0.064s
After Enhancements
==================
$ time ukermit.large -p /dev/ttyACM0 -f spear320_uImage.img
Downloading file: 100.00% completed(2014080/2014080 bytes)
real 0m5.441s
user 0m0.001s
sys 0m0.001s
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
flash reading is required earlier than flash_init is called since the env_init
is called before flash_init. This makes the smi_init necessary before env_init
being called.
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds options for all the below mentioned configurations and
subsequently renames the include/configs/spearxxx.h files to spear3xx_evb.h,
spear6xx_evb.h etc to depict evaluation board configuration.
SPEAr3xx and SPEAr6xx boards can be compiled in following configurations
1. Environment placed in NAND
2. Console on usb device
3. Console on usb device with environment placed in NAND
4. SPEAr310 and SPEAr320 support environment variables in parallel
NOR flash.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Few Designware peripheral registers need to be modified based on the
ethernet interface selected by the board. This patch supports interface
information in ethernet driver
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The
driver for this device is already supported by u-boot, so configuring
board configuration file and defining base addresses etc to make use
of the common driver
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
ethaddr can be optionally read from i2c memory. So, chip_config command supports
reading/writing hw mac id into i2c memory. Placing this code within
CONFIG_CMD_NET as this would only be needed when network interface is configured
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Xloader table was used primarily to inform u-boot about the DDR size. However,
now the ddr size is calculated at runtime which eliminates any need for the
Xloader table. So removing this unnecessary code.
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
While the u-boot code is running from the flash, it is essential that no access
is made to the bss segment. This is due to the fact that .rel.dyn and .bss areas
overlap and former contains information used in relocation. In SPEAr, this was
not taken into consideration. As a result, while the relocation wasn't complete,
dram_init populated an uninitialized global variable resulting in corruption of
.rel.dyn area, which resulted in u-boot crash.
This commit fixes this problem by removing code that accesses bss segment
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Since FSMC is a standard IP and it supports different memory interfaces, it
is supported independent of spear platform and spear is configured to use that
driver for interfacing with the NAND device
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
These functions tried to access two static tables before relocation
(board_early_init_f is executed before relocation). But these static
tables lie in the bss section which is not valid before relocation.
These accesses then overwrote some parts of u-boot binary before it was
relocated. For the kmnusa build, this results in a corrupted important
env variable (bootcmd) but it may be that some other parts of the u-boot
binary are corrupted.
This patch solves this problem by moving all the kw_gpio_* calls to
board_init, which should be early enough in the boot sequence. The only
calls that could not be moved is the one for the SOFT (bitbang) I2C, and
they have been replaced by a direct access to the GPIO dataout Control
register to set the two GPIOs as output.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Add a function to read the dip_switch on kmcoge5un. If the
switch is set the actual_bank is set to 0 and this SW is
booted.
Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
The PCIe FPGAs now have to support 2 resets: one for the non traffic
affecting part (PCIe) and one for the traffic affecting part.
When the FPGA is not reconfigured, we only reset the PCIe part.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
In order to be able to perform board resets without interrupting the
traffic, the configuration of an already properly configured FPGA is
skipped.
This is because some PCIe FPGAs embed some other function that must
continue to work over reset.
It is then the responsibility of the application to trigger a
reconfiguration when needed. This is done by lowering the FPGA_INIT_B
pin for delaying the configuration to u-boot @ next reboot, and then
lower the FPGA_PROGRAM_B signal.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Some very similar #defines for reg addresses are used in a later patch
(managed_switch support for km_arm).
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This adds a first support of the FPGA download for a PCIe FPGA based
on the BOCO2 CPLD.
This takes place in 3 steps, all done accessing the SPICTRL reg of the
BOCO2:
1) start the FPGA config with an access to the FPGA_PROG bit
2) later in the boot sequence, wait for the FPGA_DONE bit to toggle to 1
for the end of the FPGA configuration (with a timeout)
3) reset the FPGA
4) finally remove the access to its config EEPROM from the FPGA so that
the CPU can update the FPGA configuration when the kernel is running
The boards with a PCIe FPGA but without BOCO2 still are supported.
The config option name is CONFIG_KM_FPGA_CONFIG
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
The additional headerfile is unneeded here, we can use the generic
km_kirkwood.h instead. And we can use the better config option
KM_PIGGY4_88E6061 for the specific features for boards with this
design in km_arm.c.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
Use the generic header km_kirkwood.h and get rid of the
board specific header.
changes for v2: rebased because of changes in other patches
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
For u-boot this board is similar to mgcoge3un. But some differences
are present. We have a different SDRAM on it and therefore a new
SDRAM config file. Additionaly this board has a direct MAC/MAC
connection from the kirkwood to a marvell simple switch without a
phy inbetween, this needs a new configuration for the mvgbe driver.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This board is similar to portl2, but it has the u-boot environment
in a SPI NOR flash and not in an i2c eeprom like portl2 have.
Some other details:
- IVM EEPROM is at adress: pca9547:70:9
- PCI is enabled
- PIGGY4 is connected via MV88E6352 simple switch. There is no phy
between the simple switch and the kirkwood.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
USB module pads are getting enabled under non-essential
group. These will be required for fastboot, tftp support.
So move this to essential list to have them working when
non-essential pads are no more muxed.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
We overwrite these weak functions from the kirkwood spi code to
use our own method to be able to switch between the SPI NOR and
the NAND flash. This is needed e.g. to update the u-boot. The former
command do_spi_toggle can therefore be removed. And the usage of
this command is removed from the u-boot update command in the
u-boot environment.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
The command miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr) always
returns 8 for the PHY address. It is the reset value for the PHY
Address Register. Obviously, this default value could be incorrect.
Moreover, as the PHY address is well known, there is no need to
auto-detect it.
Now, the PHY address must given as a parameter to the PHY initialization
function. Additionally this patch also fixes some aesthetic issues.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
This patch adds support for both the Linkstation Live (LS-CHLv2) and
Linkstation Pro (LS-XHL) by Buffalo.
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
With the new second save argument introduced by the previous patch, all
the calls to the function had to be fixed.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
On at91sam platforms, u-boot grew larger than the allocated size in
dataflash, the layout was:
bootstrap 0x00000000
ubootenv 0x00004200
uboot 0x00008400
kernel 0x00042000
fs 0x00252000
u-boot with the defconfig doesn't seem to fit in 0x42000 - 0x8400 =
0x39C00 bytes anymore.
Now, the layout is:
bootstrap 0x00000000
ubootenv 0x00004200
uboot 0x00008400
kernel 0x00084000
fs 0x00294000
Signed-off-by: Alexandre Belloni <alexandre.belloni@piout.net>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
There is no .S file in this directory, so just remove SOBJS.
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
There is no .S file in this directory, so just remove SOBJS.
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
There is no .S file in this directory, so just remove SOBJS.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
There is no .S file in this directory, so just remove SOBJS.
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
There is no .S file in this directory, so just remove SOBJS.
Cc: Jason Liu <r64343@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Original code was assuming that the fuse revision version for all mx53loco boards
based on Dialog PMIC was the same, which is not the case.
Force the revision of all Dialog-based boards to 0.
This fixes a kernel crash when PMIC is accessed in the 2.6.35 kernel
for Dialog rev E boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Use the pinmux configuration function for SMDK5250.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
In the MAX8997, LDO regulators needs to preserve previously set voltage
values.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
panel_info data structure is gloable variable, so, I have initialized it
in board file. If it is initialized in init_panel_info() like existing,
it can't be used in drv_lcd_init() in common/lcd.c because
init_panel_info() is called after drv_lcd_init().
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Buffer the PCB revision to avoid multiple eeprom accesses
for the same data and print it as a part of board information.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tom Rini <trini@ti.com>
Legacy eeprom layout represents the revision number syntactically
(i.e. revision 1.00 is written as 0x100). This is inconsistent with
the representation in newer layouts, where it is defined semantically
(i.e. 0x64).
This patch fixes the issue by replacing the syntactic representation
with the semantic one.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Non-legacy layouts have an extended revision field,
but only the first 2 bytes are the PCB revision.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
- change gpio pin settings:
- gpio pin 6[13] (PLC reset) default value low
- gpio pin 6[0] (TPM reset) default value low
- 4 new GPIO pins
pin i/o name
- 3[9] input Board Type
- 2[7] input HW-ID0
- 2[6] input HW-ID1
- 2[3] input HW-ID2
- read board type and hw id from gpio pins on the enbw_cmc board,
and use board type for setting up different gpio pin settings.
- do not pass "davinci_mmc.use_dma=0" to linux, as MMC now
works with DMA.
- update logbuf support:
store post word in RTC scratch register
- add support for configuring KSZ8864RMN switch through
a config file on u-boot startup. For more infos see:
doc/README.switch_config
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Fix the .dts file USB unit addresses not to duplicate each-other.
Fix the board name string to indicate the vendor is Compulab not NVIDIA.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
In anticipation of Tegra3 support, continue removing/renaming
Tegra2-specific files. No functional changes (yet).
Updated copyrights to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
In anticipation of Tegra3 support, start removing/renaming
Tegra2-specific files. No functional changes (yet).
Also updated copyright to 2012.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add a device tree for Ventana; the Seaboard file no longer represents
the HW present on Ventana.
Enable USB on Ventana.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
... to enable USB host support, which enables Ethernet support.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
... to enable USB host support, which enables Ethernet support.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:
E1120 motherboard
E1108 CPU board
E1116 PMU board
The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.
Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass's proposal to fix this on Seaboard was NAK'd, so I
removed his NS16550 references and added a small delay before
SPI/UART muxing. Tested on my Seaboard with large SPI reads/writes
and saw no corruption (crc's matched) and no spurious comm chars.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.
Signed-off-by: York Sun <yorksun@freescale.com>
On p1010rdb some signals are muxed for tdm/can/uart/flash.
If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly,
defaultly we keep spi chip selection to spi-flash instead of to
tdm/slic and disable uart1 when not using flexcan, as well disable sdhc.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
is an integrated device that targets Femto base station market. It combines
Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
MAPLE-B2F baseband acceleration processing elements
BSC9131RDB Overview
-----------------
-1Gbyte DDR3 (on board DDR)
-128Mbyte 2K page size NAND Flash
-256 Kbit M24256 I2C EEPROM
-128 Mbit SPI Flash memory
-USB-ULPI
-eTSEC1: Connected to RGMII PHY
-eTSEC2: Connected to RGMII PHY
-DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.
This patch adds support for mainly Power side functionalities and peripherals
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
The value of ET0_ERXD6 and GPSR1_INIT was wrong.
This fixes them.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Exactly one board has defined CONFIG_SYS_PROMPT_HUSH_PS2 to a value
different than "> " which is vision2. I have Cc'd the maintainer here
as I strongly suspect this is a bug rather than intentional behavior.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Stefano Babic <sbabic@denx.de>
We provide a default table of { 9600, 19200, 38400, 57600, 115200 }
in <config_fallbacks.h> which mkconfig places after <configs/...h> in
the generated config file. This is used when a board has not set its
own table.
Signed-off-by: Tom Rini <trini@ti.com>
If the testpin is asserted, first check if a test_bank
variable is defined before trying to boot this
test_bank.
Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
On kmcoge5ne we have a dip switch present. If this switch
was switched on the actual_bank is set to 0 and this SW
will be booted.
Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
kmcoge5ne starts the post tests if the testpin on
the board was enabled. Currently it does simply a memory
test.
Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Enabled application buffers in uboot to allow application chipselect
access in uboot.
Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The MAC address begins at offset 1.
Signed-off-by: Thomas Herzmann <thomas.herzmann@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This board is a MPC8360 board. Two flashes are present
a NOR flash were u-boot and the u-boot environment is stored
and a NAND flash for the application code. This board has 512MB
SDRAM.
Additionaly we introduce a common km8360.h file and convert kmeter1 to
use this.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Christian Herzig <christian.herzig@keymile.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
If the ram size isn't locked to 2GiB, the get_ram_size() may hang up.
Signed-off-by: Christian Herzig <christian.herzig@keymile.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Gerlando Falauto <gerlando.falauto@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* 'master' of git://git.denx.de/u-boot-video:
video: atmel/lcd: add LCD driver for new Atmel SoC
video: cfb_console: flush dcache for frame buffer in DRAM
cfb_console: Ignore bell character
cfb_console: Add console_clear_line function
cfb_console: Fix function console_back
omap3_dss: cosmetic changes
omap3_dss: add optional framebuffer
mx53loco: Add LCD support
mx5: Rename mx51_fb_init()
mx53: Allow IPUv3 driver to also work on mx53
mx51evk: Add LCD support
EXYNOS: display 32bpp bitmap TIZEN logo
create lib/tizen directory
LCD: display 32bpp decompressed bitmap image
common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef
common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs
common/lcd.c: use ARRAY_SIZE
cmd_bmp.c: make bmp_display() usable by drivers or board code
LCD: support another s6e8ax0 panel type
LCD: change s6e8ax0 panel gamma value
include/video.h: drop unused video_printf()
Signed-off-by: Wolfgang Denk <wd@denx.de>
This is an sh2a device (max 266MHz) with FPU, video display
controller (VDC), 8 serial ports, 4 I2C channels, 3 CAN ports,
SD and on-chip USB.
The RSK2+SH7269 board uses the SH7269 processor. It is often
referred to as just rsk7269.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The AP-SH4A-4A board has SH7734, 64MB DDR2-SDRAM, USB,
Ethernet, and more.
This patch supports the following functions:
- 64MB DDR2-SDRAM
- 16MB NOR Flash memory
- Serial console (SCIF)
- Ethernet (SH-Ether with Gigabit)
- I2C
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This read MAC address from Serial EEPROM and set.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
The r0p7734 board has SH7734, 128MB DDR2-SDRAM, USB,
Ethernet, and more.
This patch supports the following functions:
- 128MB DDR2-SDRAM
- 32MB NOR Flash memory
- Serial console (SCIF)
- Ethernet (SH-Ether/SMSC)
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Add support for CLAA07LC0ACW LCD that connects to the mx53loco board.
Configure the board to show the Linux logo on the LCD.
Also increase the size of CONFIG_SYS_MALLOC_LEN variable to take into account
the framebuffer usage.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
The ipuv3 driver is currently only used on mx51, but it can be extended to work
on mx53 and mx6 as well.
Rename mx51_fb_init(), so that it can be used by other SoCs.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Add support for CLAA07LC0ACW LCD that connects to the mx51evk board.
Configure the board to show the Linux logo on the LCD.
Also increase the size of CONFIG_SYS_MALLOC_LEN variable to take into account
the framebuffer usage.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch supports drawing 32bpp bitmap TIZEN logo in exynos fb.
"tizen_hd_logo.h" data is compressed from trats_logo.bmp to
trats_logo.bmp.gz by gzip and converted to tizen_hd_logo.h header file
format by some application. The logo data is decompressed in the exynos
fb driver by bmp_display().
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
s6e8ax0 panel has many panel of types. This patch support another panel
on TIZEN lunchbox board(HWREVISION 2). This panel has reversed panel
display type. So, I had added necessary command.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
These are all the files which use the API incorrectly but did not get
built using MAKEALL -a powerpc|arm. I have no compiler for them, but
the remaining issues should be far less than without this patch.
Any outstanding issues are left to the maintainers of boards that use
these drivers.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Some copy/pasted drivers redefine functions
defined in include/net.h. Remove these so that
the definitions can be changed without error.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Fix this:
cpci405.c: In function 'do_get_bpip':
cpci405.c:737:4: warning: format '%ld' expects type 'long int', but argument 3 has type 'IPaddr_t'
cpci405.c:737:4: warning: format '%ld' expects type 'long int', but argument 4 has type 'IPaddr_t'
cpci405.c:737:4: warning: format '%ld' expects type 'long int', but argument 5 has type 'IPaddr_t'
cpci405.c:737:4: warning: format '%ld' expects type 'long int', but argument 6 has type 'IPaddr_t'
cpci405.c:700:8: warning: unused variable 'bd'
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
This field gets read in one place (by "bdinfo"), and we can replace
that with getenv("ipaddr"). After all, the bi_ip_addr field is kept
up-to-date implicitly with the value of the ipaddr env var.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
If uart2 is enabled during boot, spurious wifi chip transmission will
hang the module and it is impossible to recover from this situation
without hard reset. This will prevent any l4_per domain idle
transitions.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Seaboard uses a QUERTY keyboard. We add key codes for this to
enable key scanning to work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This adds timings for T20 and T25 Seaboards, using the bindings found here:
http://patchwork.ozlabs.org/patch/132928/
We supply both full speed options for normal running, and half speed options
for testing / development.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Set Seaboard to optimal memory settings based on the SOC in use (T20 or T25).
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra core power rail has leakage voltage around 0.2V while system in
suspend mode. The source of the leakage should be coming from PMC power
detect logic for IO rails power detection.
That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0'
to PWR_DET (APBDEV_PMC_PWR_DET_0).
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Call the function to put warmboot boot in a suitable place for resume.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
There is no need to set the VBUS power enable to 0 first and then to 1.
Set it to 1 in the gpio_direction_output() function.
While at it, use the standard naming convention for the GPIO comment.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
FSL 2.6.35 kernel assumes that the bootloader passes the CONFIG_REVISION_TAG information.
The kernel uses this data to distinguish between Dialog versus mc34708 based boards,
and also to distinguish between revA and revB of the mc34708 based boards.
Suggested-by: Yu Li <yk@magniel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
On the mx53loco board with mc34708 PMIC it is necessary to turn on VUSB regulator
so that the mx53 USBH1 PHY receives the 3.3V voltage.
Tested by inserting a USB pen drive in the upper USB slot (USBH1) and then issued the
commands:
usb start
usb info
,which correctly detected and printed the USB pen drive information.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add mc34708 support and set mx53 core frequency at its maximum value of 1GHz.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
As mx53loco board has two variants: one with Dialog PMIC and another with FSL MC34708 PMIC,
we need to be able to build both drivers.
Change pmic_init() and PMIC_NUM_OF_REGS names to avoid build conflicts when both drivers are present.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
NAND support is not enabled by default because Eval Kit is not delivered
with NAND chip. To enable NAND support add CONFIG_CMD_NAND to board config.
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Acked-by: Marek Vasut <marex@denx.de>
There are two types of mx53loco boards: initial boards were built with a Dialog
DA9053 PMIC and more recent version is based on a Freescale MC34708 PMIC.
Add DA9053 PMIC support and adjust the required voltages and clocks for running
the CPU at 1GHz.
Tested on both versions of mx53loco boards.
In the case of a MC34708-based board the CPU operating voltage remains at 800MHz.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by : Stefano Babic <sbabic@denx.de>
Print CPU information within board_late_init().
This is in preparation for adding 1GHz support, which requires programming a PMIC
via I2C. As I2C is only available after relocation, print the CPU information
later at board_late_init(), so that the CPU frequency can be printed correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Uses the 'magic_keys' idiom as described in doc/README.kbd:
http://lists.denx.de/pipermail/u-boot/2012-April/122502.html
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
There is a 'gpio_direction_output(87, 0);' call previously, so the GPIO direction is
already established.
Use gpio_set_value() for changing the GPIO output then.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
The ESG ima3-mx53 board is based on the Freescale
i.MX53 SOC. It boots from NOR (128 MB) and
supports Ethernet (FEC), SATA.
Signed-off-by: Stefano Babic <sbabic@denx.de>
vl_bpix of vidinfo_t was changed proper value for u-boot.
It is used to multiple of 2 by using NBITS() macro.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch support TRATS board configuration and display function.
Signed-off-by: Donghwa Lee <dh09.lee@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
this patch fixed following warning.
tzpc_init.c: In function 'tzpc_init':
tzpc_init.c:35: warning: assignment from incompatible pointer type
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Chander Kashyap <chander.kashyap@linaro.org>
This patch enables LDO4 power line for preparing proper voltages to be
measured by ADC converter.
This measurement is used for determination of target board HW revision.
Test HW:
Universal_C210 (Exynos4210) rev. 0.0
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
TZPC IP is common across Exynos based SoC'c. Renaming exynos5_tzpc
in arch/arm/include/asm/arch-exynos/tzpc.h to exynos_tzpc will allow generic
usase of tzpc.
Also modify board/samsung/smdk5250/tzpc_init.c to use exynos_tzpc.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
With almost all the architecture and board BOARD_LATE_INIT does not use.
CONFIG_BOARD_LATE_INIT is used instead.
This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
CC: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Enable I2C multi-bus support and config I2C muxes for I2C2 and I2C3.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Introduce a __weak misc_init_r function that just runs dieid_num_r().
Remove misc_init_r from cm_t35, mcx, omap3_logic and mt_ventoux as this was
all they did for misc_init_r.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Ilya Yanok <yanok@emcraft.com>
Cc: Peter Barada <peter.barada@logicpd.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Update pandora's GPIO setup code with these changes:
- convert to gpiolib
- set up dual voltage GPIOs to match supply of 1.8V by clearing VMODE1
- add GPIO_IO_PWRDNZ configuration for DM3730 variation of pandora
(required to enable GPIO 126, 127, and 129 I/O cells in DM3730)
- add wifi reset pulse as recommended by wifi chip's manufacturer
- drop configuration of GPIOs that u-boot doesn't need
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
This is rework on config files of IGEP-based boards with the aim to remove
duplicated code to be more maintainable. Basically this patch creates a
common configuration file for both boards and only sets the specific option
in the board config file.
On board files the hardcored mach type was replaced in favour of using the
CONFIG_MACH_TYPE option.
More than 200 duplicated lines have been deleted.
Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
TPS SET0/SET1 register is selected by a GPIO pin on OMAP4460 platforms.
Currently we control this pin with a mux configuration as part of
boot sequence.
Current configuration results in the following voltage waveform:
|---------------| (SET1 default 1.4V)
| --------(programmed voltage)
| <- (This switch happens on mux7,pullup)
vdd_mpu(TPS) -----/ (OPP boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -----------------------/ (OPP boot voltage)
Problem 1) |<----- Tx ------>|
timing violation for a duration Tx close to few milliseconds.
Problem 2) voltage of MPU goes beyond spec for even the highest of MPU OPP.
By using GPIO as recommended as standard procedure by TI, the sequence
changes to:
-------- (programmed voltage)
vdd_mpu(TPS) ------------/ (Opp boot voltage)
--------- (programmed voltage)
vdd_core(TWL6030) -------------/ (OPP boot voltage)
NOTE: This does not attempt to address OMAP5 - Aneesh please confirm
Reported-by: Isabelle Gros <i-gros@ti.com>
Reported-by: Jerome Angeloni <j-angeloni@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add parameters to the OMAP MMC initialization function so the board can
mask host capabilities and set the maximum clock frequency. While the
OMAP supports a certain set of MMC host capabilities, individual boards
may be more restricted and the OMAP may need to be configured to match
the board. The PRG_SDMMC1_SPEEDCTRL bit in the OMAP3 is an example.
Signed-off-by: Jonathan Solnit <jsolnit@gmail.com>
This change adds a basic support for Embest/Timll DevKit3250 board,
NOR and UART are the only supported peripherals for a moment. The board
doesn't require low-level init, because the initial SDRAM and GPIO
configuration is performed during kickstart bootloader execution.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
* 'agust@denx.de' of git://git.denx.de/u-boot-staging:
lin_gadget: use common linux/compat.h
linux/compat.h: rename from linux/mtd/compat.h
lin_gadget: use common mdelay
gunzip: rename z{alloc, free} to gz{alloc, free}
fs/fat: align disk buffers on cache line to enable DMA and cache
part_dos: align disk buffers on cache line to enable DMA and cache
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/85xx: don't touch MAS7 on e500v1 when relocating CCSR
powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
cmd_bdinfo: display the address map size (32-bit vs. 36-bit)
PowerPC: correct the SATA for p1/p2 rdb-pc platform
powerpc/corenet_ds: Slave core in holdoff when boot from SRIO
powerpc/corenet_ds: Slave reads ENV from master when boot from SRIO
powerpc/corenet_ds: Slave uploads ucode when boot from SRIO
powerpc/corenet_ds: Slave module for boot from SRIO
powerpc/corenet_ds: Master module for boot from SRIO
powerpc/corenet_ds: Document for the boot from SRIO
powerpc/corenet_ds: Correct the compilation errors about ENV
powerpc/srio: Rewrite the struct ccsr_rio
powerpc/85xx:Fix lds for nand boot debug info
powerpc/p2041rdb: add env in NAND support
powerpc/p2041rdb: add NAND and NAND boot support
powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
powerpc/85xx:Avoid vector table compilation for nand_spl
powerpc/85xx:Fix IVORs addr after vector table relocation
powerpc/85xx:Avoid hardcoded vector address for IVORs
powerpc/p1023rds: Disable nor flash node and enable nand flash node
In hardware revision 1.20 one more fan controller is added to dlvision-10g.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Print fpga info at last_stage_init on gdsys 405ep boards.
Use dtt_init() to startup fans.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
In order to add boards that have different hardware for fpga reset,
any 405ep gdsys board now provides these functions:
void gd405ep_init(void);
void gd405ep_set_fpga_reset(unsigned state);
void gd405ep_setup_hw(void);
int gd405ep_get_fpga_done(unsigned fpga);
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes
displays which of these is actually built, but it's inconsistent. This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used. Not only that, but each board includes code that displays
the message, so there is duplication.
The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time. The board-specific code is
deleted.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When boot from SRIO, slave's ucode can be stored in master's memory space,
then slave can fetch the ucode image through SRIO interface. For the
corenet platform, ucode is for Fman.
Master needs to:
1. Put the slave's ucode image into it's own memory space.
2. Set an inbound SRIO window covered slave's ucode stored in master's
memory space.
Slave needs to:
1. Set a specific TLB entry in order to fetch ucode from master.
2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
In the p1023rds, when system boots from nor flash, kernel only accesses nor
flash and can not access nand flash with BR0/OR0; when system boots from
nand flash, kernel only accesses nand flash and can not access nor flash
with BR0/OR0.
Default device tree nor and nand node should have the following structure:
Example:
nor_flash: nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x02000000>;
bank-width = <2>;
device-width = <1>;
status = "okay";
partition@0 {
label = "ramdisk";
reg = <0x00000000 0x01c00000>;
};
}
nand_flash: nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1023-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x00040000>;
status = "disabled";
u-boot-nand@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
read-only;
};
}
When booting from nor flash, the status of nor node is enabled and the
status of nand node is disabled in the default dts file, so do not do
anything.
But, when booting from nand flash, need to do some operations:
o Disable the NOR node by setting status = "disabled";
o Enable the NAND node by setting status = "okay";
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
* 'master' of git://git.denx.de/u-boot-sh:
sh: ecovec: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
sh: Fix rsk7264 pin setup for on-board ethernet
This sets up the external ethernet IRQ pin.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Do the same AXI cache and Qos settings done already in the
SabreLite imximage.cfg for the ARM2 board, too.
It fixes a display flash issue caused by low priority of
the display IDMA channel.
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Chen <b02280@freescale.com>
CC: Jason Liu <r64343@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <festevam@gmail.com>
Acked-by: Jason Liu <r64343@freescale.com>
The board revision is detected accessing to the pmic,
that is not available before relocation (I2C).
This generates the following error:
CPU: Freescale i.MX35 rev 2.0 at 532 MHz.
Reset cause: WDOG
<reg num> = 7 is invalid. Should be less than 0
Board: MX35 PDK 1.0
The revision number is wrong, as a default value is printed
(tested on a mx35pdk Rev. 2.0).
Move the output in the board_late_init(), when
pmic can be accessed.
Signed-off-by: Stefano Babic <sbabic@denx.de>
enable_caches() is implemented now in cpu.c for
ARM1136.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
The reset_net_chip() function has wrong timings for the reset pulse.
This appeared to work until:
0607e2b (ARMV7: OMAP: Write more than 1 byte at a time in i2c_write)
Fix the Ethernet support by introducing right timings.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Remove userbutton command and do the detection in board config file using the gpio command
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
* 'master' of git://git.denx.de/u-boot-net:
net/designware: Change timeout loop implementation
net/designware: Set ANAR to 0x1e1
net/designware: Program phy registers when auto-negotiation is ON
net/designware: Try configuring phy on each dw_eth_init
net/designware: Consecutive writes must have delay
net/designware: Phy address fix
net/designware: Fix the max frame length size
net/designware: Fix to restore hw mac address
microblaze: Wire up LL_TEMAC driver initialization
microblaze: Add faked LL_TEMAC driver configuration
microblaze: Enable several ethernet driver compilation
net: ll_temac: Add LL TEMAC driver to u-boot
Update net subsystem maintainer in doc/git-mailrc
net/eth.c: fix eth_write_hwaddr() to use dev->enetaddr as fall back
mvgbe: remove warning for unused methods
* 'master' of git://git.denx.de/u-boot-onenand:
onenand: samsung: Enable OneNAND support at Samsung's Exynos4210
onenand: Replace ONENAND_IS_MLC() with ONENAND_HAS_4KB()
onenand:samsung OneNAND chip probe functions added for GONI and Exynos4210
onenand:samsung Target dependent OneNAND chip probe function
