Commit graph

74 commits

Author SHA1 Message Date
Simon Glass
d96c26040e common: Move clock functions into a new file
These three clock functions don't use driver model and should be migrated.
In the meantime, create a new file to hold them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 13:27:29 -05:00
Yangbo Lu
c2a8b4f879 powerpc/mpc85xx: drop eSDHC periperhal clock code
The below patch added eSDHC periperhal clock code initially.
2d9ca2c mmc: fsl_esdhc: Add peripheral clock support

The purpose was to fix up device tree properties "peripheral-frequency"
so that linux could get the periperhal clock by it.
However the implementation on both u-boot and linux was only
for a Freescale SDK release. The linux part implementation had never
been upstreamed. These code should not have been exist on u-boot
mainline.

Let's remove the powerpc part changes but keep the changes in
fsl_esdhc driver. The changes in fsl_esdhc driver could be utilized
to support SD UHS and eMMC HS200/HS400 speed modes for current
Layerscape ARM platforms.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2020-01-16 13:16:25 +08:00
Simon Glass
b5981474f1 common: Move some CPU functions out of common.h
These functions belong in cpu_func.h since they do not use driver model.
Move them over. Don't bother adding comments since these functions should
be deleted.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:23:13 -05:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Prabhakar Kushwaha
add63f94a9 arch: powerpc: update the eLBC IP input clock
eLBC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock ratio register (LCRR) used in
current implementation governs eLBC IP output cloc.

Update sys_info->freq_localbus to represent eLBC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-03 14:31:45 -08:00
Prabhakar Kushwaha
1c40707e3f arch: powerpc: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.

Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-02-03 14:31:11 -08:00
York Sun
cdb72c5212 powerpc: T4080: Drop configuration for T4080
There is no T4080 target. Drop related macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:16 -08:00
York Sun
26bc57da0a powerpc: T4240: Remove macro CONFIG_PPC_T4240
Use CONFIG_ARCH_T4240 from Kconfig instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
652a7bbd87 powerpc: T4160: Remove macro CONFIG_PPC_T4160
Use CONFIG_ARCH_T4160 instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
0f3d80e993 powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081
Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:15 -08:00
York Sun
e5d5f5a8be powerpc: T1024: Remove macro CONFIG_PPC_T1024
Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:13 -08:00
York Sun
5ff3f41d04 powerpc: T1023: Remove macro CONFIG_PPC_T1023
Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
b41f192b67 powerpc: B4420: Remove macro CONFIG_PPC_B4420
Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up
existing macros.
2016-11-23 23:42:12 -08:00
York Sun
3006ebc37e powerpc: B4860: Remove macro CONFIG_PPC_B4860
Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:12 -08:00
York Sun
4167a67d5d powerpc: P1025: Remove macro CONFIG_P1025
Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:10 -08:00
York Sun
a990799d52 powerpc: P1021: Remove macro CONFIG_P1021
Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:09 -08:00
York Sun
46d9fc0bb7 powerpc: P1014: Drop configuration for P1014
P1014 is a variant of P1010. There is no P1014 target configured.
Drop related macros. P1014 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:08 -08:00
York Sun
83b9bea116 powerpc: P1012: Drop configuration for P1012
P1012 is a single-core version of P1021. There is no P1012 target
configured. Drop related macros. P1012 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
feb9e25bc7 powerpc: P1022: Remove macro CONFIG_P1022
Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
7d5f9f84f1 powerpc: P1010: Remove macro CONFIG_P1010
Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:07 -08:00
York Sun
23b36a7d48 powerpc: MPC8569: Remove macro CONFIG_MPC8569
Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:06 -08:00
York Sun
99d0a3123e powerpc: MPC8560: Remove macro CONFIG_MPC8560
Replace CONFIG_MPC8560 with ARCH_MPC8560 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
3c3d8ab58d powerpc: MPC8555: Remove macro CONFIG_MPC8555
Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
3aff30825e powerpc: mpc8541: Remove macro CONFIG_MPC8541
Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:05 -08:00
York Sun
7f825218dc powerpc: mpc8540: Remove macro CONFIG_MPC8540
Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing
macros.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:04 -08:00
York Sun
25cb74b30a powerpc: MPC8544: Move CONFIG_MPC8544 to Kconfig option
Replace CONFIG_MPC8544 with ARCH_MPC8544 in Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-11-23 23:42:03 -08:00
Shengzhou Liu
96d59e9d6a mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1
T2081 rev 1.1 changes MEM_PLL_RAT in RCW which requires new parsing
for PLL ratio.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-02 08:51:50 -08:00
Yangbo Lu
2d9ca2c72c mmc: fsl_esdhc: Add peripheral clock support
The SD clock could be generated by platform clock or peripheral
clock for some platforms. This patch adds peripheral clock
support for T1024/T1040/T2080. To enable it, define
CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-05-04 09:25:39 -07:00
Jaiprakash Singh
39b0bbbb23 driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.

FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 16:46:50 -07:00
Shaveta Leekha
b8bf0adc12 powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420

It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:

U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)

CPU0:  B4860E, Version: 2.2, (0x86880022)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
       DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
       DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
       CCB:666.667 MHz,
       DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
       CPRI:600  MHz
       MAPLE:600  MHz, MAPLE-ULB:800  MHz, MAPLE-eTVPE:1000 MHz
       FMAN1: 666.667 MHz
       QMAN:  333.333 MHz

Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
    updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
        cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
    device's frequencies
(6) README added for the same

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-03-04 10:15:29 -08:00
Shengzhou Liu
f605079041 powerpc/mpc85xx: Add T1024/T1023 SoC support
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
York Sun
14109c7a6a mpc85xx/t2080: Fix parsing DDR ratio for new revision
T2080 rev 1.1 changes MEM_RAT in RCW, which requires new parsing for ratio,
the same way as T4240 rev 2.0.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-12-05 08:06:08 -08:00
Prabhakar Kushwaha
aa5a3d8d46 powerpc/mpc85xx: Use IFC accessor function
IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.

So use IFC acessor functions instead of in_be32().

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-11-14 11:12:14 -08:00
Shengzhou Liu
5122dfae5d powerpc/85xx: add T4080 SoC support
The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2014-05-13 08:26:54 -07:00
Prabhakar Kushwaha
b33bd8cd4b powerpc/mpc85xx:Update FM1 clock select and shift for B4420
B4420 is a personality of B4860.
It should have same FM1_CLK_SEK and FM1_CLK_SHIFT as B4860

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:53 -07:00
vijay rai
0c12a1592c powerpc/85xx: Enhance get_sys_info() to check clocking mode
T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode.

In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock
(100MHz) to the following PLLs:
• Platform PLL
• Core PLLs
• USB PLL
• DDR PLL, etc

The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or
DIFF_SYSCLK (differential) is selected as the clock input to the chip.

get_sys_info has been enhanced to add the diff_sysclk so that the
various drivers can be made aware of ths diff sysclk configuration and
act accordingly.

Other changes:
-single_src to ddr_refclk_sel, as it is use for checking ddr reference clock
-Removed the print of single_src from get_sys_info as this will be
-printed whenever somebody calls get_sys_info which is not appropriate.
-Add print of single_src in checkcpu as it is called only once during initialization

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:52 -07:00
York Sun
c3678b0937 powerpc/mpc85xx: Add workaround for erratum A007212
Erratum A007212 for DDR is about a runaway condition for DDR PLL
oscilliator. Please refer to erratum document for detail.
For this workaround to work, DDR PLL needs to be disabled in RCW.
However, u-boot needs to know the expected PLL ratio. We put the
ratio in a reserved field RCW[18:23]. U-boot will skip this workaround
if DDR PLL ratio is set, or the reserved field is not set.

Workaround for erratum A007212 applies to selected versions of
B4/T4 SoCs. It is safe to apply the workaround to all versions. It
is helpful for upgrading SoC without changing u-boot. In case DDR
PLL is disabled by RCW (part of the erratum workaround), we need this
u-boot workround to bring up DDR clock.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
Zhao Qiang
2a44efeb21 QE/U-QE: Add U-QE support
Modify code to adapt to both u-qe and qe.

U_QE is a kind of cutted QE.
the differences between U_QE and QE
	1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
	2. IMMR: have different immr base addr.
	3. iopin: U_QE doesn't need to config iopin.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:47 -07:00
Shengzhou Liu
35c471e509 powerpc/t208x: some update to support t2081
- fix serdes definition for t2081.
- fix clock speed for t2081.
- update ids, as CONFIG_FSL_SATA_V2 is needed only for t2080,
  T2081 has no SATA.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-02-24 15:22:36 -08:00
Priyanka Jain
b135991a3c powerpc/mpc85xx: Add support for single source clocking
Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.

So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock

DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
 normal clocking mode by DDR_Reference clock

-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
 single source clocking mode by DIFF_SYSCLK

Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2014-01-02 14:10:13 -08:00
Shaohui Xie
c1015c67f4 powerpc/t4240: Add a frequency setting case for fman1
A new valid setting case added for fman1, it uses platform frequency.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-11 11:12:04 -08:00
Zang Roy-R61911
e88f421e7a T4240: Address T4240/T4160 Rev2.0 DDR clock change
MEM_PLL_RAT on T4240/T4160 Rev2.0 uses a value which is half of Rev1.0.
It's 12 in Rev1.0, for Rev2.0 it uses 6.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-12-04 14:54:42 -08:00
Shengzhou Liu
629d6b32d6 powerpc/mpc85xx: Add T2080/T2081 SoC support
Add support for Freescale T2080/T2081 SoC.

T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
  - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
  - Two serial ATA (SATA 2.0) controllers
  - Two high-speed USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T2080 and T2081:
  Feature               T2080 T2081
  1G Ethernet numbers:  8     6
  10G Ethernet numbers: 4     2
  SerDes lanes:         16    8
  Serial RapidIO,RMan:  2     no
  SATA Controller:      2     no
  Aurora:               yes   no
  SoC Package:          896-pins 780-pins

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-11-25 11:44:25 -08:00
Prabhakar Kushwaha
ce746fe03e powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator
CHASSIS2 architecture never fix clock groups for Cluster and hardware
  accelerator like PME, FMA. These are SoC defined. SoC defines :-
    - NUM of PLLs present in the system
    - Clusters and their Clock group
    - hardware accelerator and their clock group
      if no clock group, then platform clock divider for FMAN, PME

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16 16:13:11 -07:00
Tang Yuantian
f62b123813 powerpc/mpc85xx: Fix the I2C bus speed error on p1022
The source clock frequency of I2C bus on p1022 is the platform(CCB)
clock, not CCB/2. The wrong source clock frequency leads to wrong
I2C bus speed setting. so, fixed it.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
2013-09-09 07:44:27 +02:00
Prabhakar Kushwaha
997399fa42 powerpc: Fix CamelCase checkpatch warnings
85xx, 86xx PowerPC folders have code variables with CamelCase naming conventions.
because of this code checkpatch script generates "WARNING: Avoid CamelCase".

Convert variables name to normal naming convention and modify board, driver
files with updated the new structure.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
2013-08-20 09:57:51 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
York Sun
f69814397e powerpc/chassis2: Change core numbering scheme
To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:11 -05:00
Shaohui Xie
3e83fc9b4d powerpc/85xx: add missing QMAN frequency calculation
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:13:24 -05:00
Sandeep Singh
0cb3325cd3 powerpc/B4860: Corrected FMAN1 operating frequency print at u-boot
The bit positions for FMAN1 freq in RCW is different for B4860.
Also addded a case when FMAN1 frewuency is equal to systembus.

Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-14 16:00:24 -05:00