This adds the required GPIO and pinmux configuration to make eMMC / SD work
on Seaboard.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This adds support for changing pinmux functions of pin groups. This is done
by defining a PMUX_FUNC_... enum which can be used to select the function for
each group using pinmux_set_func(). It is also possible to enable
pullup/pulldown, and the existing tristate functionality is retained.
Also provided is a means of configuring a list of pingroups by providing a
configuration table to pinmux_config_table().
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
The pin groupings are better named PINGRP, since on Tegra2 they refer to
multiple pins.
Sorry about this, but better to get it right now when there is only a small
amount of code affected.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This adds most of the clock functions required by board and driver code:
-query and adjust peripheral clocks
-query and adjust PLLs
-reset and enable control
These functions are plumbed in as required.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This removes clock_init() and pinmux_init() which are names better suited
to those respective modules. By moving board_init_f() to the bottom of the
file we can remove the need for so many functions in the board.h header file.
The only clock/pinmux/gpio init we need to do prior to relocation is
for the UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
Rename CLOCK_PLL_ID to CLOCK_ID which takes account of the fact that the
code now deals with both PLL clocks and source clocks.
This also tidied up the assert() to match the one sent upstream, and fixes
an error in the PWM id.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This is a better name for this protocol. Also remove the typedef to keep
checkpatch happy, and move zeroing of NetBootFileXferSize a little
earlier since TFTPPUT will need to change this.
Signed-off-by: Simon Glass <sjg@chromium.org>
This reverts commit a2da616311.
THis was applied by accident - a more recent version of this change
was already present, see commit
9400f8f 2011-10-05 22:03:11 +0200 km_arm: enable POST for these boards
Signed-off-by: Wolfgang Denk <wd@denx.de>
This driver doesn't support the NET_MULTI framework, and I can't find
any boards/configs/files that reference this subdir, so punt it all.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The board stopped building some time ago, and the board maintainer
agrtees to drop it - see
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112674
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Alex Dubov <oakad@yahoo.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Seems people fixed their files to use libfoo.o, but didn't actually
update the creation targets to use $(cmd_link_o_target). Update the
rest of the Makefile's found with grep.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Tested-by: Simon Glass <sjg@chromium.org>
There are several mdelay() definitions in the driver and
board code. Remove them all and provide a common mdelay()
in lib/time.c.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
This header is unneeded due to code which was removed in the
past.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
Calucations of PRAM needs to take into account the 'rootfssize'.
Memory available to the linux kernel 'mem=' is in all cases set to the total
memory size minus the pram size.
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
This prevents u-boot to print out "Can't overwrite "ethaddr""
each time a powerpc board starts.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
The current km_arm boards have a Power-On test jumper. When this
jumper is set, this triggers some Power-On tests on the board.
This patch enables the support of this jumper for starting the
memory_regions test when the jumper is set.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
mpc85xx: Add inline GPIO acessor functions
powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
powerpc/85xx: Fix P2020DS booting
powerpc/85xx: Update USB device tree status based on pin settings
fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers
powerpc/85xx: Add support for RMan LIODN initialization
powerpc/85xx: Update device tree handling for SRIO
powerpc/85xx: Update setting of SRIO LIODNs
fm: Don't allow disabling of FM1-DTSEC1
fm-eth: Don't mark the MAC we use for MDIO as disabled in device tree
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
A temp variable was used but not declared, with CONFIG_SYS_DRAMSZ1
defined. This variable is now declared in the functione when needed.
Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
The spa, stm, int, 32 and 16 linking files are identical so there is
no need to differentiate them. A single lds file is now used, and
_config rule are simplified.
Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
Lds files cleened to remove multiple defined section and modified to
be compliant with --gc-sections added for ColdFire platform in a
previous patch.
Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
The following commit removed the code that set odt_rd_cfg and
odt_wr_cfg. With out this code P2020DS board will not boot:
commit 712cf7ab0b
Author: York Sun <yorksun@freescale.com>
Date: Mon Oct 3 09:19:53 2011 -0700
powerpc/mpc8xxx: Merge entries in DDR speed table
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add common function fdt_set_node_status() to assist in various locations
that we set a nodes status. This function utilizes the status values
that are part of the EPAPR spec (on power.org).
fdt_set_status_by_alias() is based on fdt_set_node_status() but uses an
alias string to identify the node to update.
We also add some shortcut functions to help the common cases of setting
"okay" and "disabled":
fdt_status_okay()
fdt_status_disabled()
fdt_status_okay_by_alias()
fdt_status_disabled_by_alias()
Finally, we fixup the corenet_ds ethernet code which previously had
a function by the same name that can be replaced with the new helpers.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
This adds basic files for the sandbox board. The lds file is very simple
since we can rely mostly on the linker defaults.
Signed-off-by: Simon Glass <sjg@chromium.org>
The framebuffer driver for MX5 is based on CONFIG_LCD.
In the current implementation, there is a serious bug
because the required memory is allocated before
relocation, but the driver knows only later which is
the resolution of the display. The patch switches the driver
to CONFIG_VIDEO and the memory is allocated by the driver itself.
We also need to switch the vision2 board code and config file
in the same commit so that this commit will be bisectable.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used. Punt them all.
MAKEALL didn't report any errors related to this that I could see.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
- Rework tlb and law tables.
- PCI2 is not available on MPC8548CDS, so remove it.
- Move the memory map to the board config file.
- Rewrite the board info according to the manual.
- Remove unnecessary macros and redefine some macros to align with other boards.
- Fix some typos.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device
from Qi hardware:
http://en.qi-hardware.com/wiki/Ben_NanoNotehttp://en.qi-hardware.com/wiki/Main_Pagehttp://en.wikipedia.org/wiki/Qi_hardware
This Jz4740-based clamshell device does not use NOR flash to boot.
The initial bring-up assumes that U-Boot is directly loaded into SDRAM
using USB boot tool, and starts from 0x80100000.
About USB boot tool
-------------------
Jz4740 is one of the XBurst processors with USB boot functionality
supported. The CPU can boot from a small ROM in the LSI, initialize
CPU and USB module, then wait for USB commands from the USB host.
We can send 8 KB binary data to the CPU cache using USB boot tool.
USB boot tool is available to the public at Ingenic website. Also
there is an alternative Debian package named xburst-tools.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum, so that the SDHC write
protected pin polarity does not follow the SD card standard in MPC8536
Rev 1.0 silicon.
The MPC8536DS board invert the SDHC_WP pin as a workaround. However, this
silicon erratum has been fixed in Rev 1.1, So need invert the SDHC_WP
polarity again when use the MPC8536 Rev1.1 and greater on MPC8536DS board.
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.
Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.
Removed ODT overriding for P2020DS as it is not necessary.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is long over due. All but two net drivers have been converted, but
those have now been dropped.
The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined. So here we scrub the
core code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current km_arm boards have a Power-On test jumper. When this
jumper is set, this triggers some Power-On tests on the board.
This patch enables the support of this jumper for starting the
memory_regions test when the jumper is set.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Commit "PPC: Cleanup tqm8xx_pcmcia.c" will clean up the PCMCIA code
to use I/O accessors instead of plain volatile pointer accesses.
This will result in about 300 byte bigger code. Fix custom linker
script to make room for this.
While we are at it, drop unmaintained u-boot.lds.debug linker script.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Wolfgang Denk <wd@denx.de>
* 'master' of git://git.denx.de/u-boot-nand-flash:
PPC: Fix socrates NAND problem
PPC: Fix fsl_upm.c by renaming nand handling functions
NAND: Make page, erase, oob size available via cmd_nand
mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poi
NAND: Add -y option to nand scrub command
NAND: Add nand read.raw and write.raw commands
NAND: Really ignore bad blocks when scrubbing
spl, nand: add 4bit HW ecc oob first nand_read_page function
mxc_nand: fix a problem writing more than 32MB
mxc_nand: fixed some typos (cosmetic)
nand: increase chip_delay in mv kirkwood nand driver
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p3060: Add SoC related support for P3060 platform
powerpc/85xx: Add support for setting up RAID engine liodns on P5020
powerpc/85xx: Refactor some defines out of corenet_ds.h
fm-eth: Add ability for board code to disable a port
powerpc/mpc8548: Add workaround for erratum NMG_LBC103
powerpc/mpc8548: Add workaround for erratum NMG_DDR120
powerpc/mpc85xxcds: Fix PCI speed
powerpc/mpc8548cds: Fix booting message
powerpc/p4080: Add support for secure boot flow
powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
powerpc/p2041rdb: remove watch dog related codes
powerpc/p2041rdb: updated description of cpld command
powerpc/p2041rdb: add more ddr frequencies support
powerpc/p2041rdb: set sysclk according to status of physical switch SW1
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
powerpc/mpc8xxx: Add DDR2 to unified DDR driver
powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
powerpc/85xx: Refactor P2041RDB to use common p_corenet files
powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
powerpc/85xx: Enable CMD_REGINFO on corenet boards
powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
powerpc/85xx: Fix USB protocol definitions for P1020RDB
powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
powerpc/mpc8xxx: Move DDR RCW overriding to common code
powerpc/mpc8xxx: Extend CWL table
powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
powerpc/85xx: Cleanup extern in corenet_ds board code
powerpc/p2041rdb: Add ethernet support on P2041RDB board
powerpc/85xx: Add networking support to P1023RDS
powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
powerpc/85xx: Add FMan ethernet support to P4080DS
powerpc/85xx: Add support for FMan ethernet in Independent mode
powerpc/mpc8548cds: Cleanup mpc8548cds.c
powerpc/mp: add support for discontiguous cores
powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
fdt: Add new fdt_create_phandle helper
fdt: Rename fdt_create_phandle to fdt_set_phandle
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
nand: Freescale Integrated Flash Controller NAND support
powerpc/85xx: Add basic support for P1010RDB
powerpc/85xx: Add support for new P102x/P2020 RDB style boards
powerpc/85xx: relocate CCSR before creating the initial RAM area
powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
nand.c:36: error: static declaration of 'nand_read_buf' follows non-static declaration
/home/marex/u-boot/include/nand.h:139: error: previous declaration of 'nand_read_buf' was here
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz.
Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CPLD 2.2 removed board watch dog support due to the limitation of CPLD
capacity after adding all the requested features, such as switch overriding.
There is no pin-compatible upgrade part available for current PCB design.
So remove codes related to it.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
According to CPLD 2.2, the default configuration is changed, so updated the
description of CPLD command, otherwise it will confusing.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This table covers DDR frequencies from 666 to 1666. Frequencies 666, 833,
1000, 1066 and 1333 were verified on this board with SO-DIMM
(UG51U6400N8SU-ACF).
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CPLD 2.0 provides a new register which bit[0] is set to '1' will reset
board with initializing the CPLD registers to default values. And add
bit[6] of register at offset 0x5 to use to enable flash bank selection.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The EST SBC8260 is over 10 years old, and the SBC8240 older than
that. With the tiny amount of RAM (by today's standards), there
really isn't anyone interested in running the latest U-boot on
these EOL products anymore.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: jon.diekema@smiths-aerospace.com
* 'post' of git://git.denx.de/u-boot-blackfin:
Blackfin: uart: implement loop callback for post
Blackfin: bf537-stamp/bf548-ezkit: update POST flash block range
Blackfin: post: generalize led/button tests with GPIOs
Blackfin: bf537-stamp: drop uart/flash post tests
Blackfin: post: drop custom test list
Blackfin: bf537-stamp: convert to gpio post hotkey
Let common code set the machine ID.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
As only one RAM bank is used we can rely on the code from arch/arm/lib/board.c
Cc: Matthias Weisser <weisserm@arcor.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Let common code set the machine ID.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Add NAND SPL support to the devkit8000 config
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Without this change CS's configured for synchronous clocking cannot
read data.
Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The existing timing does not quite meet the minimum requirements
in the LAN9221 datasheet. The timing in this patch solves problems
noticed on some parts. The patch also combines the CS configuration
for the overo and igep0020 boards per request.
Signed-off-by: Philip Balister <philip@opensdr.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c.
The unified driver can initialize data using DDR controller. No need to
use DMA if just to initialze for ECC.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P2041RDB has almost identical setup for TLB, LAWS, and PCI with
other P-Series CoreNet platforms.
The only difference between P2041RDB & P3041DS/P4080DS/P5020DS is the
CPLD vs PIXIS FPGA which we can handle via some simple #ifdefs in the
TLB and LAW setup tables.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that
are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and
P5020DS. There is a significant amount of commonality shared between
these boards that we can refactor into common code:
* Initial LAW setup
* Initial TLB setup
* PCI setup
We start by moving the shared code between P3041DS, P4080DS, and P5020DS
into a common directory to be shared with other P-Series CoreNet boards.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
RDIMM has different timing parameters from UDIMM. Create new tables for
RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds
from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future
use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for
future use.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII and XAUI Ethernet on P2041RDB board.
The five dTSEC can be routed to two on-board RGMII phy, three on-board
SGMII phy or four SGMII phy on SGMII riser card according to different
serdes protocol configuration and board lane configuration. Also updated
the device tree to direct the Fmac MAC to the correct PHY.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P1023 has two 1G ethernet controllers the first can run in
SGMII, RGMII, or RMII. The second can only do SGMII & RGMII.
We need to setup a for SoC & board registers based on our various
configuration for ethernet to function properly on the board.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Lei Xu <B33228@freescale.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS &
P5020DS ("Hydra").
The lane_to_slot[] array is initialized dynamically, since board switches
can be used to control the muxing of SERDES lanes to slots.
The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate
slot. The SERDES configuration is queried to help determine the routing
between MACs and slot/phy combination.
If a XAUI card is inserted, muxing for that card is enabled and never
turned off. The PHY address for the 10G XAUI card depends on the slot in
which it's inserted. If it's in slot 1, the address is 4. If it's in
slot 2, the address is 0.
Update the MDIO routing in the P3041DS and P5020DS device trees based on
the board-level muxing. The SERDES configuration determines which
SGMII/XGMII boards are located in which slots, and so the MDIO bus needs
to be muxed correctly whenever talking to a PHY connected to any Fman MAC.
The Fman Ethernet nodes in the device tree also need to be routed to the
correct PHYs.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS.
The board supports add-on cards for SGMII and XAUI functionality. Which
slots on the board these cards are in is a function of the SERDES option
selected and muxes on the board.
Additionally because of the high-configurablity which MDIO bus one is
connected to is "selected" via an FPGA register. We create dummy MDIO
bus for the phy layer and hide the mux manipulation in this dummy layer.
Add fman fdt helper function in board common code it'll be used by several
freescale boards that do various muxing of the MDIO signals based on which
controller/interface one is trying to talk to.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove unnecessary or dead code/includes.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Boot methods supported: NOR Flash, SPI Flash and SDCARD
This patch adds the following basic interfaces:
DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash.
P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
Local Bus (IFC):
32Mbyte 16bit NOR flash
32Mbyte SLC NAND Flash
64KB CPLD device(GPCM interface)
SPI Flash:
128 Mbit SPI Flash memory
SD/MMC:
connector to interface with the SD memory card
SATA:
1 internal SATA connect to 2.5. 160G SATA2 HDD
1 eSATA connector to rear panel
USB 2.0:
x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC:
eTSEC1: Connected to RGMII PHY VSC8641XKO
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY VSC8221
eCAN:
Two DB-9 female connectors for Field bus interface
UART:
supports two UARTs up to 115200 bps for console
TDM:
2 FXS ports connected via an external SLIC to the TDM interface.
SLIC:
SPI SLIC
I2C:
Serial EEprom
Real time clock
256 Kbit M24256 I2C EEPROM
PCIe:
PCIe and mPCIe connectors.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The following boards share a common design but with minor variations
between them:
P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC
The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.
Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots
As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.
VSC firmware Address is defined by default in config file for eTSEC1.
SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.
Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
Since commit d388298a59 by
Stefano Babic this file is no longer needed so delete it.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Loïc Minier <loic.minier@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The MAC address stored in the inventory eeprom begins at offset 1.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
Result of running the following command to address Wolfgang's
comment about camel case:
for file in `find . | grep '\.[chS]$'`; do perl -i -pe
's/(green|yellow|red|blue)_LED_(on|off)/$1_led_$2/g' $file; done
Discussion:
http://patchwork.ozlabs.org/patch/84988/
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
omap4: fix pad configuration settings for SDP and Panda
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: David Anders <x0132446@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Make use of GPIO framework and avoid the following build error:
tx25.c: In function 'tx25_fec_init':
tx25.c:73: error: dereferencing pointer to incomplete type
tx25.c:74: error: dereferencing pointer to incomplete type
tx25.c:75: error: dereferencing pointer to incomplete type
tx25.c:76: error: dereferencing pointer to incomplete type
tx25.c:83: error: dereferencing pointer to incomplete type
tx25.c:84: error: dereferencing pointer to incomplete type
tx25.c:114: error: dereferencing pointer to incomplete type
tx25.c:115: error: dereferencing pointer to incomplete type
tx25.c:116: error: dereferencing pointer to incomplete type
tx25.c:117: error: dereferencing pointer to incomplete type
tx25.c:124: error: dereferencing pointer to incomplete type
tx25.c:125: error: dereferencing pointer to incomplete type
tx25.c:126: error: dereferencing pointer to incomplete type
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Fix build problem:
nand_spl/board/davinci/da8xxevm/hawkboard_nand_spl.c: In function 'board_init_f':
nand_spl/board/davinci/da8xxevm/hawkboard_nand_spl.c:132: warning: implicit declaration of function 'nand_boot'
nand_spl/board/davinci/da8xxevm/hawkboard_nand_spl.c:133: warning: 'noreturn' function does return
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Syed Mohammed Khasim <sm.khasim@gmail.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Fix these:
cm4008.c: In function 'board_eth_init':
cm4008.c:79: warning: implicit declaration of function 'ks8695_eth_initialize'
cm41xx.c: In function 'board_eth_init':
cm41xx.c:79: warning: implicit declaration of function 'ks8695_eth_initialize'
While we are at it, sort include list in netdev.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Greg Ungerer <greg.ungerer@opengear.com>
The pointer to the flash based bootargs should be a "char *", not unsigned.
Fixes:
cm41xx.c: In function ‘env_flash_cmdline’:
cm41xx.c:67: warning: pointer targets in passing argument 2 of ‘setenv’ differ in signedness
Signed-off-by: Greg Ungerer <greg.ungerer@opengear.com>
The pointer to the flash based bootargs should be a "char *", not unsigned.
Fixes:
cm4008.c: In function ‘env_flash_cmdline’:
cm4008.c:67: warning: pointer targets in passing argument 2 of ‘setenv’ differ in signedness
Signed-off-by: Greg Ungerer <greg.ungerer@opengear.com>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/mpc8610hpcd: set pci1_hose.config_table after fsl_setup_hose
powerpc/mpc8548cds: set pci1_hose.config_table after fsl_setup_hose
powerpc/mpc8568mds: set pci1_hose.config_table after fsl_setup_hose
Use _bss_start_ofs as the size of the boot loader code+data that we want
to protect in the flash. This replaces use of the no longer defined
_armboot_start.
Fixes:
flash.c: In function ‘flash_init’:
flash.c:75: error: ‘_bss_start’ undeclared (first use in this function)
flash.c:75: error: (Each undeclared identifier is reported only once
flash.c:75: error: for each function it appears in.)
flash.c:75: error: ‘_armboot_start’ undeclared (first use in this function)
Signed-off-by: <greg.ungerer@opengear.com>
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The function fsl_setup_hose clears the variable pci1_hose.
Set pci1_hose.config_table after it.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The out-of-tree build fails because the Makefiles in question depend on
source files of another directory but do not explicitly mkdir that
directory.
As a matter of fact, other Makefiles under board/*/ directory that refer
to source files under another directory explicitly call mkdir.
This patch adds explicit mkdir's to the Makefiles in question, and
verifies that out-of-tree build is working.
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
The ALPR custom FPGA code was missed by commit e6a857d "fpga:
constify to fix build warning" resulting in such warnings:
fpga.c:226: warning: initialization from incompatible pointer type
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Commit 58c583b "net: Check network device driver name" increased the
code size and broke building for the ETX094 board.
Adjust the linker script to make it build again.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Commit 09c2e90 "unify version_string" defines a default value for
CONFIG_IDENT_STRING in version.h, so any private settings musty be
done before including this file. Move the include for version.h after
the one for common.h to fix the build problem.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
* 'master' of git://git.denx.de/u-boot-coldfire:
ColdFire:Clean up the CONFIG_STANDALONE_LOAD_ADDR usage
ColdFire:Add mb for 5253 dram initialization
ColdFire:Define the DM9000 byteswap for M5253 board.
ColdFire:Update the env settings for several boards.
ColdFire:disable the NFS define for 52277 board.
ColdFire:Update the timer_init since it was unified.
ColdFire: Cleanup for partial linking and --gc-sections
ColdFire: Update compile flags for each CPUs
ColdFire:Fix the configuration broken for some boards.
The dram initialization sequence should be in order.
This patch add mb for the dram intialization code to make
sure the compiler do not disorder the code.
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Introduce the --gc-sections for ColdFire platform and clean up the
corresponding lds file.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Read the led output state from GPIO instead saving state in memory when it is [re]set
* Added a toggle option to the led command
Previous discussion:
http://lists.denx.de/pipermail/u-boot/2011-May/093068.html
Changes since v1:
Fixed checkpatch errors
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Fixed USR0/USR1 to be LED 0/1 respectively
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Based on patches from Syed Mohammed Khasim (khasim@ti.com).
Configures the output of the BeagleBoard DVI to be orange.
Configures the output of the BeagleBoard S-Video to be a colorbar.
Changed display_init to beagle_display_init as suggested by Igor Grinberg:
http://www.mail-archive.com/u-boot@lists.denx.de/msg51446.html
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Based on commit f1099c7c43caf5bac3bf6a65aa266fade4747072
Author: Greg Turner <gregturner@ti.com>
Date: Tue May 25 09:19:06 2010 -0500
New u-boot command for status of USER button on BeagleBoard-xM
Modified bootcmd to check the staus at boot time and set
filename of the boot script.
* Moved to a BeagleBoard specific file.
* Removed changes to default boot command from adding userbutton
command.
* Made to handle pre-xM boards.
* Flipped polarity of the return value to avoid confusion. Success (0)
is when the button is pressed. Failure (1) is when the button is NOT
pressed.
* Used latest revision getting function.
* Used latest macros for board revision.
* Added xM-C revision definition (optional, since it was default)
* updated default configuration with UserButton functionality
* Added a separate bootenv variable to load a user defined .txt file
* Added an example, showing how a different environment file can be loaded with
the user button pressed
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Cc: Greg Turner <gregturner@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This fixes display problems in linux
Signed-off-by: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: Joel A Fernandes <agnel.joel@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The below patch reverses the order of two segments in the board file.
Output pins need to have their values initialized, before they are
exposed to the logic outside the chip.
Signed-off-by: Bob Feretich <bob.feretich@rafresearch.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
add support for DSP wake-up by default on DA850/OMAP-L138
during board initialization. Enable hwconfig environment and added
extra env setting through CONFIG_EXTRA_ENV_SETTINGS.
To prevent DSP from being woken up,set the environment variable as,
set hwconfig "dsp:wake=no"
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Add pin-mux support for NOR in board file and correspanding
macros to use NOR boot mode in configuration file.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy omap3 mmc driver to the new generic omap hsmmc
driver. This patch is based on the work done for Beagle, etc.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy mmc driver to the
new generic mmc driver.
This patch is based on similar patch for beagle[1].
[1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Switch from the legacy mmc driver to the
new generic mmc driver.
This patch is based on similar patch for beagle[1].
[1] http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=0cd31144240
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Origen board is based upon S5PV310 SoC which is similiar to
S5PC210 SoC.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This changes write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This is a cosmetic patch, which is changing the gpio_ prefix to
s5p_gpio_.
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This change is driven by need of general gpio_* functions,
which as their parameter are accepting the GPIO pin number, NOT
block and pin.
This makes the code alike to omap, and allows for using more
generic frameworks (e.g. software I2C).
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
This deletes the integrator split_by_variant.sh script and
defines a number of unique board types for the core modules
that are meaningful to support for the Integrator AP/CP, i.e.
the ones that did not just say "unsupported core module" in
split_by_variant.sh. If more core modules need to be supported
they are easy to add.
We delete all the old cruft in Makefile and MAKEALL that was
working around the old way of building boards. We create a
unique config file per board to satisfy the build system, but
they are just oneliners that include the existing
integratorap.h and integratorcp.h configs.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The integrator board was apparently never converted over to support
relocation until now. After this the integrator u-boot both compiles
and boots on the Integrator AP.
This also fixes the SDRAM memory size detection.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The integratorap/cp config for u-boot was outdated and would not
even compile, so fix the obvious missing bits for it to start
building. After this "make ap920t_config/make all" starts working
again.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Innovator and H2 boards used machine_is_* macros for setting the machine
type. These macros are expanded in compile time and thus leaves
unreachable code (though gcc might optimize it).
Switch them to use common code for machine type setting.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
