Commit graph

16082 commits

Author SHA1 Message Date
Keerthy
9a03e50c5f misc: k3_avs: Add j721e support
j721e SoCs have different OPP tables. Add support for the same.

Note: DM Still has lot of voltages TBD hence the correct
values need to be programmed once they are published.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Tero Kristo
22e8f18980 power: regulator: tps6236x: add support for tps6236x regulators
TPS6236x is a family of step down DC-DC converters optimized for battery
powered portable applications for a small solution size. Add a regulator
driver for supporting these devices.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Keerthy
e0aa873bc7 clk: clk-ti-sci: Notify AVS driver upon setting clock rate
Notify AVS driver upon setting clock rate so that voltage
is changed accordingly.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
Tero Kristo
9d233b4e3e misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0
Adaptive Voltage Scaling is a technology used in TI SoCs to optimize
the operating voltage based on characterization data written to efuse
during production. Add a driver to support this feature for K3 line of
SoCs, initially for AM65x.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:16 -05:00
liu hao
e3aafef4cf arm: add initial support for the Phytium Durian Board
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>

Signed-off-by: Steven Hao <liuhao@phytium.com.cn>
2019-11-07 18:01:13 -05:00
Tom Rini
d911087889 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- mpc85xx, socrates: Add dts, enable DM support, fix warnings, disable
  video
2019-11-07 07:25:14 -05:00
T Karthik Reddy
f69257baa8 usb: composite: add BOS descriptor support to composite framework
To add usb-3.0 support to peripheral device add BOS & SS capability
descriptors to gadget composite framework.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
d80effb184 usb: gadget: Add gadget_is_cdns3() macro
Add a new bcdDevice entry for Cadence USB gadget controller similar to
other controller and add gadget_is_cdns3() macro as well.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
a9ca4193bd usb: cdns3: Add TI wrapper driver for CDNS USB3 controller
Add driver to handle TI specific wrapper for Cadence USB3 controller
present on J721e SoC. Based on Linux driver for the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
927c22b0da usb: cdns3: gadget: Implement udc_set_speed() callback
Implement udc_set_speed() callback to limit Controller's speed to
high-speed/full-speed when working with gadgets that are high-speed or
full-speed only

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
7e91f6ccdc usb: Add Cadence USB3 host and gadget driver
Add support for USB3 host and gadget driver. This is a direct sync of
Linux kernel Cadence USB stack that from v5.4-rc1 release.
Driver has been modified so that it compiles without errors against
U-Boot code base.
Features not required for U-Boot such as scatter-gather DMA and OTG
interrupt handling has been dropped.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
[jjhiblot@ti.com: Add PHY support]
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Sherry Sun
8d94e184ff usb: udc: Introduce ->udc_set_speed() method
This patch was copied from kernel commit: 67fdfda4a99ed.

Sometimes, the gadget driver we want to run has max_speed lower than
what the UDC supports. In such situations, UDC might want to make sure
we don't try to connect on speeds not supported by the gadget
driver because that will just fail.

So here introduce a new optional ->udc_set_speed() method which can be
implemented by interested UDC drivers to achieve this purpose.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Vignesh Raghavendra
77dcbdf3c1 usb: gadget: Add match_ep() op to usb_gadget_ops
Add match_ep() op to usb_gadget_ops similar to Linux kernel which is
useful in finding a suitable ep match for the function driver. This will
avoid adding more gadget_is_xxx() handling code to usb_ep_autoconfig().

Also sync usb_ep_caps struct thats is usually used in the match_ep()
callback by the gadget controller driver

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-11-07 00:24:59 +01:00
Tom Rini
a8c1846633 Merge branch 'master' of git://git.denx.de/u-boot-usb
- DFU updates
- USB Storage updates
2019-11-06 07:11:02 -05:00
Heiko Schocher
b61cbbdcab pci: add DM based mpc85xx driver
add DM based PCI Configuration space access support for
MPC85xx PCI Bridge. This driver is based on
arch/powerpc/cpu/mpc85xx/pci.c

In the old driver there is a fix for a hw issue on the
TARGET_MPC8555CDS and TARGET_MPC8541CDS boards. As I
have no such hardware I did not port this part.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2019-11-06 16:30:19 +05:30
Peng Fan
673f659732 net: fec_mxc: support i.MX8M with CLK_CCF
Add more clks for fec_mxc according to Linux Kernel 5.4.0-rc1
drivers/net/ethernet/freescale/fec_main.c.

Since i.MX8MQ not support CLK_CCF, so add a check to restrict
the code only effect when CONFIG_IMX8M and CONFIG_CLK_CCF both defined.

Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
81dc2ac557 net: Kconfig: FEC: Add dependency on i.MX8M
Make FEC driver could be used by i.MX8M when CONFIG_FEC_MXC defined
in defconfig.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
ddf66d2159 clk: imx: imx8mm: add set_parent callback
Add set_parent callback, then assigned-clock-parents in dts could
be work.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
3bdd558737 clk: imx8mm: add enet clk
Add enet ref/timer/PHY_REF/root clk which are required to make enet
function well.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2019-11-05 10:27:18 +01:00
Peng Fan
a3aff5e5f3 clk: imx: add i.MX8MN ccf driver
Add i.MX8MM ccf driver support.
Modifed from Linux Kernel 5.3.0-rc1, drop some entries
that not used in U-Boot and adapt to U-Boot CCF style.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Lukasz Majewski <lukma@denx.de>
2019-11-05 10:27:18 +01:00
Peng Fan
b6f2945227 pinctrl: imx8m: support i.MX8MN
Support i.MX8MN in imx8m pinctrl driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
afd267af8d power: domain: add i.MX8 scu power domain driver
The power domain tree is not accepted by Linux Kernel upstream.
only a single pd node is used currently, as following:

		pd: imx8qx-pd {
			compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
			#power-domain-cells = <1>;
		};

So to migrate to use upstream linux dts, we also need a driver
to support this.

This patch is to support the new method, compared with legacy power
domain tree, it will be simpiler, because each device will
has resource id as power domain index, it will be directly passed
to scfw, and no need to let power domain build that tree. If multiple
power domain is needed, it is the dts node should has correctly power
domains entry added and sequence correct.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
954b9311ab power: domain: make imx8-power-domain.c legacy
The current i.MX8 power domain driver is based on i.MX vendor
power domain tree which will retire later.

The Linux upstream use a single pd node for power domain driver,
and U-Boot will adopt that. When U-Boot i.MX8 dts synced with
Linux Kernel upstream and related driver ready, the legacy
driver will be removed.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
816d093c1a misc: imx8: scu: simplify code to make it extendable
clk and pinctrl will be get(probed) during each device probe,
we don't need to probe them in scu driver. Only need to bind the sub-nodes
(clk and iomuxc) of MU node with their drivers.

So drop the code to probe the clk/pinctrl, and this patch will make it
easy to add more subnodes.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 10:27:18 +01:00
Peng Fan
f65d08411d mmc: fsl_esdhc_imx: Update compatible string for imx8m
To enable HS400(ES) and UHS for imx8m platforms, update the driver data
to share with imx8qm esdhc_soc_data.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 11:21:25 +08:00
Peng Fan
1d01c984b9 mmc: fsl_esdhc_imx: drop redundant clock settings
During mmc initialization, there are several calls to mmc_set_clock
and mmc_set_ios. When mmc_power_off, the mmc->clock will be set,
but the imx driver will use 400KHz. So the following calls
to mmc_set_ios will set the clock several times which is redundant
in fsl_esdhc_imx driver. So let's simplify to remove redundant
clock settings.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
618704753e mmc: fsl_esdhc: clean up DM and non-DM code
Make DM and non-DM code clear using below structure.
	#if !CONFIG_IS_ENABLED(DM_MMC)
		<non-DM_MMC code>
	#else
		<DM_MMC code>
	#endif

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
0cc127c424 mmc: fsl_esdhc: always check write protect state
The QorIQ eSDHC on all platforms supports checking write protect
state through register bit. So check it always.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
08197cb8df mmc: fsl_esdhc: drop redundant code for non-removable feature
Drop redundant code for non-removable feature. "non-removable" property
has been read in mmc_of_parse().

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
5705973b09 mmc: fsl_esdhc: convert to use fsl_esdhc_get_cfg_common()
The fsl_esdhc_init() was actually to get configuration of mmc_config.
So rename it to fsl_esdhc_get_cfg_common() and make it common for both
DM_MMC and non-DM_MMC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:25 +08:00
Yangbo Lu
07bae1de38 mmc: fsl_esdhc: clean up bus width configuration code
This patch is to clean up bus width setting code.

- For DM_MMC, remove getting "bus-width" from device tree.
  This has been done in mmc_of_parse().

- For non-DM_MMC, move bus width configuration from fsl_esdhc_init()
  to fsl_esdhc_initialize() which is non-DM_MMC specific.
  And fix up bus width configuration to support only 1-bit, 4-bit,
  or 8-bit. Keep using 8-bit if it's not set because many platforms
  use driver without providing max bus width.

- Remove bus_width member from fsl_esdhc_priv structure.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Yangbo Lu
5b05fc0310 mmc: fsl_esdhc: fix voltage validation
Voltage validation should be done by CMD8. Current comparison between
mmc_cfg voltages and host voltage capabilities is meaningless.
So drop current comparison and let voltage validation is through CMD8.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Yangbo Lu
531ccd407c mmc: fsl_esdhc: drop controller initialization in fsl_esdhc_init()
Controller initialization is not needed in fsl_esdhc_init().
It will be done in esdhc_init() for non-DM_MMC, and in
esdhc_init_common() in probe for DM_MMC.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-11-05 11:21:24 +08:00
Tom Rini
73b6e6ad25 u-boot-imx-20191104
-------------------
 
 - i.MX NAND: nandbcb support for MX6UL / i.MX7
 - i.MX8: support for HAB
 - Convert to DM (opos6ul, mccmon6)
 - Toradex i.MX6ull colibri
 - sync DTS with kernel
 
 Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/606853416
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Merge tag 'u-boot-imx-20191104' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191104
-------------------

- i.MX NAND: nandbcb support for MX6UL / i.MX7
- i.MX8: support for HAB
- Convert to DM (opos6ul, mccmon6)
- Toradex i.MX6ull colibri
- sync DTS with kernel

Travis : https://travis-ci.org/sbabic/u-boot-imx/builds/606853416
2019-11-04 12:57:41 -05:00
Tom Rini
3b02d614b4 Merge branch '2019-11-04-ti-imports'
- Various CPSW related improvements, DTS resync
2019-11-04 12:57:34 -05:00
Grygorii Strashko
62f8e846a7 net: ti: cpsw: convert to use dev/ofnode api
Conver TI CPSW driver to use dev/ofnode api.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
[trini: Add <dm/ofnode.h> to provide the prototype to ofnode]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-11-04 12:56:37 -05:00
Tom Rini
ee93ef0c4b Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Add support for Intel FSP-S and FSP-T in binman
- Correct priority selection for image loaders for SPL
- Add a size check for TPL
- Various small SPL/TPL bug fixes and changes
- SPI: Add support for memory-mapped flash
2019-11-03 19:28:54 -05:00
Igor Opaniuk
9ab5f221a5 nand: mxs_nand: add API for switching different BCH layouts
On i.MX7 in a sake of reducing the disturbances caused by a neighboring
cells in the FCB page in the NAND chip, a randomizer is enabled when
reading the FCB page by ROM bootloader.

Add API for setting BCH to specific layout (and restoring it back) used by
ROM bootloader to be able to burn it in a proper way to NAND using
nandbcb command.

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Anti Sullin <anti.sullin@artecdesign.ee>
Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2019-11-03 21:49:19 +01:00
Ye Li
264977d1c2 mach-imx: Adding new argument for SIP call interface
Need to pass total 5 arguments for SIP HAB call on i.MX8MQ,
so update the interface to add new argument.

Signed-off-by: Ye Li <ye.li@nxp.com>
[agust: fixed imx8m-power-domain build]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Peng Fan
672fc540cd power: pmic: Kconfig: add CONFIG_SPL_DM_PMIC_BD71837
Add CONFIG_SPL_DM_PMIC_BD71837 to make this driver could be
used in SPL stage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Peng Fan
e0f724f718 pmic: bd71837: drop DEBUG macro
Drop DEBUG macro definition which is used for debug purpose.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Sébastien Szymanski
cde421cfc8 video: mxsfb: set gd->fb_base
Set gd->fb_base so it can be shown with bdinfo command.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-11-03 17:04:16 +01:00
Robert Hancock
f2929d11a6 watchdog: imx: Use immediate reset bits for expire_now
The expire_now function was previously setting the watchdog timeout to
minimum and waiting for the watchdog to expire. However, this watchdog
also has bits to trigger immediate reset. Use those instead, like the
Linux imx2_wdt driver does.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03 17:04:16 +01:00
Robert Hancock
ceea0c145d watchdog: imx: Add DT ext-reset handling
The Linux imx2_wdt driver uses a fsl,ext-reset-output boolean in the
device tree to specify whether the board design should use the external
reset instead of the internal reset. Use this boolean to determine which
mode to use rather than using external reset unconditionally.

For the legacy non-DM mode, the external reset is always used in order
to maintain the previous behavior.

Signed-off-by: Robert Hancock <hancock@sedsystems.ca>
2019-11-03 17:04:16 +01:00
Grygorii Strashko
da6a728ea4 net: ti: am65x-cpsw: fix mac tx internal delay for rgmii-rxid mode
Now AM65x CPSW2G driver will disable MAC TX internal delay for PHY
interface mode "rgmii-rxid" which is incorrect. Hence, fix it by keeping
default value (enabled) for MAC TX internal delay when "rgmii-rxid"
interface mode is selected.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
a3c867a217 net: ti: cpsw: fix mac tx internal delay for rgmii-rxid mode
Now TI CPSW driver will disable MAC TX internal delay for PHY interface
mode "rgmii-rxid" which is incorrect.

Hence, fix it by keeping default value (enabled) for MAC TX internal delay
when "rgmii-rxid" interface mode is selected.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
3c57b620db net: ti: cpsw: add support for standard eth "max-speed" dt property
This patch adds support for standard Ethernet "max-speed" DT property to
allow PHY link speed limitation.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
4040148b9e net: ti: cpsw: move parsing of dt port's parameters in separate func
Move parsing of dt port's parameters in separate func for better code
readability.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Grygorii Strashko
60e81d0d28 net: ti: cpsw: enable 10Mbps link speed support in rgmii mode
According to TRMs the 10Mbps link speed is supported in RGMII only when
CPSW2G MAC SL is configured for External Control ("in band") mode
CPSW_SL_MACCTRL.EXT_EN(18) = 1.

Hence update cpsw_slave_update_link() to follow documentation.

[1] https://patchwork.kernel.org/patch/10285239/
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2019-11-03 09:36:06 -05:00
Simon Glass
a478a26cd0 x86: timer: Use a separate flag for whether timer is inited
At present the value of the timer base is used to determine whether the
timer has been set up or not. It is true that the timer is essentially
never exactly 0 when it is read. However 'time 0' may indicate the time
that the machine was reset so it is useful to be able to denote that.

Update the code to use a separate flag instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:27 +08:00
Simon Glass
096c71e34b x86: timer: Set up the timer in timer_early_get_count()
This function can be called before the timer is set up. Make sure that the
init function is called so that it works correctly.

This is needed so that bootstage can work correctly in TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:27 +08:00
Simon Glass
c53b318e1b spi: Add support for memory-mapped flash
On x86 platforms the SPI flash can be mapped into memory so that the
contents can be read with normal memory accesses.

Add a new SPI method to find the location of the SPI flash in memory. This
differs from the existing device-tree "memory-map" mechanism in that the
location can be discovered at run-time.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-11-03 07:20:26 +08:00
Tom Rini
61e8f2985b Merge tag 'arc-fixes-for-2020.01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
ARC fixes for v2020.01-rc2

The main change is move to DM_MMC of yet 2 another ARC boards:
AXS101 & IoTDK.

Among that we improve handling of stock-formatted SD-cards of high volume
on EM SDP as well as introduction of reset driver for HSDK which is required
for prepser reinitialization of some peripherals like USB etc.
2019-11-01 17:49:40 -04:00
Eugeniy Paltsev
c597e248d9 ARC: HSDK: introduce reset driver
Introduce reset driver for Synopsys ARC HSDK SoC

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-11-01 16:45:40 +03:00
Tom Rini
24b77393a5 Pull request for UEFI sub-system for efi-2020-01-rc2
Provide a better user interface for setting UEFI variables.
 
 Bug fixes:
 - ext4 file system not discovered on UEFI block device
 - 'make tests' build error on 32bit systems
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Merge tag 'efi-2020-01-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-01-rc2

Provide a better user interface for setting UEFI variables.

Bug fixes:
- ext4 file system not discovered on UEFI block device
- 'make tests' build error on 32bit systems
2019-11-01 09:37:02 -04:00
Tom Rini
bb1bb4bb5d Fix for patman with email addresses containing commas
Bootstage improvements for TPL, SPL
 Various sandbox and dm improvements and fixes
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Merge tag 'dm-pull-29oct19' of git://git.denx.de/u-boot-dm

- Fix for patman with email addresses containing commas
- Bootstage improvements for TPL, SPL
- Various sandbox and dm improvements and fixes
2019-11-01 09:34:35 -04:00
Jean-Jacques Hiblot
4e18429883 drivers: phy: Handle gracefully NULL pointers
For some controllers PHYs can be optional. Handling NULL pointers without
crashing nor failing, makes it easy to handle optional PHYs.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-31 07:22:53 -04:00
Roman Kapl
6e7325533b ata: ahci allow 64-bit DMA for SATA
Allow 64-bit DMA on AHCI. If not supported by the host controller, at
least print a message and fail.

Signed-off-by: Roman Kapl <rka@sysgo.com>
2019-10-31 07:22:53 -04:00
Patrick Wildt
2f83481dff nvme: use page-aligned buffer for identify command
Change the stack-allocated buffer for the identification command
to explicitly allocate page-aligned buffers.  Even though the spec
seems to allow having admin queue commands on non page-aligned
buffers, it seems to not be possible on my i.MX8MQ board with a
a Silicon Power P34A80.  Since all of the NVMe drivers I have seen
always do admin commands on a page-aligned buffer, which does work
on my system, it makes sense for us to do that as well.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31 07:22:53 -04:00
Patrick Wildt
8c403402ca nvme: flush dcache on both r/w, and the prp list
It's possible that the data cache for the buffer still holds data
to be flushed to memory, since the buffer was probably used as stack
before.  Thus we need to make sure to flush it also on reads, since
it's possible that the cache is automatically flused to memory after
the NVMe DMA transfer happened, thus overwriting the NVMe transfer's
data.  Also add a missing dcache flush for the prp list.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31 07:22:53 -04:00
Heinrich Schuchardt
232ba76231 virtio: pci: use correct type in virtio_pci_bind()
For printing as %u we should use an unsigned int.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-31 07:22:53 -04:00
Marek Vasut
02b0e1a36c usb: ehci-hcd: Keep async schedule running
Profiling the EHCI driver shows a significant performance problem in
ehci_submit_async(). Specifically, this function keeps enabling and
disabling async schedule back and forth for every single transaction.
However, enabling/disabling the async schedule does not take effect
immediatelly, but instead may take up to 1 mS (8 uFrames) to complete.

This impacts USB storage significantly, esp. since the recent reduction
of maximum transfer size to support more USB storage devices. This in
turn results in sharp increase in the number of ehci_submit_async()
calls. Since one USB storage BBB transfer does three such calls and
the maximum transfer size is 120 kiB, the overhead is 6 mS per 120 kiB,
which is unacceptable.

However, this overhead can be removed simply by keeping the async
schedule running. Specifically, the first transfer starts the async
schedule and then each and every subsequent transfer only adds a new
QH into that schedule, waits until the QH is completed and does NOT
disable the async schedule. The async schedule is stopped only by
shutting down the controller, which must happen before moving out
of U-Boot, otherwise the controller will corrupt memory.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2019-10-31 12:13:40 +01:00
Patrick Delaunay
067c13c70b dfu: add callback for flush and initiated operation
Add weak callback to allow board specific behavior
- flush
- initiated

This patch prepare usage of DFU back end for communication with
STM32CubeProgrammer on stm32mp1 platform with stm32prog command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
ec44cace4b dfu: add DFU virtual backend
Add a virtual DFU backend to allow board specific read and write
(for OTP update for example).

Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
d5640f700d dfu: add partition support for MTD backend
Add the support of MTD partition for the MTD backend.

The expected dfu_alt_info for one alternate on the mtd device :
	<name> part <part_id>
        <name> partubi <part_id>

"partubi" also erase up to the end of the partition after write operation.

For example: dfu_alt_info = "spl part 1;u-boot part 2; UBI partubi 3"

U-Boot> dfu 0 mtd nand0

Acked-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
6015af28ee dfu: add backend for MTD device
Add DFU backend for MTD device: allow to read
and write on all MTD device (NAND, SPI-NOR,
SPI-NAND,...)

For example :
> set dfu_alt_info "nand_raw raw 0x0 0x100000"
> dfu 0 mtd nand0

This MTD backend provides the same level than dfu nand
backend for NAND and dfu sf backend for SPI-NOR;
So it can replace booth of them but it also
add support of spi-nand.

> set dfu_alt_info "nand_raw raw 0x0 0x100000"
> dfu 0 mtd spi-nand0

The backend code is based on the "mtd" command
introduced by commit 5db66b3aee ("cmd: mtd:
add 'mtd' command")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
0de1022d88 dfu: allow read with no data without error for EOF indication
This patch allows the DFU backend to indicate that that it can't
provide no more data to fill the DFU buffer, by setting b_left =0
without error, even if the size of received data is lower of the
expected total size indicated by get_medium_size.

For USB DFU stack point of view, it is acceptable:
the read length < requested size in DFU_UPLOAD and the
transaction is stopped.

That avoid infinite loop issue in dfu_read_buffer_fill because the
size for the DFU read is limited by get_medium_size = r_left
and the DFU stack expects that read is allowed up to this size.

This issue never occurs for current flash device (where chunk are
always completely read, and b_left will be never 0) but it is useful for
virtual partition when the backend only know the max size of this
alternate, the real size of the data are only known in the read
treatment.

PS: for file access on mmc, EOF is never reached as
    dfu_get_medium_size_mmc returns the exact size of the file.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
febabe3ed4 dfu: allow to manage DFU on several devices
Add support of DFU for several interface/device
with one command.

The format for "dfu_alt_info" in this case is :
- <interface> <dev>'='alternate list (';' separated)
- each interface is separated by '&'

The previous behavior is always supported.

One example for NOR (bootloaders) + NAND (rootfs in UBI):

U-Boot> env set dfu_alt_info \
"sf 0:0:10000000:0=spl part 0 1;u-boot part 0 2; \
u-boot-env part 0 3&nand 0=UBI partubi 0,3"

U-Boot> dfu 0 list

DFU alt settings list:
dev: SF alt: 0 name: spl layout: RAW_ADDR
dev: SF alt: 1 name: ssbl layout: RAW_ADDR
dev: SF alt: 2 name: u-boot-env layout: RAW_ADDR
dev: NAND alt: 3 name: UBI layout: RAW_ADDR

U-Boot> dfu 0

$> dfu-util -l

Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=3, name="UBI", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=2, name="u-boot-env", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=1, name="u-boot", serial="002700333338511934383330"
Found DFU: [0483:5720] ver=9999, devnum=96, cfg=1,\
 intf=0, alt=0, name="spl", serial="002700333338511934383330"

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
9ada683055 dfu: prepare the support of multiple interface
Split the function dfu_config_entities with 2 new functions
- dfu_alt_init
- dfu_alt_add

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
cb986ba0fe dfu: sf: add partition support for nor backend
Copy the partition support from NAND backend to SF,
support part and partubi option.
In case of ubi partition, erase the rest of the
partition as it is mandatory for UBI.

The added code is under compilation flag CONFIG_DFU_SF_PART
activated by default.

for example:

U-Boot> env set dfu_alt_info "spl part 0 1;\
u-boot part 0 2;u-boot-env part 0 3;UBI partubi 0 4"
U-Boot> dfu 0 sf 0:0:10000000:0

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-31 12:12:31 +01:00
Patrick Delaunay
909b690b31 dfu: cosmetic: cleanup sf to avoid checkpatch error
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Marek Szyprowski
fd15b58c1a dwc3: flush cache only if there is a buffer attached to a request
Calling cache flush on invalid buffer, even with zero length might cause
an exception on certain platforms.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2019-10-31 12:12:31 +01:00
Marek Szyprowski
d2d8eab421 dfu: mmc: add support for in-partition offset
Add possibility to define a part of partition as a separate DFU entity.
This allows to have more than one items on the given partition.

The real use case for this option is TM2 board. It can use u-boot stored
as Linux kernel on the defined partition (as RAW data) and load the real
kernel from the same partition, but stored under the certain offset.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Marek Szyprowski
ade08db899 gadget: f_thor: properly enable 3rd endpoint defined by the protocol
This is needed to make Windows THOR flash tool happy, because it
starts sending data only when interrupt packet is received on the 3rd
endpoint.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Ralph Siemsen
0a815ff7bb dfu: dfu_nand: reduce verbosity
In combination with multiple partitions in NAND, this printf() ends up
being more noise than helpful. Change it to debug() instead.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-10-31 12:12:31 +01:00
Vignesh Raghavendra
d624434f5e dwc3-generic: Don't fail probe if clk/reset entries are absent
Some boards don't populate clk/reset entries as these are are optional
as per binding documentation. Therefore, don't fail driver probe if
clk/reset entries are absent in DT.

This fixes fastboot failures seen due to enabling of CONFIG_CLK on AM57xx

Fixes: e8e683d33b ("board: ti: am57xx-idk: Configure the CDCE913 clock synthesizer")
Reported-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-10-31 12:11:24 +01:00
Keerthy
3135022cb4 gpio: da8xx_gpio: Fix the _gpio_direction_output function
_gpio_direction_output function currently calls gpio_set_value
with the wrong gpio number. gpio_set_value in the uclass driver
expects a different gpio number and the _gpio_direction_output
is currently providing the number specific to the bank.

Hence fix it by calling the _gpio_set_value function instead.

Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Fixes: 8e51c0f254 ("dm: gpio: Add DM compatibility to GPIO driver for Davinci")
Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-10-30 17:48:47 -04:00
Tom Rini
412326d1bc Merge tag 'u-boot-clk-23Oct2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-clk
- Add I2C clocks for i.MX6Q CCF driver
- Fix check in clk_set_default_parents()
- Managed API to get clock from device tree
- Fixes for core clock code (including sandbox regression tests)
2019-10-30 13:13:46 -04:00
Heinrich Schuchardt
ee5041451e blk: set log2blksz in blk_create_device()
The ext4 file system requires log2blksz to be set. So when setting the
block size on the block descriptor we should fill this field too.

This fixes a problem with EFI block devices providing ext4 partitions, cf.
https://lists.denx.de/pipermail/u-boot/2019-October/387702.html.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-30 17:49:40 +01:00
Tom Rini
700336f7e4 Merge tag 'mmc-10-29-2019' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc driver cleanup
- spl_mmc bug fix to avoid access wrong emmc partition
2019-10-30 09:06:33 -04:00
Tom Rini
cc64810dc6 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- H6 dts(i) sync (Clément)
- H6 PIO (Icenowy)
- Fix pll1 clock calculation (Stefan)
- H6 dram, half DQ (Jernej)
- A64 OLinuXino eMMC (Sunil)
2019-10-30 09:04:52 -04:00
Yangbo Lu
5d336d1701 mmc: fsl_esdhc: drop i.MX DDR support code
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.

0e1bf61 mmc: fsl_esdhc: Add support for DDR mode

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:22 +08:00
Yangbo Lu
2913926f3b mmc: fsl_esdhc: remove redundant DM_MMC checking
Remove redundant DM_MMC checking which is already in DM_MMC conditional
compile block.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:21 +08:00
Yangbo Lu
41dec2fe99 mmc: fsl_esdhc: make BLK as hard requirement of DM_MMC
U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
support it, so let's force to use it.

- Drop non-BLK support for DM_MMC introduced by below patch.
  66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled

- Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).

- Use DM_MMC instead of BLK for conditional compile.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2019-10-29 10:09:21 +08:00
Jean-Jacques Hiblot
d60ae4c59d fdt: Fix alignment issue when reading 64-bits properties from fdt
The FDT specification [0] gives a requirement of aligning properties on
32-bits. Make sure that the compiler is aware of this constraint when
accessing 64-bits properties.

[0]: https://github.com/devicetree-org/devicetree-specification/blob/master/source/flattened-format.rst

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-27 13:01:53 -06:00
Kever Yang
97b5f9d1a0 dm: core: Update log method for uclass_find_device_by_seq
Use log() insted of debug() for uclass_find_device_by_seq function,
since this print is very much and we can filter it out with log()
interface.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move #define to top of file as per docs:
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-27 13:01:43 -06:00
Simon Glass
5ca5ec1e32 dm: regmap: Fix mask in regmap_update_bits()
This function assumes that the 'val' parameter has no masked bits set.
This is not defined by the function prototype though. Fix the function to
mask the value and update the documentation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-27 10:56:41 -06:00
Tom Rini
ffc379b42c - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
 - mtmips: add new drivers for clock, reset-controller and pinctrl
 - mtmips: add support for high speed UART
 - mtmips: update/enhance drivers for SPI and ethernet
 - mtmips: add support for MMC
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Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips

- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
2019-10-25 20:07:24 -04:00
Tom Rini
15147dc6a9 Merge branch '2019-10-24-ti-imports'
- Enable DFU on dra7xx boards
- Further Keystone 3 platform improvements
2019-10-25 17:33:28 -04:00
Kevin Scholz
3bb3f266ee ram: k3-j721e: Add support for J721E DDR controller
The J721E DDR subsystem comprises DDR controller, DDR PHY and wrapper
logic to integrate these blocks in the device. The DDR subsystem is
used to provide an interface to external SDRAM devices which can be
utilized for storing program or data. Introduce support for the
DDR controller and DDR phy within the DDR subsystem.

Signed-off-by: Kevin Scholz <k-scholz@ti.com
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
James Doublesin
34f27b2e86 ram: k3-am654: Do not rely on default values for certain DDR register
Added the following registers to the DDR configuration:
- ACIOCR0,
- ACIOCR3,
- V2H_CTL_REG,
- DX8SLxDQSCTL.

Modified enable_dqs_pd and disable_dqs_pd to only touch the associated
bit fields for pullup and pulldown registers (to preserve slew rate and
other bits in that same register). Also update the dts files in the same
patch to maintain git bisectability.

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
James Doublesin
c78ac7a0c9 ram: k3-am654: add support for LPDDR4 and DDR3L DDRs
Added training support for LPDDR4 and DDR3L DDRs.  Also added/changed
some register configuration to support all 3 DDR types

Signed-off-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
Tom Rini
271103ac0b Merge branch 'master' of git://git.denx.de/u-boot-usb
- DWC3 improvements
- i.MX7 EHCI bugfix
2019-10-25 13:50:51 -04:00
Tom Rini
c9e50bb12a Second set of u-boot-atmel features and fixes for 2020.01 cycle
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Merge tag 'u-boot-atmel-2020.01-b' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features and fixes for 2020.01 cycle

This feature set includes Eugen's work on a new tiny flexcom driver and
eeprom mac retrieval for the sam9x60-ek board.
2019-10-25 13:50:33 -04:00
Tom Rini
e382713d22 Xilinx/FPGA changes for v2020.01 part 2
common:
 - Fix manual relocation for repeatable commands
 
 arm:
 - Also clean up generated dtbos
 
 microblaze:
 - Add support for Manual relocation in crypto framework
 - Tune and align architecture bootm support
 
 zynq:
 - DT sync ups
 - Some defconfig updates
 - Remove empty board_early_init_f()
 
 zynqmp:
 - Clean firmware handing via drivers/firmware/
 - DT/defconfig name alignments
 - DT cleanups with using firmware based clock driver
 - Some defconfig updates
 - Add IIO ina226 DT description
 - Tune zynqmp_psu_init_minimalize.sh script
 - Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216
 
 versal:
 - Clean firmware handing via drivers/firmware/
 - Add gpio support
 - Enable DT overlay/USB/CLK/FPGA
 - DT updates
 - Tune mini configuration
 
 spi:
 - gqspi - Remove unused headers
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Merge tag 'xilinx-for-v2020.01-part2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2020.01 part 2

common:
- Fix manual relocation for repeatable commands

arm:
- Also clean up generated dtbos

microblaze:
- Add support for Manual relocation in crypto framework
- Tune and align architecture bootm support

zynq:
- DT sync ups
- Some defconfig updates
- Remove empty board_early_init_f()

zynqmp:
- Clean firmware handing via drivers/firmware/
- DT/defconfig name alignments
- DT cleanups with using firmware based clock driver
- Some defconfig updates
- Add IIO ina226 DT description
- Tune zynqmp_psu_init_minimalize.sh script
- Add single nand mini configuration, e-a2197, m-a2197-02/03 and zcu216

versal:
- Clean firmware handing via drivers/firmware/
- Add gpio support
- Enable DT overlay/USB/CLK/FPGA
- DT updates
- Tune mini configuration

spi:
- gqspi - Remove unused headers
2019-10-25 11:23:46 -04:00
Weijie Gao
77ebea23c3 mmc: mtk-sd: add a dts property cd-active-high for builtin-cd mode
This patch adds a dts property cd-active-high for builtin-cd mode to make
it configurable instead of using hardcoded active-low.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
3c92a957ee mmc: mtk-sd: add support for MediaTek MT7620/MT7628 SoCs
This patch adds mmc support for MediaTek MT7620/MT7628 SoCs.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
877d03903c net: mt7628-eth: add support to isolate LAN/WAN ports
This patch add support for mt7628-eth to isolate LAN/WAN ports mainly to
prevent LAN devices from getting IP address from WAN.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
c88ee3ea0a net: mt7628-eth: free rx descriptor on receiving failure
When received a packet with an invalid length recorded in rx descriptor,
we should free this rx descriptor to allow us to continue to receive
following packets.
Without doing so, u-boot will stuck in a dead loop trying to process this
invalid rx descriptor.

This patch adds a call to mt7628_eth_free_pkt() after received an invalid
packet length.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
f079321009 net: mt7628-eth: make phy link up detection optional via DT
The mt7628 has an embedded ethernet switch (5 phy ports + 1 cpu port).
Although in IOT mode only port0 is usable, the phy0 is still connected
to the switch, not the ethernet gmac directly.

This patch rewrites it and makes it optional. It can be turned on by adding
mediatek,poll-link-phy = <?> explicitly into the eth node. By default the
driver is switch mode with all 5 phy ports working without link detection.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
2734fdef5c net: mt7628-eth: remove hardcoded gpio settings and regmap-based phy reset
This patch removes hardcoded gpio settings as they have been replaced by
pinctrl in dts, and also replaces regmap-based phy reset with a more
generic reset controller.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
4cce51141f phy: mt76x8-usb-phy: add slew rate calibration and remove non-mt7628 part
This patch adds slew rate calibration for mt76x8-usb-phy, removes code
which belongs to mt7620, and gets rid of using syscon and regmap by using
clock driver and reset controller.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
f7ae6b682c reset: add reset controller driver for MediaTek MIPS platform
This patch adds reset controller driver for MediaTek MIPS platform and
header file for mt7628.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
3fad441c54 pinctrl: add support for MediaTek MT7628
This patch adds pinctrl support for mt7628, with a file for common pinmux
functions and a file for mt7628 which has additional support for pinconf.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
43405e009b spi: mt7621-spi: restore default register value after each xfer
Currently this driver uses a different way to implement the spi xfer,
by modifying some fields of two registers, which is incompatible with the
MTK's original SDK linux driver. This will cause the flash data being
damaged by the SDK driver.

This patch lets the mt7621_spi_set_cs() restore the original register
fields after cs deactivated.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
54a6b8e793 spi: mt7621-spi: remove data cache and rewrite its xfer function
The mt7621 spi controller supports continuous generic half-duplex spi
transaction. There is no need to cache xfer data at all.

To achieve this goal, the OPADDR register must be used as the first data
to be sent. And follows the eight generic DIDO registers. But one thing
different between OPADDR and DIDO registers is OPADDR has a reversed byte
order.

With this patch, any amount of data can be read/written in a single xfer
function call.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
f09978566b spi: mt7621-spi: use clock frequency from clk driver
This patch lets the spi driver to use clock provided by the clk driver
since the new clk-mt7628 driver provides accurate sys clock frequency.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
77ed3c42fe clk: add clock driver for MediaTek MT76x8 platform
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:44 +02:00
Weijie Gao
44fa676e58 serial: serial_mtk: add non-DM version for SPL
This patch adds non-DM version for mtk hsuart driver and makes it
compatible with ns16550a driver in configuration.
This is needed in SPL with CONFIG_SPL_DM disabled for reducing size.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:43 +02:00
Weijie Gao
99ced5331b serial: serial_mtk: enable FIFO and disable flow control
This patch adds codes to enable FIFO and disable flow control taken from
ns16550 driver.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-10-25 17:20:43 +02:00
William Zhang
e365de9051 drivers: nand: brcmnand: fix nand_chip ecc layout structure
The current brcmnand driver is based on 4.18 linux kernel which uses
mtd_set_ooblayout to set ecc layout. But nand base code in u-boot is from
old kernel which does not use this new API and expect nand_chip.ecc.layout
structure to be set. This cause nand_scan_tail function running into a bug
check if the device has a different oob size than the default ones.

This patch ports the brcmstb_choose_ecc_layout function from kernel 4.6.7
that supports the ecc layout struture and replaces the mtd_set_ooblayout
method

Signed-off-by: William Zhang <william.zhang@broadcom.com>
Reviewed-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-10-25 17:20:43 +02:00
Álvaro Fernández Rojas
a9f80cf9ad nand: brcm: add BCM6368 support
This adds support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-10-25 17:20:43 +02:00
Fabio Estevam
395ec74186 spi-nor-ids: Add support for Adesto AT25SL321
Add an entry for the Adesto AT25SL321 SPI NOR chip.

This SPI NOR chip is found in the Embedded Artist i.MX7ULP COM board.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Frieder Schrempf
832ce20278 mtd: spi: Clean up usage of CONFIG_SPI_FLASH_MTD
Most boards currently use SPI_FLASH_MTD only in U-Boot proper, not in
SPL. They often rely on hacks in the board header files to include
this option conditionally. To be able to fix this, we previously
introduced a separate option SPL_SPI_FLASH_MTD.

Therefore we can now adjust the Makefile and change the code in
sf_probe.c and sf_internal.h to use CONFIG_IS_ENABLED(SPI_FLASH_MTD).

We also need to move all occurences of CONFIG_SPI_FLASH_MTD from the
header files to the according defconfigs. The affected boards are
socfpga, aristainetos, cm_fx6, display5, ventana, rcar-gen2, dh_imx6
and da850evm.

We do this all in one patch to guarantee bisectibility.

This change was tested with buildman to make sure it does not
introduce any regressions by comparing the resulting binary sizes.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
73d74b5881 spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status
register that indicates various errors that may be encountered during
erase/write operations. Therefore add USE_FSR flag wherever missing.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
8651593a8c spi-nor: spi-nor-ids: Add entries for mt25q variants
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries
for the same. These flashes have bit 6 set in 5th byte of READ ID
response when compared to n25q* variants.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
d66e07cdf9 spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
Per datasheets of n25q256* and n25q512* not all variants of n25q256* and
n25q512* support 4 Byte stateless addressing opcodes. Therefore drop
SPI_NOR_4B_OPCODES flag from these entries

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Ley Foon Tan
e7e05fcb3e spi: designware_spi: Disable and free clock when remove driver
Disable and free clock when remove driver.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
2a2174d3da mtd: spi-nor-core: Replace MTD_SPI_NOR_USE_4K_SECTORS with SPI_FLASH_USE_4K_SECTORS
U-Boot uses CONFIG_SPI_FLASH_USE_4K_SECTORS to enable 4K small sector
support. Use that instead of MTD_SPI_NOR_USE_4K_SECTORS.

Reported-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Vignesh Raghavendra
cc9118757f mtd: spi-nor-core: Use dev_err for reporting erase/write failures
Use dev_err() when reporting reason for erase/write failures so that
users can be made aware of the reason for failure.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:32 +05:30
Frieder Schrempf
64f736c901 mtd: spi: Add a new option SPL_SPI_FLASH_MTD to Kconfig
To allow SPI_FLASH_MTD being enabled separately in SPL we add a new
option. The only user currently is the stm32mp15_basic board.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
dc738248db spi: Kconfig: Enable SPI_SUNXI for SUNXI
SPI_SUNXI driver is fully dm-aware and the Allwinner
architecture kconfig would have logic to enable the
DM_SPI. So, select default spi sunxi driver for
sunxi architecture.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
77df1a9b66 mtd: spi: Kconfig: Imply SPI_FLASH if DM_SPI_FLASH
DM_SPI_FLASH should require spi flash interface code for dm
version, so imply SPI_FLASH core by default if any board
enabled DM_SPI_FLASH.

This overcome the explicit enablement of CONFIG_SPI_FLASH on
respective boards when DM_SPI_FLASH being used.

Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Bin Meng
4b06000395 dm: spi: Change cs_info op to return -EINVAL for invalid cs num
We need distinguish the following two situations in various SPI APIs:

- given chip select num is invalid
- given chip select num is valid, but no device is attached

Currently -ENODEV is returned for both cases.

For the first case, it's more reasonable to return -EINVAL instead of
-ENODEV for invalid chip select numbers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Bin Meng
4dd520b36b dm: spi: Return 0 if driver does not implement ops->cs_info
If an SPI controller driver does not implement ops->cs_info, that
probably means any chip select number could be valid, hence let's
return 0 for spi_cs_info().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # SoPine
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
0c8e605670 spi: Kconfig: Add help text
Add detailed help text for SPI support.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
97009d543d mtd: spi-nor: ids: Add is25wp256 chip
Add is25wp256, chip to spi-nor id table.

Tested on SiFive FU540 board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-25 00:48:31 +05:30
Jagan Teki
989fd97fe5 mtd: spi: Kconfig: Update CONFIG_SPI_FLASH
1) CONFIG_SPI_FLASH is not just a legacy code, but it has common
   core code which handle both dm and non-dm spi flash code. So
   fix the info text to make it clear globally.

2) Since it's flash core it shouldn't depends on legacy SPI,
   so remove the 'depends on SPI'

Cc: Vignesh R <vigneshr@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-10-25 00:42:57 +05:30
Tom Rini
17fd9915a4 Merge branch '2019-10-24-UFS-support'
- Add Universal Flash Storage (UFS) support
2019-10-24 09:51:48 -04:00
Ye Li
235f5e158e ehci-mx6: Update EHCI driver to support OTG0 on i.MX7ULP
The ULP has two USB controllers. These two controllers have similar NC
registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not
the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY
to work.

This patch only supports OTG0 with UTMI PHY.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
2019-10-24 15:31:13 +02:00
Igor Opaniuk
1198a104d3 usb: ehci-mx6: Fix bus enumeration for iMX7 SoCs
This fixes the issues with calculation of controller indexes in
ehci_usb_bind() for iMX7, as USB controllers on iMX7 SoCs aren't
placed next to each other, and their addresses incremented by 0x10000.

Example of USB nodes for iMX7S/D:

usbotg1: usb@30b10000 {
    compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
    reg = <0x30b10000 0x200>;
           ^^^^^^^^^^
....
usbotg2: usb@30b20000 {
    compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
    reg = <0x30b20000 0x200>;
           ^^^^^^^^^^
....

usbh: usb@30b30000 {
    compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
    reg = <0x30b30000 0x200>;
           ^^^^^^^^^^
....

Which was leading to usb enumeration issues:
Colibri iMX7 # usb start
starting USB...
Bus usb@30b10000: USB EHCI 1.00
Bus usb@30b20000: probe failed, error -22
scanning bus usb@30b10000 for devices... 1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found

Fixes: 501547cec1("usb: ehci-mx6: Fix bus enumeration for DM case")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2019-10-24 15:31:13 +02:00
Michal Simek
039c740d66 arm64: zynqmp: Switch to xlnx-zynqmp-clk header
Use prepared header instead of hardcoded values.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
T Karthik Reddy
ef92ed26a5 drivers: crypto: rsa_mod_exp: Add manual relocation for ops->mod_exp()
This patch adds manual relocation for Modular Exponentiation if
CONFIG_NEEDS_MANUAL_RELOC is enabled.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
3a79c6052a spi: zynqmp: Remove unused platform headers
There is no reason to include clk.h and hardware.h headers.
Driver doesn't require them.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Shubhrajyoti Datta
98927daada gpio: zynq: Add gpio driver support for PMC gpio
This patch adds support for gpio driver for pmc gpio.

Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Ashok Reddy Soma
982485214f gpio: zynq: Add gpio driver support for Versal
This patch adds support for gpio driver for versal platform

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
44dccd5924 firmware: zynqmp: Clean up zynqmp_power_probe
Fix error debug messages to be more accurate and aligned with debug message
style in the whole file.
And do not initialize ret variable because it is initialized later on and
it is just additional step.

Fixes: 1327d1678b ("firmware: zynqmp: Add zynqmp-power support")
Reported-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-24 13:37:01 +02:00
Michal Simek
9bed8a63f7 firmware: zynqmp: Report error when xilinx_pm_request called from EL3
Function should report error when called in EL3 context. Also report it as
error instead 0 (success).

Reported-by: Luca Ceresoli <luca@lucaceresoli.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-24 13:37:01 +02:00
Michal Simek
403619515e arm64: zynqmp: Convert invoke_smc() to xilinx_pm_request()
Remove macros which use PM_SIP_SVC offset and convert invoke_smc() to
xilinx_pm_request() which do calculation with PM_SIP_SVC already.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
6596270ecb arm64: versal: Rename versal_pm_request to xilinx_pm_request
Use generic name instead of Versal specific because this should be also
used on ZynqMP.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Michal Simek
866225f394 arm64: xilinx: Move firmware functions from platform to driver
versal_pm_request() and invoke_smc() are almost the same. Only one
difference is that versal_pm_request is adding PM_SIP_SVC offset to api_id.
The patch is moving platform implementation to firmware driver code for
synchronization.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
2019-10-24 13:37:01 +02:00
Michal Simek
0f3604a2b3 arm64: versal: Clean pm_api_id usage
Copy enum values from platform code to firmware code. IDs are shared
between ZynqMP and Versal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Eugen Hristev
f81649586d misc: microchip_flexcom: introduce microchip_flexcom driver
The Microchip Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time according
to the device tree.
The bindings are kept as in Linux.
The driver registers to MISC_UCLASS.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-10-24 13:01:57 +03:00
Jean-Jacques Hiblot
2bbc1bbf5d phy: keystone-usb: handle the transition of the USB power domain
There is no proper power domain support for the keystone platforms.
However we need to turn off the USB domains before jumping to linux or it
fail to boot (observed with k2e and k2l platforms).
This can be done in the PHY driver as it is dedicated only to the keystone
platforms and matches the required on/off sequence.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
3e6ab7327f usb: dwc3: Kconfig: get rid of obsolete mode selection
The mode selection for the DWC3 is kind of obsolete. The driver does not
have to be host only or gadget only. This choice is confusing.
All the remaining callers of dwc3_uboot_init() explicitly set dr_mode
before calling the function, so none rely on a default behavior.

Remove the choice menu and keep only the USB_DWC3_GADGET option. Enable it
by default if USB_GADGET and USB_DWC3 are enabled.
It must be disabled for the evb-rk3328 as it uses DWC2 for the gadget and
DWC3 for the host.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
ba6c5f7a28 usb: dwc3: Add dwc3_of_parse() to get quirks information from DT
Add a new function that read quirk and configuration information from the
DT. The goal is to allow platforms using their own version of DWC3 driver
to migrate to the generic DWC3 driver.
The function is adapted from the function dwc3_get_properties() in the
linux dwc3 driver introduced in commit c5ac6116db35d.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1a63e5e5fb usb: dwc3-generic: if no max speed is specified in DT, assume super speed
There is no need to fail if the maximum speed is not specified.
If the speed is not specified, do the same as linux and assume super speed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
b575e90916 usb: dwc3-generic: add a new host driver that uses the dwc3 core
Currently the host driver used by dwc3-generic is "xhci-dwc3". This is
a functional driver but it doesn't use the dwc3 core and, in particular,
it lacks some bits that may be important.
For example on the k2 platforms, it is important that the phy are properly
suspended when the USB is not used anymore. The dwc3 core also has a
partial support for quirks.
The new driver can be used as a drop-in replacement for "xhci-dwc3".

In terms of implementation, it may seem strange that 2 private structures
dwc3_generic_host_priv and dwc3_generic_priv) are used. The reason for this
is simply that the xhci layer expects a struct xhci_ctrl at the beginning
of the private data and it seemed wasteful to include it also for the
peripheral case.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1af590df16 usb: dwc3-generic: factorize code
Factor code for re-usability.
This is another step toward adding host support.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
3a38a0adb9 usb: dwc3-generic: use platdata
Separate platform data from the private data.
This is one step toward adding host support.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
33a99b4365 usb: dwc3: always use the inlined version of dwc3_host_init/dwc3_host_exit
No one is actually implementing those functions.
We could remove calls to these altogether, but it does not really hurt to
keep the empty inlined version at the moment and it satisfies a symmetry
with the gadget mode.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
1708a12377 usb: xhci: move xhci.h to include usb
The xhci.h header file is currently located under drivers/usb/xhci
Move it to the include/usb folder to make it available to drivers that
are not under drivers/usb/xhci

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:17 +02:00
Jean-Jacques Hiblot
bbe3d4a6c1 usb: dwc3: switch to peripheral mode when exiting
This allow the phy to enter idle and then suspend.
the K2 platforms require the PHY to be suspended before the USB domain
clock can be turned off.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:16 +02:00
Jean-Jacques Hiblot
a8973731a4 usb: host: remove the xhci-zynqmp driver
This driver is not used anymore.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-24 11:28:16 +02:00
Vignesh Raghavendra
c2dfd0a4d8 mtd: Add TI HyperBus Memory Controller driver
AM654/J721e has HyperBus Memory Controller that supports HyperFlash and
HyperRAM devices. It provides a memory mapped interface to interact with
these devices. Add a driver to support the same.
Driver calibrates the controller, setups up for MMIO access and probes
HyperFlash child node.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-24 09:49:10 +02:00
Vignesh Raghavendra
d75eacf9b8 mtd: cfi_flash: Use CONFIG_SYS_MONITOR_BASE only when defined
Make use of CONFIG_SYS_MONITOR_BASE only when available to avoid build
error when CONFIG_SYS_MONITOR_BASE is not defined.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2019-10-24 09:48:53 +02:00
Faiz Abbas
4390eaf676 ufs: Add glue layer driver for TI J721E devices
Add glue layer driver for the controller present on TI's J721E devices.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
ef5fb5a84c ufs: Add Support for Cadence platform UFS driver
Add Support for the platform driver for the Cadence device present on
TI's J721e device.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
7feafb0ae4 ufs: Add Initial Support for UFS subsystem
Add Support for UFS Host Controller Interface (UFSHCI) for communicating
with Universal Flash Storage (UFS) devices. The steps to initialize the
host controller interface are the following:

- Initiate the Host Controller Initialization process by writing to the
Host controller enable register.
- Configure the Host Controller base address registers by allocating a
host memory space and related data structures.
- Unipro link startup procedure
- Check for connected device
- Configure UFS host controller to process requests

Also register this host controller as a SCSI host controller.

Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported to
U-boot.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
8fbac8e23e scsi: Add dma direction member to command structure
Some SCSI devices like UFS use DMA for executing scsi commands and hence
need to know the direction of transfer of the dma. Add a dma_dir element
to the command structure to facilitate this.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
d48f00ed11 scsi: Retry inquiry 3 times to overcome Unit Attention condition
The UFS SCSI device LUNs are observed to return failure the first time a
unit ready inquiry is sent and pass on the second try. Send this
inquiry 3 times to make sure device is ready.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
4ff572830e scsi: Add max_bytes_per_req to scsi_platdata
Add max_bytes_per_req to scsi_platdata to enable the host driver to limit
the number of bytes that can be read/written per request.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-10-23 20:47:12 -04:00
Faiz Abbas
66c54f1a3e scsi: Simplify scsi_read()/_write()
With no non-DM driver using scsi_read()/_write() APIs, remove
the legacy implementations.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
[trini: Reorder slightly and mark scsi_read/write behind BLK test to
avoid warnings]
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-10-23 20:47:12 -04:00
Jean-Jacques Hiblot
9a52be129c test: clk: test clock self assignment
Make sure that the clock self-assignment works by having a clock of
clk-sbox be configured automatically when clk-sbox is probed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
fd1ba29652 drivers: clk: Fix using assigned-clocks in the node of the clock it sets up
This fixes the case where assigned-clocks is used to define a clock
defaults inside this same clock's node. This is used sometimes to setup a
default parents and/or rate for a clock.

example:
muxed_clock: muxed_clock {
	clocks = <&clk_provider 0>, <&clk_provider 1>;
	#clock-cells = <0>;
	assigned-clocks = <&muxed_clock>;
	assigned-clock-parents = <&clk_provider 1>;
};

It doesn't work in u-boot because the assigned-clocks are setup *before*
the clock is probed. (clk_set_parent() will likely crash or fail if called
before the device probe function)
Making it work by handling "assigned-clocks" in 2 steps: first before the
clk device is probed, and then after the clk device is probed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
dd2e0ce2a4 test: clk: Update tests to also check the managed API
Add a few more clocks the clk_sandbox clock provider and get them using
the managed API.
Make sure they are released when the device is removed.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
52720c536f drivers: clk: Add a managed API to get clocks from the device-tree
Add devm_clk_get(), devm_clk_get_optional() to get clocks from the
device-tree. The clocks is automatically released and the data structure
freed when the device is unbound.
Also add devm_clk_put() to release the clock and free the data structure
manually.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
8a1661f20e drivers: clk: Handle gracefully NULL pointers
Prepare the way for a managed CLK API by handling NULL pointers without
crashing nor failing.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Lukasz Majewski
727fa4539c clk: Add support for I2C clocks on NXP's imx6q SoC which use CCF
This change adds support for I2C clock modeled in CCF. This code intention
is to only enable those clocks in the I2C driver with default settings.
For that reason the "busy" versions of clocks reuse the generic approach
and would need to be updated when one wants to adjust the I2C clock
frequency in U-Boot.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2019-10-22 16:14:05 +02:00
Jean-Jacques Hiblot
02e2a2ad2f clk: Fix error check in clk_set_default_parents()
According to the documentation in clk.h, clk_set_parent() return the new
rate of the clock or a negative error code.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2019-10-22 16:14:05 +02:00
Patrick Delaunay
44510daea4 dm: pinctrl: fix for introduce PINCONF_RECURSIVE option
Correct the name of the define used CONFIG_IS_ENABLED which is
not aligned with Kconfig name: CONFIG_$(SPL_)PINCONF_RECURSIVE.

The recursive calls is conditional only for UCLASS_PINCONFIG
"pinconfig" driver.
It is always needed to call pinctrl_post_bind for UCLASS_PINCTRL
"pinctrl", the test CONFIG_IS_ENABLED(PINCONF_RECURSIVE) need to
be removed for this driver.

This correct a regression introduced because the same patch is
applied twice times in u-boot-dm branch:
- commit e878b53a79 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")
- commit c20851b3d8 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-21 09:40:54 -04:00
Patrick Delaunay
ae799ffcae pinctrl: Kconfig: remove duplicated nodes
Remove the duplicated configs introduced when the same patch is
applied twice times:
- commit e878b53a79 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")
- commit c20851b3d8 ("dm: pinctrl: introduce PINCONF_RECURSIVE
  option")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-10-21 09:40:50 -04:00
Tom Rini
3b985bdeab - document alternative libretech-cc installation methods, including upstream TF-A and opensource tools
- add HDMI/CVBS display support for Amlogic G12A SoCs and SEI510 board
 - add support for Amlogic A311D based Khadas VIM3
 - add support for Amlogic S905X3 based SEI610 board, targeting Android support like SEI510
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Merge tag 'u-boot-amlogic-20191018' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- document alternative libretech-cc installation methods, including upstream TF-A and opensource tools
- add HDMI/CVBS display support for Amlogic G12A SoCs and SEI510 board
- add support for Amlogic A311D based Khadas VIM3
- add support for Amlogic S905X3 based SEI610 board, targeting Android support like SEI510
2019-10-18 16:36:44 -04:00
Neil Armstrong
a990c390a3 power: domain: add Amlogic Everything-Else power domain driver
Based on the 54ecb8f7028c ("Linux 5.4-rc1") Everything-Else power domain
driver for Amlogic SoCs.

This driver handles the VPU Power domain and other domains from the
Everything-Else part of the SM1 and G12A SoCs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18 14:33:21 +02:00
Neil Armstrong
2168a52e2b clk: meson-sm1: add compatible
The SM1 clock controller is almost identical to the G12A and
so far the differences don't matter.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18 14:26:59 +02:00
Neil Armstrong
a10388dc69 mmc: meson-gx: add support for mmc-pwrseq-emmc
Add support for mmc-pwrseq-emmc in the meson-gx mmc driver to support
enabling the eMMC.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-10-18 14:24:05 +02:00
Neil Armstrong
04eb4f45c1 video: meson: add compatible for Amlogic G12A
Finally add the Amlogic G12A SoC compatible for the VPU driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 11:45:36 +02:00
Neil Armstrong
573687c3be video: meson: sync with linux drm-misc tree
Synchronize the Amlogic Meson Video driver back with the latest
DRM misc tree, adding G12A platform support, from the latest commit:
528a25d040bc ("drm: meson: use match data to detect vpu compatibility")

The sync includes the following changes from Linux adapted to U-Boot:
- Add support for VIC alternate timings
- Switch PLL to 5.94GHz base for 297Mhz pixel clock
- Add registers for G12A SoC
- Add G12A Support for VPP setup
- Add G12A Support for VIU setup
- Add G12A support for OSD1 Plane
- Add G12A support for plane handling in CRTC driver
- Add G12A support for CVBS Encoder
- Add G12A Video Clock setup
- Add G12A support for the DW-HDMI Glue
- fix G12A HDMI PLL settings for 4K60 1000/1001 variations
- fix primary plane disabling
- fix G12A primary plane disabling
- mask value when writing bits relaxed
- crtc: drv: vpp: viu: venc: use proper macros instead of magic constants
- global clean-up
- add macro used to enable HDMI PLL
- venc: set the correct macrovision max amplitude value

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 11:42:55 +02:00
Neil Armstrong
0a3561119f video: meson: remove power domain get
Remove getting and enabling the node power domain since it's now handled
by the dm core directly.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 10:46:08 +02:00
Neil Armstrong
a0513b40cc clk: meson: g12a: add support for VPU/HDMI clocks
Add necessary clock support to set up clock for the VPU and
HDMI support.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 10:46:08 +02:00
Neil Armstrong
3dcdf85efd power: domain: meson-gx-pwrc: add G12A support
Add Amlogic G12A support for the gx-pwrc driver, aligned on the
Linux v5.2 driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-10-18 10:46:08 +02:00
Sagar Shrikant Kadam
d26b40450b gpio: sifive: add support for DM based gpio driver for FU540-SoC
This patch adds a DM based driver model for gpio controller present in
FU540-C000 SoC on HiFive Unleashed A00 board. This SoC has one GPIO
bank and 16 GPIO lines in total, out of which GPIO0 to GPIO9 and
GPIO15 are routed to the J1 header on the board.

This implementation is ported from linux based gpio driver submitted
for review by Wesley W. Terpstra <wesley@sifive.com> and/or Atish Patra
<atish.patra@wdc.com> (many thanks !!). The linux driver can be referred
here [1]

[1]: https://lkml.org/lkml/2018/10/9/1103

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-18 09:04:01 +08:00
Tom Rini
a2fce50455 Merge tag 'for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-ubi
ubi enhancements for 2020.01
- provide a way for skipping crc checks ported from linux, and add an
  U-Boot command to set this flag on already installed systems.
- fix redundand environment management
2019-10-17 07:26:16 -04:00
Stefan Roese
524acec47c ubi: Print skip_check in ubi_dump_vol_info()
It might be interesting, if "skip_check" is set or not, so lets print
this flag in ubi_dump_vol_info() as well.

hs: fix typo in commit message

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Quentin Schulz <quentin.schulz@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-10-16 05:42:27 +02:00
Quentin Schulz
386f20cade ubi: provide a way to skip CRC checks
Some users of static UBI volumes implement their own integrity check,
thus making the volume CRC check done at open time useless. For
instance, this is the case when one use the ubiblock + dm-verity +
squashfs combination, where dm-verity already checks integrity of the
block device but this time at the block granularity instead of verifying
the whole volume.

Skipping this test drastically improves the boot-time.

Adapted to U-Boot by Stefan Roese.

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Cc: Quentin Schulz <quentin.schulz@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
2019-10-16 05:42:27 +02:00
Patrick Delaunay
2a43dbdf96 dm: Tidy up dump output when there are many devices
At present the 'Index' column of 'dm tree' assumes there is
two digits, this patch increase it to 3 digits.

It also aligns output of 'dm uclass', assuming the same 3 digits index.

The boards with CONFIG_PINCTRL_FULL activated have one pinconfig
by pin configuration, so they can have more than 100 devices
pinconfig (for example with stm32mp157c-ev1 board we have
106 pinconfig node).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Patrick Delaunay
e878b53a79 dm: pinctrl: introduce PINCONF_RECURSIVE option
In the Linux pinctrl binding, the pin configuration nodes don't need to
be direct children of the pin controller device (may be grandchildren for
example). This behavior is managed with the pinconfig u-class which
recursively bind all the sub-node of the pin controller.

But for some binding (when pin configuration is only children of pin
controller) that is not necessary. U-Boot can save memory and reduce
the number of pinconf instance when this feature is deactivated
(for arch stm32mp for example for SPL).

This patch allows to control this feature with a new option
CONFIG_PINCONF_RECURSIVE when it is possible for each individual
pin controller device.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fixed CONFIG_IF_ENABLED() condition, added __maybe_unused:
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Anatolij Gustschin
52edfed65d dm: core: device: switch off power domain after device removal
The power domain associated with a device is enabled when probing,
but currently the domain remains enabled when the device is removed.
Some boards started to disable power domains for selected devices
via custom board_quiesce_devices(), but it doesn't work in many
cases, i. e. because devices still can be accessed later in
.remove() callback on behalf of dm_remove_devices_flags().

Utilize the DM core to power off the device power domain, but add a
device flag to be able to selectively let the power domain enabled
after device removal. This might be required for devices that must
remain enabled when booting OS, i. e. serial console for debug
output, etc.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Lokesh Vutla
0cf795a802 power: domain: Introduce dev_power_domain_off
Add dev_power_domain_off() api to disable all the power-domains
corresponding to a device

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Lokesh Vutla
af17b0dad5 remoteproc: k3_arm64: Enable DM_FLAG_DEFAULT_PD_CTRL_OFF
Enable DM_FLAG_DEFAULT_PD_CTRL_OFF for arm64 remote core so that
pd can be enabled after loading the image.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Lokesh Vutla
af94ad418d dm: core: Allow for not controlling the power-domain by DM framework
In some remoteproc cases, enabling the power domain of the core will
start running the core. In such cases image should be loaded before
enabling the power domain. But the current DM framework enables the
power-domain by default during probe. This is causing the remotecore
to start and crash as there is no valid image loaded.

In order to avoid this introduce a DM flag that doesn't allow for
enabling/disabling the power-domain by DM framework.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:03 -06:00
Michael Trimarchi
36a90eda84 dm: pinctrl: Skip not associated gpio phandle and rise a warning message
Skip not associated gpio phandle let register the other gpios on a group.
We need anyway to send out a warning to the user to fix their uboot-board.dtsi.
Thhe handle id can be found inside the decompiled dtb

dtc -I dtb -O dts -o devicetree.dts spl/u-boot-spl.dtb

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Peng Fan
f0cc4eae9a core: device: use dev_power_domain_on
When multiple power domains attached to a device, need power on
them all, so use dev_power_domain_on to do that.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-10-15 08:40:02 -06:00
Peng Fan
9c1e982218 power: domain: add dev_power_domain_on
Add this new API to power on multiple domains attached
to a device.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Changed to static inline and added a condition into C file:
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Thomas Fitzsimmons
640abba507 dm: spi: Do not assume first SPI bus
When CONFIG_OF_PRIOR_STAGE is enabled, this workaround was needed
before device_bind_common assigned request numbers sequentially in the
absence of aliases.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Thomas Fitzsimmons
7f3289bf6d dm: device: Request next sequence number
For CONFIG_OF_PRIOR_STAGE, in the absence of a device tree alias for a
given device, use the next request number for that type of device.
This allows aliases to be used when they're available, while still
allowing unaliased devices to be probed.

Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Kayla Theil
d8206ff198 tpm2: Don't assume active low reset value
The reset function sets the pin to 0 then 1 but if the pin is marked
ACTIVE_LOW in the DT it gets inverted and leaves the TPM in reset.
Let the gpio driver take care of the reset polarity.

Signed-off-by: Kayla Theil <kayla.theil@mixed-mode.de>
2019-10-15 08:40:02 -06:00
Patrick Delaunay
c20851b3d8 dm: pinctrl: introduce PINCONF_RECURSIVE option
In the Linux pinctrl binding, the pin configuration nodes don't need to
be direct children of the pin controller device (may be grandchildren for
example). This behavior is managed with the pinconfig u-class which
recursively bind all the sub-node of the pin controller.

But for some binding (when pin configuration is only children of pin
controller) that is not necessary. U-Boot can save memory and reduce
the number of pinconf instance when this feature is deactivated
(for arch stm32mp for example for SPL).

This patch allows to control this feature with a new option
CONFIG_PINCONF_RECURSIVE when it is possible for each individual
pin controller device.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-10-15 08:40:02 -06:00
Tom Rini
6f1f28b8e1 u-boot-imx-20191014
-------------------
 
 Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628
 
 	- logicpd pinmux
 	- i.MX7ULP: imx_ddr_size
 	- fixes Toradex i.MX6/i.MX7
 	- pico-imx7d
 	- tpc70 converted to DM
 	- New Board: meerkat96
 	- add HAB version command
 	- i.MX8 :
       		imx8: Jump from alias to OCRAM address at SPL init
       		imx8qm/qxp: Set SPL TEXT base to OCRAM base
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Merge tag 'u-boot-imx-20191014' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20191014
-------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628

	- logicpd pinmux
	- i.MX7ULP: imx_ddr_size
	- fixes Toradex i.MX6/i.MX7
	- pico-imx7d
	- tpc70 converted to DM
	- New Board: meerkat96
	- add HAB version command
	- i.MX8 :
      		imx8: Jump from alias to OCRAM address at SPL init
      		imx8qm/qxp: Set SPL TEXT base to OCRAM base
2019-10-14 13:00:51 -04:00
Tom Rini
cd5ffc5de5 - panel bridge support in stm32 ltdc
- DSI host uclass
 - sandbox DSI host uclass test driver and DSI host test
 - MIPI DSI helpers
 - Synopsys Designware MIPI DSI host bridge driver
 - STM32 DSI controller driver
 - OTM800A and RM68200 panel support
 - DSI host updates for stm32f769 and stm32mp1 dtsi files
 - splash screen for stm32f769 and stm32mp1 boards
 - stm32 defconfig updates for display support
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Merge tag 'video-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video

- panel bridge support in stm32 ltdc
- DSI host uclass
- sandbox DSI host uclass test driver and DSI host test
- MIPI DSI helpers
- Synopsys Designware MIPI DSI host bridge driver
- STM32 DSI controller driver
- OTM800A and RM68200 panel support
- DSI host updates for stm32f769 and stm32mp1 dtsi files
- splash screen for stm32f769 and stm32mp1 boards
- stm32 defconfig updates for display support
2019-10-14 07:30:16 -04:00