Commit graph

538 commits

Author SHA1 Message Date
Tom Rini
65cc0e2a65 global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
Tom Rini
aa6e94deab global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_SDRAM
namespace do not easily transition to Kconfig. In many cases they likely
should come from the device tree instead. Move these out of CONFIG
namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:07 -05:00
Tom Rini
6cc04547cb global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-11-10 10:08:55 -05:00
Tom Rini
5155207ae1 global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-11-10 10:08:55 -05:00
Bin Meng
ea253ad7b5 treewide: Remove the unnecessary space before semicolon
%s/return ;/return;

Signed-off-by: Bin Meng <bmeng@tinylab.org>
2022-11-02 13:58:17 -04:00
Rasmus Villemoes
c9473b2c37 imx8m: fix reading of DDR4 MR registers [again]
Commit 290ffe5788 (imx8m: fix reading of DDR4 MR registers) lifted a
private definition of lpddr4_mr_read() from imx8mm-cl-iot-gate board
code to drivers/ddr/imx/imx8m/ddrphy_utils.c, because that version
actually seems to work in practice.

However, commit 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
reintroduced the broken version in drivers/ddr/imx/imx8m/ddr_init.c,
copied most of the rest of ddrphy_utils.c to
drivers/ddr/imx/phy/ddrphy_utils.c, and stopped building
drivers/ddr/imx/imx8m/ddrphy_utils.c [and that file was then finally
completely removed with 7e9bd84883 (imx8m: ddrphy_utils: Remove unused
file)].

I assume this must have broken the imx8mm-cl-iot-gate board, at least
those that have not had their eeprom programmed with the proper
information. It certainly did break our out-of-tree board which always
reads back the ID register and uses that for a sanity check.

So apply the fix from 290ffe5788 once again.

Fixes: 99c7cc58e1 (ddr: imx: Add i.MX9 DDR controller driver)
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-10-24 11:34:33 +02:00
Pali Rohár
a86e294f9f ddr: fsl: Fix re-align of verbose DRAM information for non-SPL builds
During init_dram() is called also compute_lowest_common_dimm_parameters()
function which prints multi-line detailed output. So print also re-aligning
filler after "Detected ?DIMM" line to have "DRAM:  " output aligned.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Pali Rohár
2721997654 ddr: fsl: Allow to detect 4 GB DDR modules in 32-bit mode
U-Boot core code already handles the case when RAM size is bigger than
CONFIG_MAX_MEM_MAPPED. So there is no need to do duplicate check in fsl ddr
driver for CONFIG_MAX_MEM_MAPPED. Instead simplify code to just check if
RAM size can be representable in phys_size_t type. And avoid printing
warning if phys_size_t is just 1 byte smaller than RAM size, which is the
typical situation with 4 GB DDR module.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Pali Rohár
922460be0b ddr: fsl: Fix fsl_ddr_sdram_size() for 4GB modules with 32-bit phys_size_t
Function fsl_ddr_compute() always return size in unsigned long long type,
but function fsl_ddr_sdram_size() returns size in phys_size_t type.

When 36-bit addressing mode is not enabled then phys_size_t type is only
32-bit and thus it cannot store value 4GB (0x100000000). Function
fsl_ddr_sdram_size() in this case returns truncated value 0x0.

Fix this issue by returning the highest representable value, which is
0xffffffff (4GB - 1 byte).

This change fixes crashing of proper U-Boot because it detected 4 GB module
as RAM with zero size.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Pali Rohár
cf4eba4eb6 ddr: fsl: Fix checking for maximal mappable memory
Check needs to be done against CONFIG_MAX_MEM_MAPPED macro and not fixed
size 4GB (as CONFIG_MAX_MEM_MAPPED can be lower and for example for e500
cores it is just 2GB). Also fix printf re-align, which should be applied
only for non-SPL builds, during init_dram() call.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-09-23 15:13:18 -04:00
Tom Rini
e9a1ff9724 Merge branch 'master' into next
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-09-19 16:07:12 -04:00
Marek Vasut
7e9bd84883 imx8m: ddrphy_utils: Remove unused file
The ddrphy_utils.c is now deduplicated in drivers/ddr/imx/phy/ddrphy_utils.c ,
this drivers/ddr/imx/imx8m/ddrphy_utils.c is a remnant from when the
deduplication was implemented and was not removed. Remove it as it is
unused.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-09-18 22:56:10 +02:00
Stefan Roese
29caf9305b cyclic: Use schedule() instead of WATCHDOG_RESET()
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
2022-09-18 10:26:33 +02:00
Sean Anderson
6f6fbb334c ddr: fsl: Make bank_addr_bits reflect actual bits
In both the Freescale DDR controller and the SPD spec, bank address bits
are stored as the number of bank address bits minus 2. For example, if a
chip had 8 banks (3 total bank address bits), the value of
bank_addr_bits would be 1. This is rather surprising for users
configuring their memory manually, since they can't set bank_addr_bits
to the actual number of bank address bits. Rectify this.

There is at least one example of this kind of mistake already, in
board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank
address bits, but bank_addr_bits was set to 2, implying 4 bank address
bits. Such a value is reserved in BA_BITS_CS, but I suspect the
controller simply ignores the top bit, making this kind of mistake
harmless, if misleading.

Fixes: e8a7f1c32b ("powerpc/t1023rdb: Add T1023 RDB board support")
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-09-06 09:28:46 +08:00
Sean Anderson
96624d7b47 ddr: fsl: Reduce the size of interactive options
The interactive mode uses large several tables of options which can be
configured. However, much of the contents of these tables are
repetetive. For example, no struct is larger than half a kilobyte, so
the offset only takes up 9 bits. Similarly, the size is only ever 4 or
8, and printhex is a boolean. Reduce the size of these fields. This
reduces the size of the options tables by around 10 KiB. However, the
largest contributor to the size of the options tables is the use of a
pointer for the strings. A better approach would be to use a separate
array of strings, and store an integer index in the options tables.
However, this would require a large re-architecting of this file.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-09-06 09:28:45 +08:00
Tom Rini
d0748898d8 Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
   CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS

And we remove the entries from the README for a number of already
converted items.

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-12 16:10:49 -04:00
Simon Glass
4e4bf9449b common: Drop display_options.h from common header
Move this out of the common header and include it only where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-08-10 13:46:55 -04:00
Tom Rini
78475d2572 Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_INTLV_256B

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-08-04 16:18:48 -04:00
Peng Fan
23387416da ddr: imx8m: helper: load ddr firmware according to binman symbols
By reading binman symbols, we no need hard coded IMEM_LEN/DMEM_LEN after
we update the binman dtsi to drop 0x8000/0x4000 length for the firmware.

And that could save binary size for many KBs.

Tested-by: Tim Harvey <tharvey@gateworks.com> #imx8m[m,n,p]-venice
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
[Alper: Check BINMAN_SYMS_OK instead]
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-07-26 11:29:02 +02:00
Ye Li
5f77e669df ddr: imx9: enable Performance monitor counter
Add Kconfig for enabling reference events counter in DDRC performance
monitor by default

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Ye Li
99c7cc58e1 ddr: imx: Add i.MX9 DDR controller driver
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.

The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-07-26 11:29:01 +02:00
Tom Rini
c24e8e2bb3 Convert CONFIG_SYS_DDR_RAW_TIMING to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_DDR_RAW_TIMING

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
bca4509d57 Convert CONFIG_SYS_SPD_BUS_NUM to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_SPD_BUS_NUM

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
140f0aa0de nxp: Cleanup some emulator related options.
- Drop the emulator CONFIG test from include/configs/ls1088ardb.h
- Migrate CONFIG_SYS_FSL_DDR_EMU to a select'able option in
  drivers/ddr/fsl/Kconfig

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-07-05 17:03:01 -04:00
Tom Rini
52af0101be Merge branch 'master' into next
Merge in v2022.07-rc5.
2022-06-20 14:40:59 -04:00
Dinesh Maniyam
32e0379143 ddr: altera: soc64: Integer fix overflow that caused DDR size mismatched
Convert the constant integer to 'phys_size_t' to avoid overflow
when calculating the SDRAM size.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-17 16:27:05 +08:00
Tien Fong Chee
39bbcc341b ddr: altera: Stratix10: Use phys_size_t for memory size
Replace with phys_size_t for all memory size variables declaration
for the sake of scalability. phys_size_t is defined in
/arch/arm/include/asm/types.h.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:10:58 +08:00
Tien Fong Chee
ee06c5390f ddr: altera: Ignore bit[7-4] for both seq2core & core2seq handshake in HPS
Bit[7-4] for both register seq2core and core2seq handshake in HPS are not
required for triggering DDR re-calibration or resetting EMIF. So, ignoring
these bits just for playing it safe.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-16 16:10:44 +08:00
Tien Fong Chee
166e5b82a3 intel: n5x: ddr: update license
All the source code of sdram_n5x.c are from Intel, update the license to
use both GPL2.0 and BSD-3 Clause because this copy of code may used for
open source and internal project.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2022-06-15 17:48:22 +08:00
Tom Rini
90f0819a31 Convert CONFIG_SPL_COMMON_INIT_DDR to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_COMMON_INIT_DDR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-06-06 12:09:12 -04:00
Rasmus Villemoes
290ffe5788 imx8m: fix reading of DDR4 MR registers
I was trying to employ lpddr4_mr_read() to something similar to what
the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM
type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c
differs from the private one used by that board in how it extracts the
byte value, and I was only getting zeroes. Adding a bit of debug
printf'ing gives me

 tmp = 0x00ffff00
 tmp = 0x00070700
 tmp = 0x00000000
 tmp = 0x00101000

and indeed I was expecting a (combined) value of 0xff070010 (0xff
being Manufacturer ID for Micron). I can't find any documentation that
says how the values are supposed to be read, but clearly the iot-gate
definition is the right one, both for its use case as well as my
imx8mp-based board.

So lift the private definition of lpddr4_mr_read() from the
imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration
in the ddr.h header where e.g. get_trained_CDD() is already declared.

This has only been compile-tested for the imx8mm-cl-iot-gate
board (since I don't have the hardware), but since I've merely moved
its definition of lpddr4_mr_read(), I'd be surprised if it changed
anything for that board.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-05-20 09:30:28 +02:00
Pali Rohár
78cdaf4053 ddr: fsl: Allow to compile it without env support
When env support is disabled then usage of env_get_f() generates linker
errors. So do not compile env_get_f() when env support is disabled (for
example when disabled only in SPL).

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-04-26 17:18:39 +05:30
Marek Vasut
b8a24e07b2 imx8m: ddrphy_utils: Add 3732 MT/s mode
Add entry for 3732 MT/s mode of operation of the LPDDR4, in
which case the DDR PLL has to be configured in 933 MHz mode.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-04-12 15:36:17 +02:00
Tom Rini
388de0fa8b Convert CONFIG_DIMM_SLOTS_PER_CTLR to Kconfig
This converts the following to Kconfig:
   CONFIG_DIMM_SLOTS_PER_CTLR

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-04-08 10:46:22 -04:00
Tom Rini
225aaacf36 db-mv784mp-gp: Rename CONFIG_DB_784MP_GP to CONFIG_TARGET_DB_MV784MP_GP
The value CONFIG_DB_784MP_GP is only used in the DDR code to refer to
CONFIG_TARGET_DB_MV784MP_GP so just use that second value directly.

Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-04-01 10:28:47 -04:00
Tom Rini
f9147d636c Convert CONFIG_CHIP_SELECTS_PER_CTRL to Kconfig
This converts the following to Kconfig:
   CONFIG_CHIP_SELECTS_PER_CTRL

Cc: Alison Wang <alison.wang@nxp.com>
Cc: Pramod Kumar <pramod.kumar_1@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Vladimir Oltean <olteanv@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-03-03 16:51:20 -05:00
Marek Behún
a163db9fba ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT decision
In commit 3fc92a215b ("ddr: marvell: a38x: fix SPLIT_OUT_MIX state
decision") I ported a cleaned up and changed version of patch
  mv_ddr: a380: fix SPLIT_OUT_MIX state decision

In the port we removed checking for BYTE_HOMOGENEOUS_SPLIT_OUT bit,
because:
- the fix seemed to work without it
- the bit was checked for only at one place out of two, while the second
  bit, BYTE_SPLIT_OUT_MIX, was checked for in both cases
- without the removal it didn't work on Allied Telesis' x530 board

We recently had a chance to test on more boards, and it seems that the
change needs to be opposite: instead of removing the check for
BYTE_HOMOGENEOUS_SPLIT_OUT from the first if() statement, the check
needs to be added also to the second one - it needs to be at both
places.

With this change all the Turris Omnia boards I have had available to
test seem to work, I didn't encounter not even one failed DDR training.

As last time, I am noting that I do not understand what this code is
actually doing, I haven't studied the DDR training algorithm and
I suspect that no one will be able to explain it to U-Boot contributors,
so we are left with this blind poking in the code with testing whether
it works on several boards and hoping it doesn't break anything for
anyone :-(.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-02-17 14:17:07 +01:00
Ye Li
01aa4cd8ba imx8ulp: ddr: Fix DDR frequency request issue
After acking the requested frequency, should wait the ack bit clear
by DDR controller and check the DFS interrupt for next request polling.
Otherwise, the next polling of request bit will get previous value
that DDR controller have not cleared it, so a wrong request frequency
is used.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Jacky Bai
b80ec768a3 imx8ulp:ddr: saving the dram config timing data into sram
On i.MX8ULP, The dram config timing need to be saved into sram for
ddr retention when APD enter PD mode, so add this support on i.MX8ULP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Marek Behún
3fc92a215b ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision
This is a cleaned up and fixed version of a patch
  mv_ddr: a380: fix SPLIT_OUT_MIX state decision

  in each pattern cycle the bus state can be changed
  in order to avoide it, need to back to the same bus state on each
  pattern cycle
by
  Moti Boskula <motib@marvell.com>

The original patch is not in Marvell's mv-ddr-marvell repository. It was
gives to us by Marvell to fix an issues with DDR training on some
boards, but it cannot be applied as is to mv-ddr-marvell, because it is
a very dirty draft patch that would certainly break other things, mainly
DDR4 training code in mv-ddr-marvell, since it changes common functions.

I have cleaned up the patch and removed stuff that seemed unnecessary
(when removed, it still fixed things). Note that I don't understand
completely what the code does exactly, since I haven't studied the DDR
training code extensively (and I suspect that no one besides some few
people in Marvell understand the code completely).

Anyway after the cleanup the patch still fixes isssues with DDR training
on the failing boards.

There was also a problem with the original patch on some of the Allied
Telesis' x530 boards, reported by Chris Packham. I have asked Chris to
send me some logs, and managed to fix it:
- if you look at the change, you'll notice that it introduces
  subtraction of cur_start_win[] and cur_end_win[] members, depending on
  a bit set in the current_byte_status variable
- the original patch subtracted cur_start_win[] if either
  BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
  subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
  was set
- from Chris Packham logs I discovered that the x530 board where the
  original patch introduced DDR training failure, only the
  BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
  patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
  current_byte_status variable
- this led me to the hypothesis that both cur_start_win[] and
  cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
  set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
- this hypothesis also gains credibility when considering the commit
  title ("fix SPLIT_OUT_MIX state decision")

Hopefully this will fix things without breaking anything else.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
2022-01-14 11:39:15 +01:00
Marek Behún
eadc4f512f ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode determination
Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
mode"), Asynchornous Mode was only used when the CPU Subsystem Clock
Options[4:0] field in the SAR1 register was set to value 0x13: CPU at
2 GHz and DDR at 933 MHz.

Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
mode") added support for Asynchornous Modes with frequencies other than
933 MHz (but at least 467 MHz), but the code it added to check for
whether Asynchornous Mode should be used is wrong: it checks whether the
frequency setting in board DDR topology map is set to value other than
MV_DDR_FREQ_SAR.

Thus boards which define a specific value, greater than 400 MHz, for DDR
frequency in their board topology (e.g. Turris Omnia defines
MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that
commit.

The A38x Functional Specification, section 10.12 DRAM Clocking, says:
  In Synchornous mode, the DRAM and CPU clocks are edge aligned and run
  in 1:2 or 1:3 CPU to DRAM frequency ratios.

Change the check for whether Asynchornous Mode should be used according
to this explanation in Functional Specification.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 07:47:57 +01:00
Vagrant Cascadian
0776c5fbb7 drivers/ddr/altera/sequencer.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Stefan Roese
0cbd3d8121 arm: mvebu: axp: ddr: Switch to using DM I2C API
No functional change intended. This patch switches from the legacy I2C
API to the DM I2C API, so that this code can be used with DM I2C
enabled.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Stefan Roese
622882893d arm: mvebu: axp: Remove unreferenced ddr3_get_eprom_fabric() function
This function is not referenced in mainline U-Boot. Let's remove now.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Tom Rini
c7fad78ec0 Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_BR0_PRELIM
   CONFIG_SYS_OR1_PRELIM
   CONFIG_SYS_BR1_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR2_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR3_PRELIM
   CONFIG_SYS_OR3_PRELIM
   CONFIG_SYS_BR4_PRELIM
   CONFIG_SYS_OR4_PRELIM
   CONFIG_SYS_BR5_PRELIM
   CONFIG_SYS_OR5_PRELIM
   CONFIG_SYS_BR6_PRELIM
   CONFIG_SYS_OR6_PRELIM
   CONFIG_SYS_BR7_PRELIM
   CONFIG_SYS_OR7_PRELIM

This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms
that can set these values do so.  Add the relevant SYS_BRx_PRELIM_BOOL
to platforms that had not been previously migrated.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-01 10:58:10 -05:00
Maninder Singh
38ce95a1c6 drivers: ddr: lc_common_dimm_params.c : Fix Divison by zero issue
Adds check for memory clock variable before calculating caslat_actual.

Set mclk_ps to slowest DIMM supported if mclk_ps is found zero.

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Priyanka Singh
71b255b657 drivers: ddr: main.c: Fix Bad Shift operator issue
Fix Bad Shift operator issue in step_to_string function
by adding an if check

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Priyanka Singh
f5a37b02b0 drivers: ddr: fsl_ddr_gen4.c: Fix divide by zero issue
Fix possible divide by zero issue in fsl_ddr_set_memctl_regs
by adding an if check

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Priyanka Singh
a1932ece70 drivers: ddr: util.c: Fix divide by zero issue
Fix possible divide by zero issue in get_memory_clk_period_ps
by adding a check

Signed-off-by: Priyanka Singh <priyanka.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Wolfgang Denk
0cf207ec01 WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 09:08:16 -04:00