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Convert CONFIG_SPL_COMMON_INIT_DDR to Kconfig

Browse source 
This converts the following to Kconfig:
   CONFIG_SPL_COMMON_INIT_DDR

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-05-21 14:44:28 -04:00
parent 6074a536d5
commit 90f0819a31
47 changed files with 61 additions and 28 deletions
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4
README
View file

@ -1712,10 +1712,6 @@ The following options need to be configured:
Support for a lightweight UBI (fastmap) scanner and
loader
CONFIG_SPL_COMMON_INIT_DDR
Set for common ddr init with serial presence detect in
SPL binary.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,

3
board/freescale/p1010rdb/tlb.c
View file

@ -72,8 +72,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_1M, 1),
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),

3
board/freescale/p1_p2_rdb_pc/tlb.c
View file

@ -77,8 +77,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 7, BOOKE_PAGESZ_1M, 1),
#endif
#if defined(CONFIG_SYS_RAMBOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,

1
configs/P1010RDB-PA_36BIT_NAND_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

2
configs/P1010RDB-PA_36BIT_NOR_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -89,3 +90,4 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1010RDB-PA_NAND_defconfig
View file

@ -67,6 +67,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

2
configs/P1010RDB-PA_NOR_defconfig
View file

@ -48,6 +48,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -87,3 +88,4 @@ CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P1010RDB-PA_SDCARD_defconfig
View file

@ -59,6 +59,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1010RDB-PA_SPIFLASH_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1010RDB-PB_36BIT_NAND_defconfig
View file

@ -69,6 +69,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

2
configs/P1010RDB-PB_36BIT_NOR_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -91,3 +92,4 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_ADDR_MAP=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View file

@ -64,6 +64,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1010RDB-PB_NAND_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

2
configs/P1010RDB-PB_NOR_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -89,3 +90,4 @@ CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P1010RDB-PB_SDCARD_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1010RDB-PB_SPIFLASH_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1020RDB-PC_36BIT_NAND_defconfig
View file

@ -78,6 +78,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

1
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -69,6 +69,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

2
configs/P1020RDB-PC_36BIT_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -101,3 +102,4 @@ CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P1020RDB-PC_NAND_defconfig
View file

@ -77,6 +77,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

1
configs/P1020RDB-PC_SDCARD_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1020RDB-PC_SPIFLASH_defconfig
View file

@ -71,6 +71,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

2
configs/P1020RDB-PC_defconfig
View file

@ -57,6 +57,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -99,3 +100,4 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P1020RDB-PD_NAND_defconfig
View file

@ -80,6 +80,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

1
configs/P1020RDB-PD_SDCARD_defconfig
View file

@ -71,6 +71,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P1020RDB-PD_SPIFLASH_defconfig
View file

@ -74,6 +74,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

2
configs/P1020RDB-PD_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -103,3 +104,4 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P2020RDB-PC_36BIT_NAND_defconfig
View file

@ -82,6 +82,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

1
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -73,6 +73,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -76,6 +76,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

2
configs/P2020RDB-PC_36BIT_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -106,3 +107,4 @@ CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_COMMON_INIT_DDR=y

1
configs/P2020RDB-PC_NAND_defconfig
View file

@ -81,6 +81,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_TPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

1
configs/P2020RDB-PC_SDCARD_defconfig
View file

@ -72,6 +72,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/P2020RDB-PC_SPIFLASH_defconfig
View file

@ -75,6 +75,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

2
configs/P2020RDB-PC_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_SPL_COMMON_INIT_DDR=y
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
@ -104,3 +105,4 @@ CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_FSL=y
CONFIG_USB_STORAGE=y
CONFIG_COMMON_INIT_DDR=y

14
drivers/ddr/fsl/Kconfig
View file

@ -263,6 +263,20 @@ config SYS_OR7_PRELIM
depends on SYS_BR7_PRELIM_BOOL
endmenu
if TARGET_P1010RDB_PA || TARGET_P1010RDB_PB || TARGET_P1020RDB_PC || \
TARGET_P1020RDB_PD || TARGET_P2020RDB
config COMMON_INIT_DDR
bool "Do not have a TLB entry to cover common DDR init with serial presence detect (SPD)"
config SPL_COMMON_INIT_DDR
bool "Do not have a TLB entry to cover common DDR init with SPD in SPL"
config TPL_COMMON_INIT_DDR
bool "Do not have a TLB entry to cover common DDR init with SPD in TPL"
endif
config SYS_FSL_ERRATUM_A008378
bool

7
include/configs/P1010RDB.h
View file

@ -22,9 +22,6 @@
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#endif
#ifdef CONFIG_SPIFLASH
@ -39,9 +36,6 @@
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#endif
#endif
@ -57,7 +51,6 @@
#else
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)

1
include/configs/T102xRDB.h
View file

@ -23,7 +23,6 @@
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#define CONFIG_SPL_COMMON_INIT_DDR
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)

1
include/configs/T104xRDB.h
View file

@ -15,7 +15,6 @@
#include <asm/config_mpc85xx.h>
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SPL_COMMON_INIT_DDR
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000

1
include/configs/T208xQDS.h
View file

@ -31,7 +31,6 @@
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#define CONFIG_SPL_COMMON_INIT_DDR
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)

1
include/configs/T208xRDB.h
View file

@ -26,7 +26,6 @@
#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET 0x27FFC
#define BOOT_PAGE_OFFSET 0x27000
#define CONFIG_SPL_COMMON_INIT_DDR
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)

2
include/configs/T4240RDB.h
View file

@ -36,8 +36,6 @@
#endif
#endif
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#endif /* CONFIG_RAMBOOT_PBL */

7
include/configs/p1_p2_rdb_pc.h
View file

@ -83,9 +83,6 @@
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#elif defined(CONFIG_SPIFLASH)
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
@ -94,13 +91,9 @@
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)