Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-24 21:54:01 +00:00
Code Issues Projects Releases Packages Wiki Activity

Convert CONFIG_DIMM_SLOTS_PER_CTLR to Kconfig

Browse source 
This converts the following to Kconfig:
   CONFIG_DIMM_SLOTS_PER_CTLR

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-03-30 18:07:31 -04:00
parent bef12ea4a3
commit 388de0fa8b
65 changed files with 35 additions and 49 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
configs/T2080QDS_NAND_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

1
configs/T2080QDS_SDCARD_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

1
configs/T2080QDS_SECURE_BOOT_defconfig
View file

@ -46,6 +46,7 @@ CONFIG_ETHPRIME="FM1@DTSEC3"
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

1
configs/T2080QDS_SPIFLASH_defconfig
View file

@ -64,6 +64,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

1
configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

1
configs/T2080QDS_defconfig
View file

@ -47,6 +47,7 @@ CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_DM_I2C=y

1
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_SATA=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
# CONFIG_DDR_SPD is not set
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls1028aqds_tfa_defconfig
View file

@ -55,6 +55,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls1028aqds_tfa_lpuart_defconfig
View file

@ -54,6 +54,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
# CONFIG_DDR_SPD is not set
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls2080aqds_SECURE_BOOT_defconfig
View file

@ -46,6 +46,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2080aqds_defconfig
View file

@ -49,6 +49,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2080aqds_nand_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2080aqds_qspi_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2080aqds_sdcard_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2080ardb_SECURE_BOOT_defconfig
View file

@ -50,6 +50,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2080ardb_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2080ardb_nand_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2081ardb_defconfig
View file

@ -52,6 +52,7 @@ CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y

1
configs/ls2088aqds_tfa_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
View file

@ -48,6 +48,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls2088ardb_qspi_defconfig
View file

@ -55,6 +55,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
View file

@ -53,6 +53,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/ls2088ardb_tfa_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2160aqds_tfa_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
View file

@ -54,6 +54,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2160ardb_tfa_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2160ardb_tfa_stmm_defconfig
View file

@ -62,6 +62,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
View file

@ -58,6 +58,7 @@ CONFIG_DM=y
CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2162aqds_tfa_defconfig
View file

@ -65,6 +65,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

1
configs/lx2162aqds_tfa_verified_boot_defconfig
View file

@ -66,6 +66,7 @@ CONFIG_SATA=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_MPC8XXX_GPIO=y

4
drivers/ddr/fsl/Kconfig
View file

@ -53,6 +53,10 @@ config CHIP_SELECTS_PER_CTRL
int "Number of chip selects per controller"
default 4
config DIMM_SLOTS_PER_CTLR
int "Number of DIMM slots per controller"
default 1
config SYS_FSL_DDR_VER
int
default 50 if SYS_FSL_DDR_VER_50

2
include/configs/MPC8548CDS.h
View file

@ -47,8 +47,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */

2
include/configs/P1010RDB.h
View file

@ -161,8 +161,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* DDR3 Controller Settings */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302

2
include/configs/P2041RDB.h
View file

@ -91,8 +91,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x52
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */

1
include/configs/T102xRDB.h
View file

@ -145,7 +145,6 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#if defined(CONFIG_TARGET_T1024RDB)
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51

2
include/configs/T104xRDB.h
View file

@ -127,8 +127,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51

1
include/configs/T208xQDS.h
View file

@ -116,7 +116,6 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51

1
include/configs/T208xRDB.h
View file

@ -111,7 +111,6 @@
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPD_BUS_NUM 0
#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1 0x51

2
include/configs/T4240RDB.h
View file

@ -92,8 +92,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/*
* IFC Definitions
*/

2
include/configs/corenet_ds.h
View file

@ -94,8 +94,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS1 0x51
#define SPD_EEPROM_ADDRESS2 0x52

2
include/configs/km/pg-wcom-ls102xa.h
View file

@ -22,8 +22,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54

2
include/configs/kmcent2.h
View file

@ -173,8 +173,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x54
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */

1
include/configs/kontron_sl28.h
View file

@ -19,7 +19,6 @@
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define CONFIG_VERY_BIG_RAM
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

1
include/configs/ls1012a2g5rdb.h
View file

@ -9,7 +9,6 @@
#include "ls1012a_common.h"
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/* SATA */

1
include/configs/ls1012afrdm.h
View file

@ -9,7 +9,6 @@
#include "ls1012a_common.h"
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifndef CONFIG_SPL_BUILD

1
include/configs/ls1012afrwy.h
View file

@ -13,7 +13,6 @@
#define BOARD_REV_C 0x00080000
#define BOARD_REV_MASK 0x001A0000
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define SYS_SDRAM_SIZE_512 0x20000000
#define SYS_SDRAM_SIZE_1024 0x40000000

1
include/configs/ls1012aqds.h
View file

@ -10,7 +10,6 @@
#include "ls1012a_common.h"
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/*

1
include/configs/ls1012ardb.h
View file

@ -10,7 +10,6 @@
#include "ls1012a_common.h"
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_SDRAM_SIZE 0x40000000
/*

1
include/configs/ls1021aqds.h
View file

@ -49,7 +49,6 @@
#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_DDR_RAW_TIMING
#endif
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

3
include/configs/ls1028aqds.h
View file

@ -10,9 +10,6 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk() / 4)
/* DDR */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_QIXIS_I2C_ACCESS
/*

2
include/configs/ls1028ardb.h
View file

@ -14,8 +14,6 @@
/* Store environment at top of flash */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_QIXIS_I2C_ACCESS
/*

1
include/configs/ls1043aqds.h
View file

@ -10,7 +10,6 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51

1
include/configs/ls1043ardb.h
View file

@ -10,7 +10,6 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define CONFIG_SYS_SPD_BUS_NUM 0

2
include/configs/ls1046afrwy.h
View file

@ -10,8 +10,6 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_UBOOT_BASE 0x40100000
/*

1
include/configs/ls1046aqds.h
View file

@ -10,7 +10,6 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51

1
include/configs/ls1046ardb.h
View file

@ -11,7 +11,6 @@
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define SPD_EEPROM_ADDRESS 0x51

2
include/configs/ls1088aqds.h
View file

@ -18,8 +18,6 @@
#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0

1
include/configs/ls1088ardb.h
View file

@ -26,7 +26,6 @@
#endif
#define SPD_EEPROM_ADDRESS 0x51
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)

1
include/configs/ls2080aqds.h
View file

@ -26,7 +26,6 @@
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif

1
include/configs/ls2080ardb.h
View file

@ -36,7 +36,6 @@
#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
#endif

1
include/configs/lx2160a_common.h
View file

@ -33,7 +33,6 @@
#define SPD_EEPROM_ADDRESS6 0x56
#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
/* Miscellaneous configurable options */

2
include/configs/p1_p2_rdb_pc.h
View file

@ -158,8 +158,6 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Default settings for DDR3 */
#ifndef CONFIG_TARGET_P2020RDB
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f

2
include/configs/socrates.h
View file

@ -59,8 +59,6 @@
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */

2
include/configs/ten64.h
View file

@ -11,8 +11,6 @@
#define COUNTER_FREQUENCY 25000000 /* 25MHz */
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd"