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Convert CONFIG_SYS_FSL_DDR_INTLV_256B to Kconfig

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This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_INTLV_256B

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-07-23 13:05:12 -04:00
parent 7da6a9e7df
commit 78475d2572
26 changed files with 29 additions and 8 deletions
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5
README
View file

@ -413,11 +413,6 @@ The following options need to be configured:
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.
CONFIG_SYS_FSL_DDR_INTLV_256B
DDR controller interleaving on 256-byte. This is a special
interleaving mode, handled by Dickens for Freescale layerscape
SoCs with ARM core.
CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
Number of controllers used as main memory.

1
configs/ls2080aqds_SECURE_BOOT_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y

1
configs/ls2080aqds_defconfig
View file

@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y

1
configs/ls2080aqds_nand_defconfig
View file

@ -79,6 +79,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57

1
configs/ls2080aqds_qspi_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57

1
configs/ls2080aqds_sdcard_defconfig
View file

@ -74,6 +74,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57

1
configs/ls2080ardb_SECURE_BOOT_defconfig
View file

@ -60,6 +60,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y

1
configs/ls2080ardb_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y

1
configs/ls2080ardb_nand_defconfig
View file

@ -83,6 +83,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
CONFIG_FSL_ESDHC=y

1
configs/ls2081ardb_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x57

1
configs/ls2088aqds_tfa_defconfig
View file

@ -66,6 +66,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
View file

@ -56,6 +56,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y

1
configs/ls2088ardb_qspi_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_EARLY_INIT=y

1
configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/ls2088ardb_tfa_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_DDR_CLK_FREQ=133333333
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
View file

@ -61,6 +61,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2160aqds_tfa_defconfig
View file

@ -68,6 +68,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
View file

@ -59,6 +59,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2160ardb_tfa_defconfig
View file

@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2160ardb_tfa_stmm_defconfig
View file

@ -67,6 +67,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
View file

@ -63,6 +63,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2162aqds_tfa_defconfig
View file

@ -70,6 +70,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

1
configs/lx2162aqds_tfa_verified_boot_defconfig
View file

@ -71,6 +71,7 @@ CONFIG_DYNAMIC_DDR_CLK_FREQ=y
CONFIG_DIMM_SLOTS_PER_CTLR=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_FSL_DDR_INTLV_256B=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

7
drivers/ddr/fsl/Kconfig
View file

@ -182,6 +182,13 @@ config SYS_DDR_RAW_TIMING
timing parameters are extracted from datasheet and hard-coded into
header files or board specific files.
config SYS_FSL_DDR_INTLV_256B
bool "Enforce 256-byte interleave"
help
DDR controller interleaving on 256-byte. This is a special
interleaving mode, handled by Dickens for Freescale layerscape SoCs
with ARM core.
endif
menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"

2
include/configs/ls2080a_common.h
View file

@ -16,8 +16,6 @@
/* Link Definitions */
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0

1
include/configs/lx2160a_common.h
View file

@ -13,7 +13,6 @@
#define CONFIG_SYS_FLASH_BASE 0x20000000
/* DDR */
#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0