Commit graph

307 commits

Author SHA1 Message Date
Masahiro Yamada
0bd20207ab ARM: uniphier: disable cache in SPL of PH1-LD20
The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table.  Disable D-cache and MMU
before jumping to U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-26 00:35:26 +09:00
Robert P. J. Day
1cc0a9f496 Fix various typos, scattered over the code.
Spelling corrections for (among other things):

* environment
* override
* variable
* ftd (should be "fdt", for flattened device tree)
* embedded
* FTDI
* emulation
* controller
2016-05-05 21:39:26 -04:00
Masahiro Yamada
bef4b024e9 ARM: uniphier: move pin-mux code into pin_init function
The code in uniphier_sld3_sbc_init() is pin-muxing, so it would
be a better fit in uniphier_sld3_early_pin_init().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:13:45 +09:00
Masahiro Yamada
5eb4150e84 ARM: uniphier: allow to use System Bus for ROM boot mode of PH1-LD20
The System Bus is not available by default on the ROM boot mode of
PH1-LD20.  To use devices connected to the System Bus, such as the
Micro Support Card, it is necessary to set up pin-muxing and some
System Bus Controller register.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:09:18 +09:00
Masahiro Yamada
1dce5eb9de ARM: uniphier: enable Peripherl clock to use UART in SPL
This is needed to use UART on SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:09:17 +09:00
Masahiro Yamada
68340966e6 ARM: uniphier: fix boot mode table of PH1-LD20
PH1-LD20 does not have the dedicated boot swap select latch.
Instead, it is controlled from the boot mode select.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-05-01 01:09:11 +09:00
Masahiro Yamada
9d0c2ceb35 ARM: uniphier: add PH1-LD20 SoC support
This is the first ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24 09:54:08 +09:00
Masahiro Yamada
881aa5a79a ARM: uniphier: rework uniphier_set_fdt_file()
The current table look-up for the DTB file name turned out bothersome
in terms of maintainability; I ended up adding a new entry every time
a new board is supported.

There is a common pattern between the DT compatible string and the
corresponding file name; drop the vendor prefix "socionext," and
prefix it with "uniphier-" and suffix it with ".dtb".

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24 09:54:03 +09:00
Masahiro Yamada
d90b9745ea ARM: uniphier: carry on booting for Unknown boot mode
No need to stop booting U-Boot even if boot mode is unknown.
Setting the "bootmode" environment is only useful for booting
Linux Kernel.  Anyway, U-Boot has already booted by this point.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24 09:53:57 +09:00
Masahiro Yamada
612ccd9001 ARM: uniphier: add sg_set_iectrl_range()
For PH1-LD20 or later, per-pin input-enable control is supported,
that is, we need to set-up IECTRL registers for a group of pins.
This helper function will be useful for a bunch of register settings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24 09:53:57 +09:00
Masahiro Yamada
7b3a032dd3 ARM: uniphier: avoid unaligned access to DT on 64bit SoC
Because DT properties are 4-byte aligned, the pointer access
*(fdt64_t *) in this code causes unaligned access.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-24 09:53:55 +09:00
Hans de Goede
c09d29057a arm: Replace v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL) with asm code
v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788

While debugging this I learned that v7_maint_dcache_all() is unreliable
when build with gcc5 too when it is marked as noinline.

This commit fixes the reliability issues by replacing the C-code with
the ready to use asm implementation from the kernel.

Given that this code when written as C-code clearly is quite fragile
(also see the existing comments about the C-code being the way it is
 to get optimal assembly) and that we have a proven asm alternative,
I believe that this is the best solution.

Note that we actually already had a copy of the kernel's
v7_flush_dcache_all() before this commit in
arch/arm/mach-uniphier/arm32/lowlevel_init.S.

This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames
it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper
which saves / restores the clobbered registers for use from C-code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-11 20:48:26 -04:00
Masahiro Yamada
6797630685 cosmetic: Fix typos "privide"
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
5b66006646 ARM: uniphier: rename function names ph1_* to uniphier_*
Eliminate the "ph1"_ prefixes from function names because "uniphier_"
describes the SoC familiy better.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
a75ecfc2a6 ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
ac2a1030e3 ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64
Currently, these functions assume #address-cells and #size-cells are
both one.  Fix them to support 64bit DTB.

Also, I am fixing a buffer overrun bug while I am here.  The array
size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS.  The number of
iteration in the loop should be limited by that CONFIG.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-04-01 00:59:47 +09:00
Masahiro Yamada
cbbc2d80fc ARM: uniphier: add NOR boot support
This allows to boot from NOR flash (or SRAM) with help of an external
loader (NOR-loader).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:41 +09:00
Masahiro Yamada
d5cf32977f ARM: uniphier: support Debug UART
For ARM32 architecture, CONFIG_DEBUG_LL is available for early
low-level debugging (and actually UniPhier 32bit SoCs use it), but
ARM64 architecture does not support it.  Instead, CONFIG_DEBUG_UART
is available as an architecture-independent debug facility.

This commit supports it on all the UniPhier SoCs (including the new
ARMv8 SoCs), which is very useful for new SoC bringups.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:41 +09:00
Masahiro Yamada
650aedbfc0 ARM: uniphier: add System Control register macros for ARMv8 SoCs
The System Control block moved to a completely different register
map for ARMv8 SoCs, so it cannot be shared with the ARM 32-bit ones.
Define register macros in a new header file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:22 +09:00
Masahiro Yamada
c8cc7213a5 ARM: uniphier: add sg_set_iectrl() function
This helper function would be useful for new SoCs with per-pin
input enable controlling, such as PH1-LD20, PH1-LD11, etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:21 +09:00
Masahiro Yamada
f6c65bc2fa ARM: uniphier: enable DDR PHY parameter dump commands by default
These commands are not necessarily needed for usual operations
(they are useful in case of DDR memory trouble), but enabling them
by default would be nice in terms of the compilation test coverage.
They are small enough, so limited impact on the memory footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:20 +09:00
Masahiro Yamada
36223f5de8 ARM: uniphier: add work-around to support Micro Support Card v3.6.10
Due to some hardware guy's awful work, this version is not compatible
with v3.6: the logic of BIT(0) of the reset logic is inverted! (and
v3.6.10 is horribly wrong in multiple ways), but this is what we have
to solve now.

The v3.6 expects 0x0000 set to the register for reset de-assertion,
while v3.6 does 0x0001.

This commit (ab)uses another bug of v3.6.10 to work around the issue.
The UniPhier System Bus is a 16-bit bus, which this support card is
connected to.  A 32-bit write to the bus (writel() function call) is
divided into two 16-bit write transactions, with LSB the first.  What
is amazing for v3.6.10 is that access to address 4N + 2 goes to 4N
(Jesus Christ!).

For clarification, things are like this:

    writel(0x00010000, MICRO_SUPPORT_CARD_RESET);

is done with two bus transactions as follows

    [1] write 0x0000 to address MICRO_SUPPORT_CARD
    [2] write 0x0001 to address MICRO_SUPPORT_CARD + 2

For v3.6, [1] is written to the register and [2] is correctly ignored
because there is nothing at the address MICRO_SUPPORT_CARD + 2.  This
is what we expect.

For v3.6.10, [1] is written to the reset register and then [2] is
over-written to the same register due to the bus access bug.

For the latter, it produces a glitch signal to the BIT[0], so the
device state is lost due to the reset pulse.  This solution only
works for the start-up code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:19 +09:00
Masahiro Yamada
1b1f2319ca ARM: uniphier: drop ifdef in ddrphy-regs.h
The ifdef conditionals in header files prevent us from multi-SoC
support in a single U-Boot image.  Detect SoC specific parameters
run-time rather than define them statically with an ifdef in
ddrphy-regs.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:19 +09:00
Masahiro Yamada
5d0607c58c ARM: uniphier: refactor SBC init code
There is a bunch of duplication in the System Bus Controller init
code.  Roughly, there are two types in the SBC mode:  Adress/Data
Multiplex Mode and Save Pins Mode.  Consolidate per-SoC functions
into the two, plus per-SoC optional init code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:18 +09:00
Masahiro Yamada
ea65c98050 ARM: uniphier: drop PH1- prefix from CONFIG options and file names
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long.  It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family.  Also, rename files for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:42:13 +09:00
Masahiro Yamada
5d07648662 ARM: uniphier: allow debug_ll_init() to do nothing for unknown SoCs
This function should just return for unknown SoCs rather than writing
unexpected values to registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-09 01:11:15 +09:00
Masahiro Yamada
51244a6080 ARM: uniphier: fix build error when CONFIG_CMD_DDRMPHY_DUMP=y
The build fails if compiled with CONFIG_CMD_DDRMPHY_DUMP=y since commit
46abfcc99e ("ARM: uniphier: rework struct uniphier_board_data").

Fixes: 46abfcc99e ("ARM: uniphier: rework struct uniphier_board_data")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-09 01:10:47 +09:00
Masahiro Yamada
11d3ede42c ARM: uniphier: fix warnings reported by aarch64 compiler
The UniPhier SoC family has not supported ARMv8 yet, but these would
cause warnings if they were compiled with a 64bit compiler.  Before
adding the ARMv8 support really, fix them now.

Because UniPhier SoCs do not support Large Physical Address Extension,
casting "phys_addr_t" into "unsigned long" would carry the address
as is.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-01 00:33:29 +09:00
Masahiro Yamada
fe5ea57bdb ARM: uniphier: prepare directory structure for ARMv8 SoC support
Before adding ARMv8 support, this commit refactors the directory
structure.  Move ARMv7 specific files to arch/arm/mach-uniphier/arm32
to avoid a mess by mixture of ARMv7 and ARMv8 code.  Also move the
"select CPU_V7" to the lower-level menu because we will have to
select ARM64 instead of CPU_V7 for ARMv8 SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-01 00:33:24 +09:00
Masahiro Yamada
2247c332db ARM: uniphier: rename PH1-LD10/PH1-sLD11 to PH1-LD20/PH1-LD11
Due to the company's awful projecting, PH1-LD10 and PH1-sLD11 have
been renamed to PH1-LD20 and PH1-LD11, respectively.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
5fb87a1632 ARM: uniphier: rework UniPhier SoC select in Kconfig
The chains of "depends on <SoC_name>" in the current Kconfig is
clumsy.  The idea here is to allow users to choose a SoC group first
(SoC group consists of some SoCs that can coexist in one binary).
Then, allow to enable/disable each SoC support in the selected SoC
group.  This makes the Kconfig menu clearer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4e651003e5 ARM: uniphier: rename variable for DRAM controller base address
Rename the variable that contains the base address for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a191e0dee0 ARM: uniphier: deprecate umc_dram_init_{start, poll}
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
7c9cac9c22 ARM: uniphier: remove unused macros for UMC base addresses
These macros are no longer used.  These base addresses are
SoC-dependent, so they should not be placed in the header.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
fd14397e93 ARM: uniphier: rework DRAM size handling in UMC init code
Currently, DRAM size is converted twice:
  size in byte -> size in Gbit -> enum

Optimize the code by converting the "size in byte" into enum directly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
9a71844a38 ARM: uniphier: optimize PH1-Pro4 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
b870848795 ARM: uniphier: optimize PH1-LD4 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
c5985b4bbb ARM: uniphier: optimize PH1-sLD8 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
71d7ef35df ARM: uniphier: refactor UMC init code for PH1-LD4
Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
380a8cafc0 ARM: uniphier: support more DRAM use cases for PH1-sLD8
Support DDR3-1600 / 512MB DDR size.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
82e5950802 ARM: uniphier: refactor UMC init code for PH1-sLD8
Move frequency-dependent register settings to arrays for clean-up.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
6257a0b0e9 ARM: uniphier: refactor DDR-PHY init code
The if-else statements for the frequency-dependent register settings
seem clumsy.  Moving them to arrays would make it cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
7887670498 ARM: uniphier: remove unused argument of ph1_ld4_ddrphy_init()
The DDR PHY settings no longer depend on the DRAM size.  Drop the
argument from the init function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4f19f61184 ARM: uniphier: merge DDR PHY init code for 3 SoCs
Now these three are almost the same.  The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored.  (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
4021b4381d ARM: uniphier: add a field to specify DDR3+
Add a field to distinguish DDR3+ from (standard) DDR3.  It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).

Default DDR3 spec for each SoC:

  PH1-LD4, PH1-sLD8: DDR3+
  Others: DDR3

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
3c963d4899 ARM: uniphier: disable debug circuit clocks for PH1-Pro4
These settings control the clocks around the memory controller.
The debug ability is unneeded once it works properly.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
00dd3f6ab0 ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings
These settings were used only for the PH1-sLD3 and older SoCs.  The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
94b756f331 ARM: uniphier: refactor UMC init code for ProXstream2
Currently, a dummy value is defined for the UMC_SPCCTLA register
when the DRAM size is zero.  This seems weird because the controller
does not need setting in the first place if the size is zero.

Also, redefine enum dram_size to represent the DRAM size per 16-bit
unit.  This makes things simpler because the channel 0 and 1 are
connected with 32-bit width DRAM, while the channel 2 is connected
with 16-bit width one.

I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_*
for consistency) while I am here because SIZE_* might be easily
mixed-up with the macros in include/linux/sizes.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a54c879a42 ARM: uniphier: use pr_err() where possible
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
59fe23c2e0 ARM: uniphier: optimize ProXstream2 UMC init code with "for" loop
Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
46abfcc99e ARM: uniphier: rework struct uniphier_board_data
This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it.  It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
8353266825 ARM: uniphier: remove unused umc_polling()
This function is unused.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
aa8a93480e ARM: uniphier: default to environment in eMMC
Of the several boot devices supported, it looks like the eMMC is the
most commonly used.  Enable CONFIG_ENV_IS_IN_MMC by default.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
569e4be172 ARM: uniphier: add a command to find the first MMC (non-SD) device
UniPhier SoC family supports both (e)MMC boot and SD card boot;
however, both of them are handled in the same uclass.

When booting from the eMMC, we want to know the device number
of the (e)MMC, not SD.  This command is useful to find the first
MMC (non-SD) device.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a55d9feeec ARM: uniphier: add eMMC boot support
Export device nodes needed for eMMC boot (eMMC node, pinctrl, and
clock) to the SPL DTB.  CONFIG_SUPPORT_EMMC_BOOT is also necessary
to use "mmc partconf" command.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
3f23111722 ARM: uniphier: add support for PH1-Pro4 Ace and Sanji boards
Initial commit for PH1-Pro4 Ace and Sanji boards.

Note:
There are two variants for the Ace board in terms of the amount of
DDR memory; 1GB or 2GB.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
f775c09d00 ARM: uniphier: adjust DDR clock delay line for ProXstream2
It turned out that DDR channel 2 was not working on ProXstream2
Vodka board.  Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
c9552895a8 ARM: uniphier: move cmd_ddrmphy.c to fix build error
If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails.

Fixes: 93d92d46cd ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
126f9bad77 ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.c
The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram
to build these commands.

Fixes: 93d92d46cd ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
2851971b8f ARM: uniphier: remove unused header mio-regs.h
This header is no longer used.

This is the last file in arch/arm/mach-uniphier/include/mach/.
At last, I've succeeded in eliminating the mach directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
8034b5171f ARM: uniphier: drop unneeded EHCI pin mux settings
These pin mux settings are cared by the pinctrl drivers.
Remove the ad-hoc code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 17:07:46 +09:00
Masahiro Yamada
cd0847fe63 ARM: uniphier: switch over to generic EHCI driver
The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does
nothing special but set the base address and handle reset/clock.

Since commit 4feefdcfe9 ("usb: add clock support for generic EHCI"),
the generic one (drivers/usb/host/ehci-generic.c) can do those, too.

We no longer need to stick to the dedicated driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:51:07 +09:00
Masahiro Yamada
fec4816387 ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC
The USB boot code is too fat and complicated to be included in SPL
(at least for now).  So, it was implemented as a separate project
(what we call USB-loader).

The expected boot sequence is as follows:

  Boot ROM -> USB-loader -> SPL -> U-Boot proper

The USB-loader loads the SPL and U-Boot proper from a USB memory
onto the locked L2 cache.  Then, SPL needs to copy the U-Boot proper
to DRAM, so this mode looks like a NOR boot from the view of SPL.
However, we want to distinguish between (genuine) NOR boot and USB
boot in some places.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
a89be270e7 ARM: uniphier: add missing static qualifier
This function is for local use in the file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
4b50369fb5 ARM: uniphier: create early page table at run-time
UniPhier SoCs are not equipped with dedicated on-chip SRAM.  Instead,
locked outer cache is used as RAM area during the early boot stage
where DRAM is not ready yet.  This effectively means MMU must be
always enabled while we are in SPL.

Currently, the SPL image for UniPhier SoCs contains the page table
statically defined at compile time.  It has been a burden because the
16KB page table occupies a quarter memory footprint of the 64KB SPL
image.

Finally, there is no more room to implement new features in SPL.
Setting aside the NOR boot mode, this issue can be solved by creating
the page table onto RAM at run time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
755c7d9a61 ARM: uniphier: change stack pointer address for SPL
No special reason for the current stack address 0x0ff08000.
Change it to 0x00100000 to simplify the init_page_table.

There are two types of SoCs in terms of the load address of SPL.

 [1] PH1-sLD3, PH1-LD4, PH1-sLD8
   SPL is loaded at 0x00040000-0x0004ffff
 [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b
   SPL is loaded at 0x00100000-0x0010ffff

The new stack area (0x000f8000-0x00100000) should be safe for all the
cases.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
84a7562e49 ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boards
Some of PH1-Pro4 boards are equipped with larger amount of DRAM than
the reference board.  Add UMC settings to support them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-14 16:36:13 +09:00
Masahiro Yamada
048c61d674 ARM: uniphier: remove unneeded if conditionals
The if block does the same as the else block does.  The conditional
is not necessary at all.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-20 08:40:33 +09:00
Masahiro Yamada
faefef9994 ARM: uniphier: move UMC register macros to umc-regs.h
The umc-proxstream2.c defiens the same macros as in umc-regs.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-20 08:40:22 +09:00
Masahiro Yamada
d649fb8aef ARM: uniphier: set active ways to really enable outer cache
Each way must be unlocked to make it effective.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-20 08:40:11 +09:00
Masahiro Yamada
6d95778283 ARM: uniphier: fix range invalidate for outer cache
If invalidate operation is invoked against a cache-unaliged region,
the both ends of the region should be flushed, not invalidated.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-20 08:40:02 +09:00
Masahiro Yamada
5407735935 ARM: uniphier: factor out outer cache sync as a helper function
Avoid repeating the same code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-20 08:39:52 +09:00
Masahiro Yamada
cefca48ca7 ARM: uniphier: refactor outer cache operation slightly
Improve readability without changing the behavior.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-20 08:39:42 +09:00
Masahiro Yamada
93d92d46cd ARM: uniphier: add dump command for DDR Multi PHY registers
The ProXstream2/PH1-LD6b is integrated with a new IP for DDR PHY
which is not register-compatible with the former SoCs.
Add a new command to support the register dump of this IP.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-13 01:54:57 +09:00
Masahiro Yamada
15607d0d94 ARM: uniphier: add DRAM init code for ProXstream2/PH1-LD6b
As mentioned in the log of commit 019df879a9 (ARM: uniphier: add
ProXstream2 and PH1-LD6b support), the DRAM init code was missing
for a long time.  Finally, here it is.  SPL works now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-13 01:54:55 +09:00
Masahiro Yamada
107b3fb484 ARM: uniphier: move headers out of include/mach directory
These headers are only included locally in arch/arm/mach-uniphier/.
There is no reason to export them by putting in the mach/ directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-13 01:54:53 +09:00
Masahiro Yamada
042b28f436 ARM: uniphier: move cmd_pinmon.c to boot-mode subdirectory
This command shows the boot mode pins, so it would be more at home
in the boot-mode subdirectory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-13 01:54:51 +09:00
Masahiro Yamada
9ca6616426 ARM: uniphier: move cmd_ddrphy.c to dram subdirectory
This command shows the register dump of the DDR PHY, so it would be
more at home in the dram subdirectory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-13 01:54:45 +09:00
Masahiro Yamada
9475f8de88 ARM: uniphier: kill bogus header includes
These includes are not necessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-01-13 01:54:38 +09:00
Masahiro Yamada
8ea4f49a47 ARM: uniphier: set DTB file name to fdt_file environment
When we want to boot Linux with a DTB file downloaded from a TFTP
server or somewhere, we need to know the file name to be downloaded.

Assume the U-Boot configuration is shared among some similar boards.
If they are similar enough, the difference only appears in device
trees.  The build procedure would be like this:

 - Board A:  make foo_common_defconfig && make DEVICE_TREE=foo_board_a
 - Board B:  make foo_common_defconfig && make DEVICE_TREE=foo_board_b
 - Board C:  make foo_common_defconfig && make DEVICE_TREE=foo_board_c

In this case, the U-Boot image contains nothing about the DTB file name
it is running with.  (CONFIG_DEFAULT_DEVICE_TREE is not helpful for this
purpose because it is painful to change it from "make menuconfig" for
each board.)

This commit allows to lookup the DTB file name based on the compatible
string and set it to "fdt_file" environment.  Then "tftpboot $fdt_file"
will download the file we want.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:56 +09:00
Masahiro Yamada
33886693b6 ARM: uniphier: merge umc/ and ddrphy/ into a single directory
The UMC (Universal Memory Controller) and the DDR PHY block are
highly related to each other.  It is better to have both code in the
same directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:55 +09:00
Masahiro Yamada
6e1550fa7c ARM: uniphier: display model number all the time on boot up
Both "Model 1" and "Model 2" are supported for ProXstream2 and
PH1-LD6b boards.  It is useful to show the model number in the
boot banner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:54 +09:00
Masahiro Yamada
6f45a9755e ARM: uniphier: add macros and revision IDs for sLD11 and LD10
These are new SoCs from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:48 +09:00
Masahiro Yamada
6994700712 ARM: uniphier: compile uniphier_get_board_param() for U-Boot proper
Compile this file for U-Boot proper as well as SPL, so that the
U-Boot proper can call uniphier_get_board_param().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:42 +09:00
Masahiro Yamada
89c05fa51f ARM: uniphier: split ProXstream2 board data and change DDR frequency
The DDR3 memory chips on ProXstream2 boards support up to 2133 MHz,
while only up to 1866MHz on PH1-LD6b boards.

Split the board data structure and change the DDR frequency of
ProXstream2 boards to 2133 MHz.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:41 +09:00
Masahiro Yamada
6ba60fafda ARM: uniphier: call uniphier_get_board_param() without FDT blob
Move "gd->fdt_blob" from the caller to the callee so that this
function can be used more easily.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:40 +09:00
Masahiro Yamada
2071f149e5 ARM: uniphier: add functions to get SoC model/revision
We sometimes have to implement different code depending on the SoC
revision.  This commit adds functions to get the model/revision
number.

Note:
  Model number: incremented on major changes of the SoC
  Revision number: incremented on minor changes of the SoC

The "Model 2" exists for PH1-sLD3, ProXstream2/PH1-LD6b.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:35 +09:00
Masahiro Yamada
6a9f6ba0f9 ARM: uniphier: allow DDR function to return more precise error code
Return different error code depending on the reason so that the
caller can know the cause of the failure.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:27 +09:00
Masahiro Yamada
11d6effeae ARM: uniphier: use BIT() macro for DDR PHY header
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:15 +09:00
Masahiro Yamada
b04ed73a50 ARM: uniphier: rename DTCR_RNKEN_* register bit to DTCR_RANKEN_*
The bit 27-24 of the DTCR register is described as RANKEN in the
DDR PHY databook.  Follow this abbreviation.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:09 +09:00
Masahiro Yamada
a1c4bf8666 ARM: uniphier: add const qualifier to constant array
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:03 +09:00
Masahiro Yamada
fc18be1271 ARM: uniphier: add static qualifiers to locally used functions
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-12-23 00:08:03 +09:00
Masahiro Yamada
b375219e73 ARM: uniphier: drop UniPhier specific SMP code
The latest Linux can directly handle SMP operations for UniPhier SoCs
without any help of U-boot.  Drop the relevant code from U-boot.

See commit b1e4006aeda8c8784029de17d47987c21ea75f6d ("ARM: uniphier:
rework SMP operations to use trampoline code") in Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-11-11 23:35:35 +09:00
Tom Rini
da58dec866 Various Makefiles: Add SPDX-License-Identifier tags
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:19:52 -05:00
Masahiro Yamada
d47fe9bb83 ARM: uniphier: fix init page table for ProXstream2/PH1-LD6b USB boot
Currently, the USB boot mode is supported by an external loader and
U-boot proper image is put on the section 0.  This commit allows
access there.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:33 +09:00
Masahiro Yamada
019df879a9 ARM: uniphier: add ProXstream2 and PH1-LD6b support
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:33 +09:00
Masahiro Yamada
28f40d4a4d ARM: uniphier: add PH1-Pro5 support
The DDR SDRAM initialization code has not been mainlined yet, but
U-Boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:59:28 +09:00
Masahiro Yamada
323d1f9d5b ARM: uniphier: allow to enable multiple SoCs
Before this commit, the Kconfig menu in mach-uniphier only allowed us
to choose one SoC to be compiled.  Each SoC has its own defconfig file
for the build-test coverage.  Consequently, some defconfig files are
duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and
CONFIG_{SOC_NAME}=y.

Now, most of board-specific parameters have been moved to device trees,
so it makes sense to include init code of multiple SoCs into a single
image as long as the SoCs have similar architecture.  In fact, some
SoCs of UniPhier family are very similar:
 - PH1-LD4 and PH1-sLD8
 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit)

This commit will be helpful to merge some defconfig files for better
maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:58:38 +09:00
Masahiro Yamada
e6eecca54f ARM: uniphier: unify low-level debug init code
Move init code of low-level debug into a single file.
This is helpful to create an image that runs on multiple SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
fcbcd59730 ARM: uniphier: fix glitch signal problem for low-level debug
Currently, IECTRL is enabled after pin-mux settings for the low-level
debugging for PH1-LD4 and PH1-sLD8.  While IECTRL is disabled, input
signals are pulled-down, i.e. glitch signal (Low to High transition)
problem occurs if pin-mux is set up first.  As a result, one invalid
character is input to the UART block and the auto-boot counting is
terminated immediately.

The correct initialization procedure is:
 [1] Enable IECTRL (if IECTRL exists for the pins)
 [2] Set up pin-muxing
 [3] Deassert the reset of the hardware block

Currently, the low-level debugging is working for PH1-sLD3 and
PH1-Pro4, but just in case, follow the sequence for all the SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
257b11f32d ARM: uniphier: delete unneeded input enable for low-level debug
The UART I/O ports for PH1-Pro4 has no input enable controlling.
This code is useless.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
8497ccc4c2 ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_*
I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify
they belong to UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
c8df23cf33 ARM: uniphier: allow to disable CONFIG_MICRO_SUPPORT_CARD
Without this, build fails if CONFIG_MICRO_SUPPORT_CARD is disabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
d7728aa408 ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local file
It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally.
Move them to a C file as local macros.  Also, rename the C file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
8469700b6c ARM: uniphier: refactor LED function
The macro, led_write(), is now only used in C sources.  There is no
more reason to keep the tricky assembly macro.  Replace it with a
new C function led_puts().

Also, rename board.h to micro-support-card.h.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
0b198670c6 ARM: uniphier: remove useless wrapper functions
The wrapper functions, uniphier_board_*, are just making function
calls complex.  Remove them.

Also, use empty inline functions in case CONFIG_MICRO_SUPPORT_CARD
is disabled, so that prototype checking works.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
f1378cabc0 ARM: uniphier: remove unused header file
This has been unused since commit f4e190e317 ("ARM: uniphier:
enable SPL_OF_CONTROL").

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
cf88affab6 ARM: uniphier: parse device tree to determine DRAM base and size
Device tree specifies the available memory ranges in its "/memory"
node.  Use it to simplify the CONFIG defines.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
9628afa7f5 ARM: uniphier: remove ifdef CONFIG_{SOC} conditionals from sg-regs.h
To achieve the complete run-time configuration by device trees, ifdef
conditionals in header files are not preferable.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
d5ed8c5727 ARM: uniphier: change the external bus address mapping
In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces
 0x00000000 - 0x0fffffff
 0x40000000 - 0x4fffffff
are both mapped to the external bus (also called system bus),
so either was OK.

In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is
assigned for the serial NOR interface.

Going forward, use the latter for the external bus.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-25 00:27:53 +09:00
Masahiro Yamada
9879842c6f ARM: uniphier: drop DCC micro support card support
Historically (for compatibility with very old platforms), two
different types of micro support cards have been used with the
UniPhier SoC development boards.  It has been painful to maintain
both.  Having one of them is enough.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-25 00:27:52 +09:00
Masahiro Yamada
1386233da3 ARM: uniphier: drop ad-hoc input enable settings
These input enable settings are handled by the pinctrl drivers.

Because the external bus pins are input-enabled by default, on-board
devices such as LED still work fine even with this delayed input
enabling.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-09-25 00:27:52 +09:00
Masahiro Yamada
11f3afeaa5 ARM: uniphier: drop ad-hoc early pin-muxing settings
As the UniPhier serial driver had already switched to Drive Model
and the pinctrl drivers are now enabled, these pin-muxing settings
are properly handled by the pinctrl drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-25 00:27:52 +09:00
Masahiro Yamada
f4e190e317 ARM: uniphier: enable SPL_OF_CONTROL
Device Tree really improves code maintainability and is now
available for SPL too.

This is the state-of-the-art implementation in U-boot.

The board files (platform data) are no longer needed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-31 00:25:06 +09:00
Masahiro Yamada
94bd3699ee ARM: uniphier: fix build error when CONFIG_DEBUG_LL is defined
The build error happens if CONFIG_DEBUG_LL and CONFIG_MACH_PH1_SLD3
are both enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-08-30 22:19:00 +09:00
Masahiro Yamada
3365b4eb55 ARM: UniPhier: add PH1-sLD3 SoC support
The init code for UMC (Unified Memory Controller) and PLL has not
been mainlined yet, but U-boot proper should work.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-07-23 23:42:22 +09:00
Masahiro Yamada
8101b98298 ARM: UniPhier: add IDs for PH1-Pro5, ProXstream2, PH1-LD6b
This prepares for new SoCs support.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-07-02 01:07:25 +09:00
Masahiro Yamada
fcb2525d37 ARM: UniPhier: add pin mux setting for NAND CS1 of PH1-Pro4
The chip select 1 of the NAND controller is available if you want to
use, although the pins are shared with UART port 2.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:56:02 +09:00
Masahiro Yamada
28148b060d ARM: UniPhier: fix pin mux setting for USB port 2 of PH1-sLD8
The register value should be 1, not 4.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:56:00 +09:00
Masahiro Yamada
585b38c585 ARM: UniPhier: update DDR PHY register map for PH1-Pro5
PH1-Pro5 includes a newer version of DDR PHY IP.  Some registers
have been added to the reserved areas.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:55:57 +09:00
Masahiro Yamada
7fff91ffc0 ARM: UniPhier: set MACH_PH1_PRO4 as default SoC
One disadvantage of commit a26cd04920 (arch: Make board selection
choices optional) is that Kconfig could create such an insane
.config file that no board is selected.

As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the
"optional" again in favor of PH1-Pro4 as the default SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:55:53 +09:00
Masahiro Yamada
4e143cd6da ARM: UniPhier: remove meaningless CONFIG_SPL_BUILD ifdefs
This file is only built for SPL.  These ifdef conditionals are
unnecessary because UniPhier platform now supports UART on SPL.
Show appropriate messages on error.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:55:41 +09:00
Masahiro Yamada
9fc5f9daa1 ARM: UniPhier: remove unnecessary cache coherency code
Cache coherency for SMP is cared by Linux.  In U-Boot, the secondary
CPU(s) are just sleeping.  Nothing in memory is shared with the
primary CPU.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:55:38 +09:00
Masahiro Yamada
12a70e3c96 ARM: UniPhier: use 32 bit register access for debug UART setting
For the same reason as commit d0c47b3ef7 (serial: UniPhier: use
32 bit register access), use "str" instead of "strb" for the LCR
register setting.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:55:34 +09:00
Masahiro Yamada
b6ef3a3f04 ARM: UniPhier: update the vendor name of UniPhier in Kconfig
The business for UniPhier Soc family has been transferred from
Panasonic Corporation to Socionext Inc.

Update the SoC select menu in Kconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:55:30 +09:00
Masahiro Yamada
f6e7f07c17 ARM: UniPhier: replace <asm/io.h> with <linux/io.h>
In the Linux coding style, it is recommended to include <linux/io.h>
rather than <asm/io.h>.  Follow this trend.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-31 02:53:56 +09:00
Joe Hershberger
a26cd04920 arch: Make board selection choices optional
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
2015-05-12 18:10:02 -04:00
Masahiro Yamada
326a682358 malloc_f: enable SYS_MALLOC_F by default if DM is on
This option has a bool type, not hex.
Fix it and enable it if CONFIG_DM is on because Driver Model always
requires malloc memory.  Devices are scanned twice, before/after
relocation.  CONFIG_SYS_MALLOC_F should be enabled to use malloc
memory before relocation.  As it is board-independent, handle it
globally.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:09 -04:00
Masahiro Yamada
91405b7fa9 malloc_f: remove redundant defalut values of CONFIG_SYS_MALLOC_F_LEN
The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig
as 0x400.  Each defconfig or Kconfig need not repeat the same value.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Robert Baldyga <r.baldyga@samsung.com>
2015-03-28 09:03:08 -04:00
Masahiro Yamada
90e357efed ARM: UniPhier: remove unnecessary ifdef conditional
The callee (arch/arm/lib/cache-cp15.c) has a #ifdef
CONFIG_SYS_DCACHE_OFF conditional.  The same conditional in the
caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:16:02 +09:00
Masahiro Yamada
a509161a21 ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper
The L2 cache is used as a temporary SRAM on SPL.
Now the secondary CPUs store the necessary code for jumping to
Linux on their L1 I-caches.  So, the L2 cache can be disabled
much earlier, at the very entry of U-Boot proper (lowlevel_init).
This makes the boot sequence clearer.
Also, as the L1 cache has been disabled by the start.S,
enable_caches() does not need to do it again.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:58 +09:00
Masahiro Yamada
62118b7b01 ARM: UniPhier: optimize kicking secondary CPUs code
Currently, the secondary CPU(s) are kicked three times:
Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux.
It makes the boot sequence very complicated.

This commit merges the first and the second kicks, so the secondary
CPU(s) can directly jump from SPL to Linux.
arch/arm/mach-uniphier/smp.S is no longer necessary.

Linux boot test passed.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:55 +09:00
Masahiro Yamada
4d13b1b708 ARM: UniPhier: fix typos in comments
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:52 +09:00
Masahiro Yamada
def3feb8cb ARM: UniPhier: add empty lowlevel_init to U-boot proper
To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT,
add late_lowlevel_init.S to U-Boot proper.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:48 +09:00
Masahiro Yamada
ce3a63905b ARM: UniPhier: use CONFIG_SPL_STACK to define SPL stack pointer
Ifdef conditionals for CONFIG options are not Kconfig-friendly.
Instead, define CONFIG_SPL_STACK to prepare for Kconfig moves.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:38 +09:00
Masahiro Yamada
499785b970 ARM: UniPhier: enable Driver Model and UART on SPL
Enable CONFIG_SPL_DM and CONFIG_SPL_SERIAL_SUPPORT, which provide
Driver Model UART support on SPL.

CONFIG_SYS_SPL_MALLOC_{START,SIZE} should be dropped because simple
malloc is preferred on SPL.  Dlmalloc requires some static variables
on .data section that is not available yet for NOR boot mode etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:35 +09:00
Masahiro Yamada
7d1a3a67bc ARM: UniPhier: move UART pin settings to SPL
The UniPhier platform is going to enable Driver Model and UART
support on SPL.  Move UART pin settings to early_pin_init(),
which is called from SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:28 +09:00
Masahiro Yamada
94ab98bb1c ARM: UniPhier: move platform devices to SPL
Since we do not have OF_CONTROL support for SPL, platform devices
are necessary to enable Driver Model on SPL.

To prepare for that, move platdevice.o to SPL and enable it by
CONFIG_SPL_DM.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:24 +09:00
Masahiro Yamada
d5e7305013 ARM: UniPhier: include PH1-LD4 Makefile from PH1-sLD8
The two Makefiles arch/arm/mach-uniphier/{ph1-ld4,ph1-sld8}/Makefile
are completely the same.  We can improve the maintainability by
having one to include the other.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:21 +09:00
Masahiro Yamada
4ab994b16a ARM: UniPhier: remove unnecessary CONFIG_SYS_SOC
Since commit a86ac9540e (ARM: UniPhier: include <mach/*.h> instead
of <asm/arch/*.h>), UniPhier platform does not need the symbolic
link arch/arm/include/asm.  This option is not necessary either.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-24 00:15:10 +09:00
Masahiro Yamada
105a9e705e ARM: UniPhier: remove SSC_WAY_SIZE and SSC_NUM_ENTRIES macros
Each way of the system cache has 256 entries for PH1-Pro4 and older
SoCs, whereas 512 entries for PH1-Pro5 and newer SoCs.  The line
size is still 128 byte.  Thus, the way size is 32KB/64KB for old/new
SoCs.

To keep lowlevel_init SoC-independent, set BOOT_RAM_SIZE to the
constant value 32KB.  It is large enough for temporary RAM and
should work for all the SoCs of UniPhier family.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:03:21 +09:00
Masahiro Yamada
b76fa3a34b ARM: UniPhier: remove stop_mpll() from PH1-Pro4 PLL initialization
This function was intended for MN2WS0235 (what we call PH1-Pro4TV).
On that SoC, MPLL is already running on the power-on reset and it
makes sense to stop the PLL at early boot-up.
On the other hand, PH1-Pro4(R) does not have SC_MPLLOSCCTL register,
so this function has no point.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:03:18 +09:00
Masahiro Yamada
6cc2120646 ARM: UniPhier: consolidate MEMCONF setting code
This code is duplicated in ph1-ld4/sg_init.c and ph1-pro4/sg_init.c.
Merge the same code into a new file, memconf.c.

The helper functions no longer have to be placed in the header file.
Also, move them into memconf.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:03:13 +09:00
Masahiro Yamada
ea6de4ac80 ARM: UniPhier: support 1CS support card for all the UniPhier SoCs
Two support card variants are used with UniPhier reference boards:
 - 1 chip select support card (original CPLD)
 - 3 chip selects support card (ARIMA-compatible CPLD)

Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:03:06 +09:00
Masahiro Yamada
1535163a4e ARM: UniPhier: enable xHCI and GIO cores for PH1-Pro4
This is necessary to use the USB 3.0 host controllers on PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:55 +09:00
Masahiro Yamada
bdcf5a4c14 ARM: UniPhier: add I/O pin settings for xHCI on PH1-Pro4
This is necessary to use the xHCI cores for PH1-Pro4.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:54 +09:00
Masahiro Yamada
4c7d025368 ARM: UniPhier: move uniphier_ehci_reset() function
Because uniphier_ehci_reset() is only called from ehci-uniphier.c,
it can be a static function there.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-03-01 00:02:49 +09:00
Masahiro Yamada
44f597adeb ARM: UniPhier: remove EHCI platform devices
Now UniPhier platform highly depends on Device Tree configuration
(CONFIG_OF_CONTROL is select'ed by Kconfig).  Since the EHCI is only
used on main U-Boot, we can drop platform devices of the EHCI
controllers.  We still keep UART platform devices because they might
be useful for SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-03-01 00:02:48 +09:00
Masahiro Yamada
42ca6982ff ARM: UniPhier: enable STDMAC for EHCI
Deassert the reset signal and provide the clock for STDMAC core.
This is necessary for the USB 2.0 host controllers.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:45 +09:00
Masahiro Yamada
d3384bf77e ARM: UniPhier: reset NAND core in SPL for non-NAND boot mode
For all the UniPhier SoCs so far, the reset signal of the NAND core
is automatically deasserted after the PLL gets stabled.
(The bit 2 of SC_RSTCTRL is default to one.)

This causes a fatal problem on the NAND controller of PH1-LD4.
For that SoC, the NAND I/O pins are not set up yet at the power-on
reset except the NAND boot mode.  As a result, the NAND controller
begins automatic device scanning with wrong I/O pins and finally
hangs up.

Actually, U-Boot dies after printing "NAND:" on the console unless
the boot mode latch detected the NAND boot mode.

To work around this problem, reset the NAND core in SPL for non-NAND
boot modes.  If CONFIG_NAND_DENALI is enabled, the reset signal is
deasserted again in U-Boot proper.  At this time, I/O pins have been
correctly set up, the device scanning should succeed.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:40 +09:00
Masahiro Yamada
198a97a6ab ARM: UniPhier: split clkrst_init() into two functions
Split the current clkrst_init() into two functions:

 - early_clkrst_init(): called from SPL
  Deassert the reset signals of the memory controller and some other
  basic cores.

 - clkrst_init(): called from main U-boot
  Deassert the reset signals that are necessary for the access to
  peripherals etc.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:36 +09:00
Masahiro Yamada
f267b81e20 ARM: UniPhier: rename SC_CLKCTRL_CLK_* to SC_SCLKCTRL_CEN_*
Follow the register macros in the LSI specification book.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:32 +09:00
Masahiro Yamada
27eac5df17 ARM: UniPhier: fix SBC init code
Now UniPhier SoCs only work with CONFIG_SPL and the function
sbc_init() is called from SPL.
The conditional #if !defined(CONFIG_SPL_BUILD) has no point
any more.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:29 +09:00
Masahiro Yamada
1a745d27bd ARM: UniPhier: fix comments in PH1-Pro4 SBC code
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:27 +09:00
Masahiro Yamada
a86ac9540e ARM: UniPhier: include <mach/*.h> instead of <asm/arch/*.h>
Since commit 0e7368c6c4 (kbuild: prepare for moving headers into
mach-*/include/mach), we can replace #include <asm/arch/*.h> with
<mach/*.h> so we do not need to create the symbolic link during the
build.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:18 +09:00
Masahiro Yamada
9eb7acef97 ARM: UniPhier: move SoC headers to mach-uniphier/include/mach
Move arch/arm/include/asm/arch-uniphier/*
  -> arch/arm/mach-uniphier/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:02:12 +09:00
Masahiro Yamada
4c42557021 ARM: UniPhier: move SoC sources to mach-uniphier
Move
arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2015-03-01 00:01:56 +09:00