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ARM: uniphier: add dump command for DDR Multi PHY registers
The ProXstream2/PH1-LD6b is integrated with a new IP for DDR PHY which is not register-compatible with the former SoCs. Add a new command to support the register dump of this IP. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
15607d0d94
commit
93d92d46cd
3 changed files with 339 additions and 0 deletions
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@ -70,8 +70,17 @@ config CMD_PINMON
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config CMD_DDRPHY_DUMP
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bool "Enable dump command of DDR PHY parameters"
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depends on ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 || \
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ARCH_UNIPHIER_PH1_SLD8
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help
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The command "ddrphy" shows the resulting parameters of DDR PHY
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training; it is useful for the evaluation of DDR PHY training.
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config CMD_DDRMPHY_DUMP
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bool "Enable dump command of DDR Multi PHY parameters"
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depends on ARCH_UNIPHIER_PROXSTREAM2 || ARCH_UNIPHIER_PH1_LD6B
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help
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The command "ddrmphy" shows the resulting parameters of DDR Multi PHY
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training; it is useful for the evaluation of DDR Multi PHY training.
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endif
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329
arch/arm/mach-uniphier/cmd_ddrmphy.c
Normal file
329
arch/arm/mach-uniphier/cmd_ddrmphy.c
Normal file
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@ -0,0 +1,329 @@
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/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "ddrmphy-regs.h"
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/* Select either decimal or hexadecimal */
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#if 1
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#define PRINTF_FORMAT "%2d"
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#else
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#define PRINTF_FORMAT "%02x"
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#endif
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/* field separator */
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#define FS " "
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static void __iomem *get_phy_base(int ch)
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{
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return (void __iomem *)(0x5b830000 + ch * 0x00200000);
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}
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static int get_nr_ch(void)
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{
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const struct uniphier_board_data *bd = uniphier_get_board_param();
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return bd->dram_ch2_width ? 3 : 2;
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}
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static int get_nr_datx8(int ch)
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{
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unsigned int width;
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const struct uniphier_board_data *bd = uniphier_get_board_param();
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switch (ch) {
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case 0:
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width = bd->dram_ch0_width;
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break;
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case 1:
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width = bd->dram_ch1_width;
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break;
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default:
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width = bd->dram_ch2_width;
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break;
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}
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return width / 8;
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}
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static void print_bdl(void __iomem *reg, int n)
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{
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u32 val = readl(reg);
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int i;
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for (i = 0; i < n; i++)
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printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
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}
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static void dump_loop(void (*callback)(void __iomem *))
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{
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int ch, dx, nr_ch, nr_dx;
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void __iomem *dx_base;
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nr_ch = get_nr_ch();
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for (ch = 0; ch < nr_ch; ch++) {
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dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
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nr_dx = get_nr_datx8(ch);
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for (dx = 0; dx < nr_dx; dx++) {
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printf("CH%dDX%d:", ch, dx);
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(*callback)(dx_base);
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dx_base += DMPHY_DX_STRIDE;
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printf("\n");
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}
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}
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}
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static void zq_dump(void)
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{
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int ch, zq, nr_ch, nr_zq, i;
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void __iomem *zq_base;
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u32 dr, pr;
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printf("\n--- Impedance Data ---\n");
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printf(" ZPD ZPU OPD OPU ZDV ODV\n");
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nr_ch = get_nr_ch();
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for (ch = 0; ch < nr_ch; ch++) {
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zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
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nr_zq = 3;
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for (zq = 0; zq < nr_zq; zq++) {
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printf("CH%dZQ%d:", ch, zq);
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dr = readl(zq_base + DMPHY_ZQ_DR);
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for (i = 0; i < 4; i++) {
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printf(FS PRINTF_FORMAT, dr & 0x7f);
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dr >>= 7;
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}
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pr = readl(zq_base + DMPHY_ZQ_PR);
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for (i = 0; i < 2; i++) {
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printf(FS PRINTF_FORMAT, pr & 0xf);
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pr >>= 4;
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}
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zq_base += DMPHY_ZQ_STRIDE;
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printf("\n");
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}
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}
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}
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static void __wbdl_dump(void __iomem *dx_base)
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{
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print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
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printf(FS "(+" PRINTF_FORMAT ")",
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readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
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}
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static void wbdl_dump(void)
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{
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printf("\n--- Write Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
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dump_loop(&__wbdl_dump);
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}
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static void __rbdl_dump(void __iomem *dx_base)
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{
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print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
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printf(FS "(+" PRINTF_FORMAT ")",
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(readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
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printf(FS "(+" PRINTF_FORMAT ")",
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(readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
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}
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static void rbdl_dump(void)
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{
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printf("\n--- Read Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
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dump_loop(&__rbdl_dump);
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}
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static void __wld_dump(void __iomem *dx_base)
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{
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int rank;
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u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
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u32 gtr = readl(dx_base + DMPHY_DX_GTR);
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for (rank = 0; rank < 4; rank++) {
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u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
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u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
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printf(FS PRINTF_FORMAT "%sT", wld,
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wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
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}
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}
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static void wld_dump(void)
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{
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printf("\n--- Write Leveling Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(&__wld_dump);
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}
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static void __dqsgd_dump(void __iomem *dx_base)
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{
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int rank;
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u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
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u32 gtr = readl(dx_base + DMPHY_DX_GTR);
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for (rank = 0; rank < 4; rank++) {
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u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
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u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
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printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
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}
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}
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static void dqsgd_dump(void)
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{
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printf("\n--- DQS Gating Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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dump_loop(&__dqsgd_dump);
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}
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static void __mdl_dump(void __iomem *dx_base)
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{
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int i;
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u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
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for (i = 0; i < 3; i++)
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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}
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static void mdl_dump(void)
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{
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printf("\n--- Master Delay Line ---\n");
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printf(" IPRD TPRD MDLD\n");
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dump_loop(&__mdl_dump);
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}
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#define REG_DUMP(x) \
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{ int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \
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printf("%3d: %-10s: %p : %08x\n", \
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ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
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#define DX_REG_DUMP(dx, x) \
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{ int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \
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DMPHY_DX_## x; \
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void __iomem *reg = phy_base + ofst; \
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printf("%3d: DX%d%-7s: %p : %08x\n", \
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ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
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static void reg_dump(void)
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{
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int ch, dx, nr_ch, nr_dx;
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void __iomem *phy_base;
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printf("\n--- DDR PHY registers ---\n");
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nr_ch = get_nr_ch();
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for (ch = 0; ch < nr_ch; ch++) {
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phy_base = get_phy_base(ch);
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nr_dx = get_nr_datx8(ch);
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printf("== Ch%d ==\n", ch);
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printf(" No: Name : Address : Data\n");
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REG_DUMP(RIDR);
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REG_DUMP(PIR);
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REG_DUMP(PGCR0);
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REG_DUMP(PGCR1);
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REG_DUMP(PGCR2);
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REG_DUMP(PGCR3);
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REG_DUMP(PGSR0);
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REG_DUMP(PGSR1);
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REG_DUMP(PLLCR);
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REG_DUMP(PTR0);
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REG_DUMP(PTR1);
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REG_DUMP(PTR2);
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REG_DUMP(PTR3);
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REG_DUMP(PTR4);
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REG_DUMP(ACMDLR);
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REG_DUMP(ACBDLR0);
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REG_DUMP(DXCCR);
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REG_DUMP(DSGCR);
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REG_DUMP(DCR);
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REG_DUMP(DTPR0);
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REG_DUMP(DTPR1);
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REG_DUMP(DTPR2);
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REG_DUMP(DTPR3);
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REG_DUMP(MR0);
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REG_DUMP(MR1);
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REG_DUMP(MR2);
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REG_DUMP(MR3);
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for (dx = 0; dx < nr_dx; dx++) {
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DX_REG_DUMP(dx, GCR0);
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DX_REG_DUMP(dx, GCR1);
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DX_REG_DUMP(dx, GCR2);
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DX_REG_DUMP(dx, GCR3);
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DX_REG_DUMP(dx, GTR);
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}
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}
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}
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static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *cmd = argv[1];
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if (argc == 1)
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cmd = "all";
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if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
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zq_dump();
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if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
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wbdl_dump();
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if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
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rbdl_dump();
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if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
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wld_dump();
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if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
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dqsgd_dump();
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if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
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mdl_dump();
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if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
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reg_dump();
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return 0;
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}
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U_BOOT_CMD(
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ddrm, 2, 1, do_ddrm,
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"UniPhier DDR PHY parameters dumper",
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"- dump all of the followings\n"
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"ddrm zq - dump Impedance Data\n"
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"ddrm wbdl - dump Write Bit Delay\n"
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"ddrm rbdl - dump Read Bit Delay\n"
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"ddrm wld - dump Write Leveling\n"
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"ddrm dqsgd - dump DQS Gating Delay\n"
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"ddrm mdl - dump Master Delay Line\n"
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"ddrm reg - dump registers\n"
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);
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@ -12,3 +12,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += umc-proxstream2.o
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obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += umc-proxstream2.o
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obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
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obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
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