Commit graph

191 commits

Author SHA1 Message Date
Wolfgang Denk
20640002e6 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-08-29 00:53:51 +02:00
Heiko Schocher
f98984cb19 IDE: - make ide_inb () and ide_outb () "weak", so boards can
define there own I/O functions.
          (Needed for the pcs440ep board).
        - The default I/O Functions are again 8 Bit accesses.
        - Added CONFIG_CMD_IDE for the pcs440ep Board.

Signed-off-by: Heiko Schocher <hs@denx.de>
2007-08-28 17:39:14 +02:00
Stefan Roese
93f7983460 Merge with /home/stefan/git/u-boot/u-boot-ppc4xx 2007-08-21 16:33:33 +02:00
Stefan Roese
3ad6387873 ppc4xx: Add matrix kbd support to lwmon5 board (440EPx based)
This patch adds support for the matrix keyboard on the lwmon5 board.
Since the implementation in the dsPCI is kind of compatible with the
"old" lwmon board, most of the code is copied from the lwmon
board directory.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-21 16:27:57 +02:00
Andy Fleming
b96c83d4ae Fix numerous bugs in the 8568 UEC support
Actually, fixed a large bug in the UEC for *all* platforms.
How did this ever work?

uec_init() did not follow the spec for eth_init(), and returned
0 on success.  Switch it to return the link like tsec_init()
(and 0 on error)

The immap for the 8568 was defined based on MPC8568, rather than
CONFIG_MPC8568

CONFIG_QE was off

CONFIG_ETHPRIME was set to "Freescale GETH".  Now is "FSL UEC0"

Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is
enabled

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-16 12:12:51 +02:00
Stefan Roese
3b3bff4cbf Merge with git://www.denx.de/git/u-boot.git 2007-08-14 16:36:29 +02:00
Andy Fleming
da9d4610d7 Add support for UEC to 8568
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:47:44 -05:00
Haiying Wang
c59e4091ff Add PCI support for MPC8568MDS board
This patch is against u-boot-mpc85xx.git of www.denx.com

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
2007-08-14 01:46:08 -05:00
Ed Swarthout
837f1ba05c 8544ds PCIE support
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address.

Enable LBC and ECM errors and clear error registers.

Add tftpflash env var to get uboot from tftp server and flash it.

Add pci/pcie convenience env vars to display register space:
  "run pcie3regs" to see all pcie3 ccsr registers
  "run pcie3cfg" to see all cfg registers
Whitespace cleanup and MPC8544DS.h

Enable CONFIG_INTERRUPTS.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:38:40 -05:00
Andy Fleming
61a21e980a 85xx start.S cleanup and exception support
From: Ed Swarthout <Ed.Swarthout@freescale.com>

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-14 01:34:21 -05:00
Ed Swarthout
2e4d94f1e3 fsl_pci_init cleanup.
Do not enable normal errors created during probe (master abort, perr,
and pcie Invalid Configuration access).

Add CONFIG_PCI_NOSCAN board option to prevent bus scan.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2007-08-10 11:39:37 -05:00
Jon Loeliger
cfc7a7f5bb cpu/86xx fixes.
Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-10 11:02:32 -05:00
Wolfgang Denk
f2c2a937d8 Merge with /home/wd/git/u-boot/custodian/u-boot-testing 2007-08-06 01:11:08 +02:00
Wolfgang Denk
46919751ea Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xx 2007-08-06 00:55:51 +02:00
Ed Swarthout
63cec5814f Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts.
All of the PCI/PCI-Express driver and initialization code that
was in the MPC8641HPCN port has now been moved into the common
drivers/fsl_pci_init.c.  In a subsequent patch, this will be
utilized by the 85xx ports as well.

Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added.

Also enable the second PCI-Express controller on 8641
by getting its BATS and CFG_ setup right.

Fixed a u16 vendor compiler warning in AHCI driver too.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Zhang Wei <wei.zhang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-08-06 00:22:24 +02:00
Stefan Roese
b5dc4403f6 Merge with git://www.denx.de/git/u-boot.git 2007-08-02 08:43:48 +02:00
Rafal Jaworowski
8993e54b6f [ADS5121] Support for the ADS5121 board
The following MPC5121e subsystems are supported:

- low-level CPU init
- NOR Boot Flash (common CFI driver)
- DDR SDRAM
- FEC
- I2C
- Watchdog

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
2007-07-27 14:43:59 +02:00
Rafal Jaworowski
1863cfb7b1 [PPC] Remove unused MSR_USER definition
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-07-27 14:22:04 +02:00
Rafal Jaworowski
cc3023b9f9 Fix breakage of 8xx boards from recent commit.
This patch fixes the negative consequences for 8xx of the recent
"ppc4xx: Clean up 440 exceptions handling" commit.

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
2007-07-19 17:12:28 +02:00
Stefan Roese
5743a9207a ppc4xx: Add remove_tlb() function to remove a mem area from TLB setup
The new function remove_tlb() can be used to remove the TLB's used to
map a specific memory region. This is especially useful for the DDR(2)
setup routines which configure the SDRAM area temporarily as a cached
area (for speedup on auto-calibration and ECC generation) and later
need this area uncached for normal usage.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-16 08:53:51 +02:00
Andy Fleming
982efcf23f From: eran liberty <eran.liberty@gmail.com>
adds the reset register to 85xx immap

Signed-off-by: Eran Liberty <eran.liberty@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-07-11 18:19:07 -05:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Stefan Roese
b7c3e93105 Merge with /home/stefan/git/u-boot/denx-440-exceptions 2007-06-15 11:20:13 +02:00
Grzegorz Bernacki
efa35cf12d ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 11:19:28 +02:00
Stefan Roese
85f737376d [ppc4xx] Extend 44x GPIO setup with default output state
The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
is extended with the default GPIO output state (level).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 07:39:43 +02:00
Stefan Roese
f3679aa13d Merge with /home/stefan/git/u-boot/bamboo-nand 2007-06-01 16:15:34 +02:00
Stefan Roese
53ad02103f ppc4xx: Update in_be32() functions and friends to latest Linux version
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01 15:16:58 +02:00
Wolfgang Denk
256176d3d5 Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xx 2007-05-16 01:12:04 +02:00
Grzegorz Wianecki
a9d87e2707 [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
message. Use PVR to distinguish between the two variants, and print proper CPU
information.

Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com>
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
2007-05-05 21:35:03 +02:00
Andy Fleming
6743105988 Add support for the 8568 MDS board
This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-05-02 15:50:02 -05:00
Andy Fleming
81f481ca70 Enable 8544 support
* Add support to the Makefile
* Add 8544 configuration support to the tsec driver
* Add 8544 SVR numbers to processor.h

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-04-23 19:58:28 -05:00
Andy Fleming
45cef612cc Changed BOOKE_PAGESZ_nGB to BOOKE_PAGESZ_nG
The other pagesz constants use one letter to specify order of
magnitude.  Also change the one reference to it in mpc8548cds/init.S

Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-04-23 19:58:28 -05:00
Zang Roy-r61911
41fb7e0f1e u-boot: Enable PCI function and add PEX & rapidio memory map on MPC8548CDS board
Enable PCI function and add PEX & rapidio memory map on MPC8548CDS
board.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2007-04-23 19:58:27 -05:00
Scott Wood
0f253283a3 mpc83xx: Add 831x support to global_data.h
Signed-off-by: Scott Wood <scottwood@freescale.com>
2007-04-23 16:32:00 -05:00
Scott Wood
95e7ef897e mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().
Rather than misleadingly define PVR_83xx as the specific type of 83xx
being built for, the PVR of each core revision is defined. checkcpu() now
prints the core that it detects, rather than aborting if it doesn't find
what it thinks it wants.

Signed-off-by: Scott Wood <scottwood@freescale.com>
2007-04-23 16:31:59 -05:00
Scott Wood
d87c57b201 mpc83xx: Add register definitions for MPC831x.
Signed-off-by: Scott Wood <scottwood@freescale.com>
2007-04-23 16:31:59 -05:00
Wolfgang Denk
43f6226db0 Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xx 2007-04-18 17:00:09 +02:00
Stefan Roese
0e7d4916af Merge with git://www.denx.de/git/u-boot.git 2007-03-31 13:44:12 +02:00
Wolfgang Denk
6db7d0af23 Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xx 2007-03-29 12:16:41 +02:00
Stefan Roese
e50b791b3f Merge with /home/stefan/git/u-boot/acadia 2007-03-24 15:59:23 +01:00
Stefan Roese
0d974d5297 [PATCH] Add 4xx GPIO functions
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-24 15:57:09 +01:00
Haiying Wang
9964a4dd0d Set Rev 2.x 86xx PIC in mixed mode.
Prevent false interrupt from hanging Linux as MSR[EE] is set
to enable interrupts by changing the PIC out of the default
pass through mode into mixed mode.

Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
2007-03-22 11:02:35 -05:00
Stefan Roese
fc1e45ce6e Merge with /home/stefan/git/u-boot/acadia 2007-03-21 14:38:25 +01:00
Stefan Roese
e01bd218b0 [PATCH] Add AMCC PPC405EZ support
This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.

Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-21 13:38:59 +01:00
Kumar Gala
3e78a31cfe mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead
The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all
MPC834X class processors.  Change the protections from CONFIG_MPC8349 to
CONFIG_MPC834X so they are more generic.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-02 11:05:53 -06:00
Dave Liu
24c3aca3f1 mpc83xx: Add support for the MPC832XEMDS board
This patch supports DUART, ETH3/4 and PCI etc.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:53 -06:00
Dave Liu
e080313c32 mpc83xx: streamline the 83xx immr head file
For better format and style, I streamlined the 83xx head files,
including immap_83xx.h and mpc83xx.h. In the old head files, 1)
duplicated macro definition appear in the both files; 2) the structure
of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The
macro definition put inside the each structure. So, I cleaned up the
structure of QE immr from immap_83xx.h, deleted the duplicated stuff and
moved the macro definition to mpc83xx.h, Just like MPC8260.

CHANGELOG

*streamline the 83xx immr head file

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:53 -06:00
roy zang
00b574bdc8 Merge branch 'master' into hpc2
Conflicts:

	drivers/Makefile
Fix the merge conflict in file drivers/Makefile
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
2007-02-28 16:46:48 +08:00
Haiying Wang
3a197b2fe4 [PATCH v3] Add sync to ensure flash_write_cmd is fully finished
Some CPUs like PPC, BLACKFIN need sync() to ensure cfi flash write command
is fully finished. The sync() is defined in each CPU's io.h file. For
those CPUs which do not need sync for now, a dummy sync() is defined in
their io.h as well.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2007-02-21 16:52:31 +01:00
Stefan Roese
4037ed3b63 [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM support
This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:

- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:43:34 +01:00