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https://github.com/AsahiLinux/u-boot
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Add PCI support for MPC8568MDS board
This patch is against u-boot-mpc85xx.git of www.denx.com Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>
This commit is contained in:
Haiying Wang
Andrew Fleming-AFLEMING
parent
d111d6382c
commit
c59e4091ff
4 changed files with 98 additions and 38 deletions
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@ -143,54 +143,42 @@ tlb1_entry:
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.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLBe 2: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM
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* TLBe 2: 1G Non-cacheable, guarded
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* 0x80000000 512M PCI1 MEM
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* 0xa0000000 512M PCIe MEM
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*/
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.long TLB1_MAS0(1, 2, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLBe 3: 256M Non-cacheable, guarded
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* 0xa0000000 256M PCIe Mem
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*/
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.long TLB1_MAS0(1, 3, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLBe 4: Reserved for future usage
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*/
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/*
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* TLBe 5: 64M Non-cacheable, guarded
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* TLBe 3: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe200_0000 8M PCI1 IO
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* 0xe280_0000 8M PCIe IO
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*/
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.long TLB1_MAS0(1, 5, 0)
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.long TLB1_MAS0(1, 3, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLBe 6: 64M Cacheable, non-guarded
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* TLBe 4: 64M Cacheable, non-guarded
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* 0xf000_0000 64M LBC SDRAM
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*/
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.long TLB1_MAS0(1, 6, 0)
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.long TLB1_MAS0(1, 4, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLBe 7: 256K Non-cacheable, guarded
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* TLBe 5: 256K Non-cacheable, guarded
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* 0xf8000000 32K BCSR
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* 0xf8008000 32K PIB (CS4)
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* 0xf8010000 32K PIB (CS5)
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*/
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.long TLB1_MAS0(1, 7, 0)
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.long TLB1_MAS0(1, 5, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
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@ -202,12 +190,12 @@ tlb1_entry:
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* LAW(Local Access Window) configuration:
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*
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*0) 0x0000_0000 0x7fff_ffff DDR 2G
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*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB
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*2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB
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*5) 0xc000_0000 0xdfff_ffff SRIO 256MB
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*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
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*2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
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*-) 0xe000_0000 0xe00f_ffff CCSR 1M
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*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
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*4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M
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*4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
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*5) 0xc000_0000 0xdfff_ffff SRIO 512MB
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*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
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*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
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*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
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@ -226,20 +214,20 @@ tlb1_entry:
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
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#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
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#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
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/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
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#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
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@ -27,6 +27,7 @@
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <spd.h>
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#include <i2c.h>
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#include "bcsr.h"
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@ -50,6 +51,15 @@ int board_early_init_f (void)
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enable_8568mds_duart();
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enable_8568mds_flash_write();
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#ifdef CFG_I2C2_OFFSET
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/* Enable I2C2_SCL and I2C2_SDA */
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volatile struct par_io *port_c;
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port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
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port_c->cpdir2 |= 0x0f000000;
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port_c->cppar2 &= ~0x0f000000;
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port_c->cppar2 |= 0x0a000000;
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#endif
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return 0;
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}
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@ -269,20 +279,62 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
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#endif
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static struct pci_controller hose[] = {
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{
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#ifndef CONFIG_PCI_PNP
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{ config_table: pci_mpc8568mds_config_table,},
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#endif
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#ifdef CONFIG_MPC85XX_PCI2
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{},
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config_table: pci_mpc8568mds_config_table,
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#endif
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}
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};
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#endif /* CONFIG_PCI */
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/*
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* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
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*/
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void
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pib_init(void)
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{
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u8 val8, orig_i2c_bus;
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/*
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* Assign PIB PMC2/3 to PCI bus
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*/
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/*switch temporarily to I2C bus #2 */
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orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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val8 = 0x00;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0x00;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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val8 = 0xf9;
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0x00;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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asm("eieio");
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}
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void
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pci_init_board(void)
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{
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#ifdef CONFIG_PCI
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pib_init();
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pci_mpc85xx_init(&hose);
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#endif
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}
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@ -1522,6 +1522,17 @@ typedef struct ccsr_rio {
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char res58[60176];
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} ccsr_rio_t;
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/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
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typedef struct par_io {
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uint cpodr; /* 0x100 */
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uint cpdat; /* 0x104 */
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uint cpdir1; /* 0x108 */
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uint cpdir2; /* 0x10c */
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uint cppar1; /* 0x110 */
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uint cppar2; /* 0x114 */
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char res[8];
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}par_io_t;
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/*
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* Global Utilities Register Block(0xe_0000-0xf_ffff)
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*/
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@ -1585,7 +1596,13 @@ typedef struct ccsr_gur {
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uint svr; /* 0xe00a4 - System version register */
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char res10a[8];
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uint rstcr; /* 0xe00b0 - Reset control register */
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#ifdef MPC8568
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char res10b[76];
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par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
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char res10c[3136];
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#else
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char res10b[3404];
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#endif
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uint clkocr; /* 0xe0e00 - Clock out select register */
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char res11[12];
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uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
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@ -33,7 +33,7 @@
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#define CONFIG_MPC8568 1 /* MPC8568 specific */
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#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
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#undef CONFIG_PCI
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#define CONFIG_PCI
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
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@ -306,11 +306,14 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_I2C_CMD_TREE
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR 0x52
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_NOPROBES {0,0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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#define CFG_I2C2_OFFSET 0x3100
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/*
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* General PCI
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@ -318,7 +321,7 @@ extern unsigned long get_clock_freq(void);
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*/
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_IO_BASE 0x00000000
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#define CFG_PCI1_IO_PHYS 0xe2000000
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#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
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