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Fix numerous bugs in the 8568 UEC support

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Actually, fixed a large bug in the UEC for *all* platforms.
How did this ever work?

uec_init() did not follow the spec for eth_init(), and returned
0 on success.  Switch it to return the link like tsec_init()
(and 0 on error)

The immap for the 8568 was defined based on MPC8568, rather than
CONFIG_MPC8568

CONFIG_QE was off

CONFIG_ETHPRIME was set to "Freescale GETH".  Now is "FSL UEC0"

Fixed a comment about the ranges for CONFIG_ETHPRIME if TSEC_ENET is
enabled

Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Andy Fleming 2007-08-15 20:03:34 -05:00 committed by Wolfgang Denk
parent 3a79013e2a
commit b96c83d4ae
3 changed files with 7 additions and 7 deletions
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6
drivers/qe/uec.c
View file

@ -1110,7 +1110,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
if (dev->enetaddr[0] & 0x01) {
printf("%s: MacAddress is multcast address\n",
__FUNCTION__);
return -EINVAL;
return 0;
}
uec_set_mac_address(uec, dev->enetaddr);
uec->the_first_run = 1;
@ -1119,10 +1119,10 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
err = uec_open(uec, COMM_DIR_RX_AND_TX);
if (err) {
printf("%s: cannot enable UEC device\n", dev->name);
return err;
return 0;
}
return 0;
return uec->mii_info->link;
}
static void uec_halt(struct eth_device* dev)

2
include/asm-ppc/immap_85xx.h
View file

@ -1596,7 +1596,7 @@ typedef struct ccsr_gur {
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
#ifdef MPC8568
#ifdef CONFIG_MPC8568
char res10b[76];
par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
char res10c[3136];

6
include/configs/MPC8568MDS.h
View file

@ -35,7 +35,7 @@
#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#undef CONFIG_QE /* Enable QE */
#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@ -348,7 +348,7 @@ extern unsigned long get_clock_freq(void);
*/
#define CONFIG_UEC_ETH
#ifndef CONFIG_TSEC_ENET
#define CONFIG_ETHPRIME "Freescale GETH"
#define CONFIG_ETHPRIME "FSL UEC0"
#endif
#define CONFIG_PHY_MODE_NEED_CHANGE
#define CONFIG_eTSEC_MDIO_BUS
@ -409,7 +409,7 @@ extern unsigned long get_clock_freq(void);
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
/* Options are: eTSEC[0-3] */
/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
#endif /* CONFIG_TSEC_ENET */