This patch adds support for Realtek PHY RTL8201F 10/100Mbs
(with variants: RTL8201FN and RTL8201FL) PHYceiver. It is
present on Actions Semi Cubieboard7 board.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default
ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform
Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board
mmc:
- minor GD pointer removal
net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver
spi:
- Cleanup global macros for xilinx spi drivers
firmware:
- Add support for pmufw reloading
fpga:
- Improve error status reporting
common:
- Remove 4kB addition space for FDT allocation
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Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2020.10
Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default
ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform
Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board
mmc:
- minor GD pointer removal
net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver
spi:
- Cleanup global macros for xilinx spi drivers
firmware:
- Add support for pmufw reloading
fpga:
- Improve error status reporting
common:
- Remove 4kB addition space for FDT allocation
The clock ouput frequency is calculated incorrectly for AR8035 due to
wrong masking of priv->clk_25m_reg and priv->clk_25m_mask.
This same issue has been already fixed in the kernel by:
commit b1f4c209d84057b6d40b939b6e4404854271d797
Author: Oleksij Rempel <o.rempel@pengutronix.de>
Date: Wed Apr 1 11:57:32 2020 +0200
net: phy: at803x: fix clock sink configuration on ATH8030 and ATH8035
The masks in priv->clk_25m_reg and priv->clk_25m_mask are one-bits-set
for the values that comprise the fields, not zero-bits-set.
This patch fixes the clock frequency configuration for ATH8030 and
ATH8035 Atheros PHYs by removing the erroneous "~".
To reproduce this bug, configure the PHY with the device tree binding
"qca,clk-out-frequency" and remove the machine specific PHY fixups.
Fixes: 2f664823a47021 ("net: phy: at803x: add device tree binding")
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk>
Tested-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Apply the same fix in the U-Boot driver.
Tested on a i.MX6 Hummingboard.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Tested-by: Tom Rini <trini@konsulko.com>
Add the DP8382X generic PHY registration to the TI PHY init file.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
ti_phy_init function was allocated to the DP83867 PHY. This function
name is to generic for a specific PHY. The function can be moved to a
TI specific file that can register all TI PHYs that are defined in the
defconfig. The ti_phy_init file will contain all TI PHYs initialization
so that only phy_ti_init can be called from the framework.
In addition to the above the config flag for the DP83867 needs to be changed
in the Kconfig and dependent defconfig files. The config flag that was
used for the DP83867 was also generic in nature so a more specific
config flag for the DP83867 was created.
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
There are devices accesible through mdio clause-45, such as
retimers, that do not have PMA or PCS blocks.
This patch adds MDIO_MMD_VEND1 on the list of device addresses
where phyid is searched. Previous order of devices was kept.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Linux commit 232ba3a51cc2 ('net: phy: Micrel KSZ8061: link failure after
cable connect') implements a fix for the above errata.
This patch replicates that errata fix in an ksz8061 specific init routine.
Signed-off-by: Bryan O'Donoghue <bod@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.
Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.
This requires quite a few header-file additions.
Signed-off-by: Simon Glass <sjg@chromium.org>
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.
Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add RX delay enable support for RTL8211F PHY.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The two functions are now exactly the same, remove one of them.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
We can configure the clock output in the device tree. Disable the
hardcoded one in here. This is highly board-specific and should have
never been enabled in the PHY driver.
If bisecting shows that this commit breaks your board it probably
depends on the clock output of your Atheros AR8035 PHY. Please have a
look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
"clk-out-frequency = <125000000>" because that value was the hardcoded
value until this commit.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add support for configuring the CLK_25M pin as well as the RGMII I/O
voltage by the device tree.
By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
But this output can also be changed by software to other frequencies.
This commit introduces a generic way to configure this output.
Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V.
An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V
option needs an external supply voltage. This commit adds support to
switch the internal LDO to 1.8V.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Provide functions to read and write the Atheros debug registers.
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
To eliminate any doubts about the out-of-reset value of the PHY, that
the driver previously relied on.
If bisecting shows that this commit breaks your board you probably have
a wrong PHY interface mode. You probably want the
PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Delete the extraneous write to debug reg 5 that enables Tx delay
When the driver was originally introduced in commit "6027384a phylib:
Add Atheros AR8035 GETH PHY support", the Tx delay was being
unconditionally enabled.
Then during "2ec4d10b phy: atheros: add support for RGMII_ID, RGMII_TXID
and RGMII_RXID", the author did not notice that code for enabling Tx
delay code was already. Therefore, the if condition for Tx delay has
always been useless for this PHY since this commit introduced it.
Prior to this patch, every AR8035 PHY in U-boot had Tx delay enabled.
After this patch, only those who define the interface as RGMII_TXID or
RGMII_ID will. This is to be expected, but will nonetheless break the
setups of those who didn't know they rely on Tx delay implicitly.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PHY models of the Marvell 88E151x series are not reliably
distinguishable by their uid / PHY identifiers.
The 88E1510, 88E1512, 88E1514 and 88E1518 all have the same OUI and
model number and bits 3:0 in the PHY Identifier 2 (Page 0, Reg 3) are
described as HW revision number, but both 88E1510 and 88E1518 PHYs were
observed with the same HW rev number (1).
Before commit 83cfbeb0df ("net: phy: Fix mask so that we can identify
Marvell 88E1518"), the 88E151x were detected because the HW revision
bits were masked from the uid. After that change, 88E1510/12/18 were all
detected as 88E1518 and the 88E1510 specific code was no longer run.
I modified the mask to again ignore all four HW revision bits, removed
the 88E1510 specific code (board-specific LED/INTn setup), which was not
called since late 2016 anyway and renamed the config function and
phy_driver struct to the better fitting 88e151x.
The uid and mask bits 3:0 are now again the same as in the Linux kernel.
Signed-off-by: Clemens Gruber <clemens.gruber@pqgruber.com>
This patch adds ability to switch beetween two PHY SGMII modes.
Some hardware, for example, FPGA IP designs may use 6-wire mode
which enables differential SGMII clock to MAC.
Patch description, dt flags have been done in mainline Linux by
commit a2111c460c0c ("net: phy: dp83867: Add documentation for SGMII mode type")
and by commit 507ddd5c0d47 ("net: phy: dp83867: Add SGMII mode type switching")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit 27c3f70f3b ("net: phy: Increase link up delay in
genphy_update_link()") increased the per-iteration waiting time from
1ms to 50ms, without adjusting the timeout counter. This lead to the
timeout increasing from the typical 4 seconds to over three minutes.
Adjust the timeout counter evaluation by that factor of 50 to bring the
timeout back to the intended value.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes: net: phy: Increase link up delay in genphy_update_link() ("27c3f70f3b50")
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The driver now unconditionally prints some information that's not
universally useful. Replace printf with debug.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use either USXGMII or XFI in aquantia_set_proto and drop XGMII as a valid
protocol configuration. The PHY doesn't support it, it's just used as an
alias for one of the other two protocols.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add NC-SI to the usual phy handling. This makes two notable changes:
- Somewhat similar to a fixed phy, phy_connect() will create an NC-SI
phy if CONFIG_PHY_NCSI is defined.
- An early return is added to phy_read() and phy_write() to handle a
case like the NC-SI phy which does not define a bus.
Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This introduces support for the NC-SI protocol, modelled as a phy driver
for other ethernet drivers to consume.
NC-SI (Network Controller Sideband Interface) is a protocol to manage a
sideband connection to a proper network interface, for example a BMC
(Baseboard Management Controller) sharing the NIC of the host system.
Probing and configuration occurs by communicating with the "remote" NIC
via NC-SI control frames (Ethernet header 0x88f8).
This implementation is roughly based on the upstream Linux
implementation[0], with a reduced feature set and an emphasis on getting
a link up as fast as possible rather than probing the full possible
topology of the bus.
The current phy model relies on the network being "up", sending NC-SI
command frames via net_send_packet() and receiving them from the
net_loop() loop (added in a following patch).
The ncsi-pkt.h header[1] is copied from the Linux kernel for consistent
field definitions.
[0]: https://github.com/torvalds/linux/tree/master/net/ncsi
[1]: https://github.com/torvalds/linux/blob/master/net/ncsi/ncsi-pkt.h
Signed-off-by: Samuel Mendoza-Jonas <sam@mendozajonas.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On Xilinx ZynqMP revA board initial value of PHYCR register is 0x5448 which
means FORCE_LINK_GOOD is already setup. Origin code was doing write but the
new code is doing read/modify/write and keep this bit untouched. That's why
ethernet stop to work.
The patch is cleaning this bit when PHYCR value is composed.
Tested on Xilinx zcu102-revA and zcu104-rev1.0 boards.
Fixes: 37d6265f2b ("net: phy: dp83867: refactor rgmii configuration")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.
Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface. The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to avoid losing the 1st packet.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique. Add an optional DT property used
to change SMBus address if needed.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.
Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register. Keep that functionality too, so we don't break existing drivers.
Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix vendor name in MV88E61xx option description.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Support probing and init for 88E6071 switch.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On mv88E6071 the 'EDet' field offset, width and sense control
bits are different, adjust the driver to init the PHY control
register as needed. This fixes not working link detection and
tftp transfers.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
On 88E6071 chip the port status register bit field offsets
for duplex and link bits differ. Extend the driver to use
88E6071 specific offset values. The width of bit fields for
speed status differ, too. Adapt for proper port speed
detection on 88E6071.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Extend the driver to init switch register offsets from variables
instead of compile time macros and enable detection of 88E6071 and
compatible devices. Ethernet transfer (e.g. tftp) does not work yet,
so enable the registration of the 'indirect mii' bus for easier PHY
register access by 'mii' command.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The KSZ8081 PHY has a factory test mode which is set at the de-assertion
of the reset line based on the RXER (KSZ8081RNA/RND) or TXC
(KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a
pull-up, the factory test mode should be cleared by manually writing a 0
(according to the datasheet).
Create another ksz8081_config function to handle this case.
Suggested-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia quad-phys may take longer to initialize. This commit adds
a polling mechanism for a global alarm bit that tells if phy init
sequence is completed.
Signed-off-by: Florin Chiculita <florinlaurentiu.chiculita@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
I've noticed that in most cases when genphy_update_link() is called, the
ethernet driver (mt7628-eth in this case) fails with the first ethernet
packets. Resulting in a timeout of the first tftp command. Increasing
the delay in the link check look from 1 to 50 ms and moving it below the
BMSR register read fixes this issue, resulting in a stable ethernet
traffic, even after initial link autonogotiation.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Refactor SGMII configuration to group all settings together and reduce
number of MDIO transactions.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit 27708eb5481b ("net: phy: dp83867: IO impedance is not
dependent on RGMII delay") of mainline linux kernel.
The driver would only set the IO impedance value when RGMII internal delays
were enabled. There is no reason for this. Move the IO impedance block
out of the RGMII delay block.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay
handling") of mainline linux kernel.
The current code is assuming the reset default of the delay control
register was to have delay disabled. This is what the datasheet shows as
the register's initial value. However, that's not actually true: the
default is controlled by the PHY's pin strapping.
This patch:
- insures the other direction's delay is disabled If the interface mode is
selected as RX or TX delay only
- validates the delay values and fail if they are not in range
- checks if the board is strapped to have a delay and is configured to use
"rgmii" mode and warning is generated that "rgmii-id" should have been
used.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Based on commit 13c83cf8af0d ("net: phy: dp83867: Add ability to disable
output clock") of mainline linux kernel.
Generally, the output clock pin is only used for testing and only serves as
a source of RF noise after this. It could be used to daisy-chain PHYs, but
this is uncommon. Since the PHY can disable the output, make doing so an
option. I do this by adding another enumeration to the allowed values of
ti,clk-output-sel.
The code was not using the value DP83867_CLK_O_SEL_REF_CLK as one might
expect: to select the REF_CLK as the output. Rather it meant "keep clock
output setting as is", which, depending on PHY strapping, might not be
outputting REF_CLK.
Change this so DP83867_CLK_O_SEL_REF_CLK means enable REF_CLK output.
Omitting the property will leave the setting as is (which was the previous
behavior in this case).
Out of range values were silently converted into DP83867_CLK_O_SEL_REF_CLK.
Change this so they generate an error.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The driver ti.c is actually driver for TI DP83867x PHYs, so rename it
accordingly.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix 'mask' calculation in phy_connect() for phy addr '0'.
'mask' is getting set to '0xffffffff' for phy addr '0'
in phy_connect() whereas expected value is '0'.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reported-by: tetsu-aoki via github
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This converts the following to Kconfig:
CONFIG_SYS_CORTINA_FW_IN_MMC
CONFIG_SYS_CORTINA_FW_IN_NAND
CONFIG_SYS_CORTINA_FW_IN_NOR
CONFIG_SYS_CORTINA_FW_IN_REMOTE
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds support for gmiitorgmii converter.
This converter sits between the MAC and the external phy
MAC <==> GMII2RGMII <==> RGMII_PHY.
The ethernet driver probes this bridge and this bridge driver
probes real phy driver and invokes the real phy functionalities
as requested. This bridge just needs to be configured based on
real phy negotiated speed and duplex.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch define init routine for generic phy driver and registers it
using phy_register as this generic phy driver also needs to be relocated
incase of manual reloc.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Current code fails to probe some C45 PHYs that also respond to C22 reads.
This is the case for PHYs like Aquantia AQR112, Marvell 88X2242 (as
previously posted on the u-boot list).
If the PHY ID reads all 0s just ignore it and try the next devad.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
adds AQR112 and AQR412 to the list of supported PHYs using existing AQR
code.
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch is to use block layer to read from mmc in cortina
Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The code block reading the DT property for the clock output control was
before the phy's DT node pointer was set, so it could never work. Move
it after the node pointer is set.
Also store the unsigned 32-bit property into an unsigned value, not a
signed value, as the former will cause a problem if value overflows.
For instance, if one were to add 0xffffffff as a code to mean the clock
output should be turned off.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Janine Hagemann <j.hagemann@phytec.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When not using DM_ETH, these PHY settings are programmed with default
values hardcoded into the driver. When using DM_ETH, they should come
from the device tree. However, if the device tree does not have the
properties, the driver will silent use -1. Which is entirely out of
range, programs nonsense into the PHY's registers, and does not work.
Change this to use the same defaults as non-DM_ETH if the device tree is
lacking the properties.
As an alternative, the kernel driver for the phy will display an error
message and fail if the device tree is lacking.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Janine Hagemann <j.hagemann@phytec.de>
Cc: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There is a need to fill node before clk_output_sel is setup.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Reviewed-by: <hannes.schmelzer@br-automation.com>
Commit d397f7c45b ("net: phy: micrel: Separate KSZ9000 drivers from
KSZ8000 drivers") separated the KSZ8xxx and KSZ90x1 drivers and warns
that you shouldn't select both of them due to a device ID clash between
the KSZ9021 and the KS8721, asserting that "it is highly unlikely for a
system to contain both a KSZ8000 and a KSZ9000 PHY". Unfortunately
boards like the SAMA5D3xEK do contain both types of PHY, but fortunately
the Linux Micrel PHY driver provides a solution by using different PHY
ID and mask values to distinguish these chips.
This commit contains the following changes:
- The PHY ID and mask values for the KSZ9021 and the KS8721 now match
those used by the Linux driver.
- The warnings about not enabling both drivers have been removed.
- The description for PHY_MICREL_KSZ8XXX has been corrected (these are
10/100 PHYs, not GbE PHYs).
- PHY_MICREL_KSZ9021 and PHY_MICREL_KSZ9031 no longer select PHY_GIGE
since this is selected by PHY_MICREL_KSZ90X1.
- All of the relevant defconfig files have been updated now that
PHY_MICREL_KSZ8XXX does not default to 'Y'.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In some of the device trees that specify skew values for KSZ90x1 PHYs
the values are stored (incorrectly) in the MAC node, whereas in others
it is in an 'ethernet-phy' subnode. Previously the code would fail to
find and program these skew values, so this commit changes it to look
for an "ethernet-phy" subnode first, and revert to looking in the MAC
node if there isn't one.
The device trees affected (where the skew values are in a subnode) are
imx6qdl-icore-rqs.dtsi, r8a77970-eagle.dts, r8a77990-ebisu.dts,
r8a77995-draak.dts, salvator-common.dtsi, sama5d3xcm.dtsi,
sama5d3xcm_cmp.dtsi, socfpga_cyclone5_vining_fpga.dts,
socfpga_stratix10_socdk.dts and ulcb.dtsi. Before this change the skew
values in these device trees would be ignored.
The device trees where the skew values are in the MAC node are
socfpga_arria10_socdk.dtsi, socfpga_arria5_socdk.dts,
socfpga_cyclone5_de0_nano_soc.dts, socfpga_cyclone5_de10_nano.dts,
socfpga_cyclone5_de1_soc.dts, socfpga_cyclone5_is1.dts,
socfpga_cyclone5_socdk.dts, socfpga_cyclone5_sockit.dts. These should be
unaffected by this change.
The changes were tested on a sama5d3xcm.
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Commit ff7bd212cb ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.
The preceding commit c16e69f702 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).
This commit sorts out the resulting confusion in a consistent way by
making the following changes:
- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.
- Update the Micrel PHY driver to select the appropriate divisor for
both parts.
- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).
Signed-off-by: James Byrne <james.byrne@origamienergy.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For AQR405 in register 4.c441 bit 15 was override with 0. This caused the
phy to not negotiate at 2.5GB rate with mac. To avoid
this override it needed first to know the previous value of reg 4.c441
and set only bit 3.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Don't ignore return value of phy_probe() call as
the probe may fail and it needs to be reported.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch relocates the pointers inside phy_drivers incase
of manual reloc. Without this reloc, these points to invalid
pre relocation address and hence causes exception or hang.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When EEE is supported by the PHY and the driver allows it, libphy in the
kernel is configuring the PHY to stop receiving the xMII clock while it
is signaling LPI. While this (usually) works fine in the kernel this is
causing issues in U-Boot when rebooting from the linux kernel with this
bit set (without having the possibility to reset the PHY) where the PHY
suddenly stops working.
A new quirk is introduced to unconditionally reset this bit. If the
quirk is not enabled using the proper configuration symbol, the PHY state
is not changed.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
phy_reset should be called before autoneg is setup
The only boards using MV88E61XX_SWITCH are:
- alliedtelesis/SBx81LIFKW
- alliedtelesis/SBx81LIFXCAT
- gateworks/gw_ventana
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Print information about Aquantia system interface and firmware loaded
on the phy.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If System Interface protocol is USXGMII then enable USXGMII autoneg
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
According to the datasheet to access the extended registers we have to:
1. Write Register 31 Data = 0x0XYZ (Page 0xXYZ)
2. Read/Write the target Register Data
3. Write Register 31 Data = 0x0000 or 0xa42 (switch back to IEEE
Standard Registers)
Hook the missing functions so that we can use the `mdio rx/wx` command to
easily access the extended registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For KSZ9021, all skew register fields are 4-bit wide.
For KSZ9031, the clock skew register fields are 5-bit wide.
The common code in ksz90x1_of_config_group calculating the combined
register value checks if the requested value is above the maximum
and uses this maximum if so. The calculation of this maximum uses
the register width, but the check itself does not. It uses a hardcoded
value of 0xf, which is too low in case of the 5-bit clock (0x1f).
This detail was probably lost during driver unification.
Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps),
this silently results in 1860 (== +960ps) instead of the requested one.
Fix the check by using the bit width instead of hardcoded value(s).
Signed-off-by: Andreas Pretzsch <apr@cn-eng.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The phy devices can be accessed via clause 22 or via clause 45.
This information can be deduced when we read phy id. if the phy id
is read without giving any MDIO Manageable Device Address (MMD), then
it conforms to clause 22. otherwise it conforms to clause 45.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch moves fixed-link functionality code to a separate
routine inorder to make it more modular and cleaner.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When fixed-link phy is used subnode offset is used as phy address. This
number is bigger then space allocated for bus structure (allocated via
mdio_alloc).
bus->phymap[] array has PHY_MAX_ADDR size (32).
That's why writing bus->phymap[addr] where addr is < 0 or > PHY_MAX_ADDR
is causing write to memory which can caused full U-Boot crash.
The patch is checking if address is in correct range.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure. Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.
This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.
The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.
The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Part of the config is common between the VSC8584 and the VSC8574, so to
prepare for the upcoming support of VSC8574, use the phy_device.priv
pointer that will keep the function that holds code that is PHY-specific
and that should be called during config function.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with the
MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set
the blinking pattern of each of its 4 LEDs, supports hardware offloading
of MACsec and supports SyncE as well as HP Auto-MDIX detection.
This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.
The VSC8584 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.
The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
The revA of the VSC8584 PHY (which is not and will not be publicly
released) should NOT patch the firmware of the microcontroller or it'll
make things worse, the easiest way is just to not support it.
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
If the phy reports a valid firmware version and doesn't indicate
a fault, skip loading the firmware. This allows the same image
to be used on boards that have firmware storage and those that do not.
Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Aquantia phys have firmware that can be loaded automatically
from storage directly attached to the phy or via MDIO commands.
Add support for loading firmware from either a file or a
raw location on an MMC device.
Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The aquantia driver requires both CONFIG_PHY_GIGE and CONFIG_PHYLIB_10G.
Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The DP83867 when not properly bootstrapped - especially with LED_0 pin -
can enter N/A MODE4 for "port mirroring" feature.
To provide normal operation of the PHY, one needs not only to explicitly
disable the port mirroring feature, but as well stop some IC internal
testing (which disables RGMII communication).
To do that the STRAP_STS1 (0x006E) register must be read and RESERVED bit
11 examined. When it is set, the another RESERVED bit (11) at PHYCR
(0x0010) register must be clear to disable testing mode and enable RGMII
communication.
Thorough explanation of the problem can be found at following e2e thread:
"DP83867IR: Problem with RESERVED bits in PHY Control Register (PHYCR) -
Linux driver"
https://e2e.ti.com/support/interface/ethernet/f/903/p/571313/2096954#2096954
Based on commit ac6e058b75be ("net: phy: dp83867: Recover from "port mirroring"
N/A MODE4") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
This patch adds support for enabling or disabling the lane swapping
(called "port mirroring" in PHY's CFG4 register) feature of the DP83867
TI's PHY device.
One use case is when bootstrap configuration enables this feature (because
of e.g. LED_0 wrong wiring) so then one needs to disable it in software
(at u-boot/Linux).
Based on commit fc6d39c39581 ("net: phy: dp83867: Add lane swapping
support in the DP83867 TI's PHY driver") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use PHY API phy_get_ofnode() helper to get PHY DT node.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Use PHY API phy_get_ofnode() helper to get PHY DT node.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Now the UCLASS_ETH device "node" field is owerwritten by some network drivers in
case of Ethernet PHYs which are linked to UCLASS_ETH device using
"phy-handle" DT property and when Ethernet PHY driver needs to read some
additional information from DT. In such cases following happens (in
general):
- network drivers
priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
priv->interface);
<-- phydev is connected to dev which is UCLASS_ETH device
if (priv->phy_of_handle > 0)
dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
<-- phydev->dev->node is overwritten by phy-handle DT node
- PHY driver in .config() callback
int node = dev_of_offset(dev);
<-- PHY driver uses overwritten dev->node
const void *fdt = gd->fdt_blob;
if (fdtdec_get_bool(fdt, node, "property"))
...
As result, UCLASS_ETH device can't be used any more for DT accessing.
This patch adds additional ofnode node field to struct phy_device which can
be set explicitly by network drivers and used by PHY drivers, so
overwriting can be avoided. Also add helper function phy_get_ofnode()
which will check and return phy_device->node or dev_ofnode(phydev->dev) for
backward compatibility with existing drivers.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
We want to be able to include some other system headers in phy.h but
that requires us to have included common.h in the top-level first.
Also, common.h includes config.h as the first thing it does, so don't
include it directly.
Series-to: u-boot
Series-cc: Grygorii Strashko <grygorii.strashko@ti.com>
Seried-cc: ti
Series-process-log: sort, uniq
Cover-letter:
Prepare for net: phy: prevent uclass_eth device "node" field overwriting
Prepare for [1] so that it doesn't break the build for a bunch of
boards. There are a number of reasons this series broke the build
but none of them depend on changes in the series, so fix up those
situations ahead of applying that series.
[1] https://patchwork.ozlabs.org/cover/940104/
END
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Switch to use more generic ofnode API instead of FDT API.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
The data manual for DP83867IR/CR, SNLS484E[1], revised march 2017,
advises that strapping RX_DV/RX_CTRL pin in mode 1 and 2 is not
supported (see note below Table 5 (4-Level Strap Pins)).
It further advises that if a board has this pin strapped in mode 1 and
mode 2, then bit[7] of Configuration Register 4 (address 0x0031) must
be cleared to 0. This is to ensure proper operation of PHY.
Since it is not possible to detect in software if RX_DV/RX_CTRL pin is
incorrectly strapped, add a device-tree property to advertise this and
allow corrective action in software.
[1] http://www.ti.com/lit/ds/snls484e/snls484e.pdf
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add support for Cortina CS4223 10G PHY
- As per the CS4223 specs, an EEPROM module is
connected to the PHY. At startup the PHY reads
the firmware line and tries to load the firmware
into the internal memory.
- This driver reads the EEPROM status
and checks if firmware has been loaded
Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Some boards expect to find more than one phy while other boards are old
and need to be limited to a specific phy address. Only limit the phy
address for boards that opt in.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This patch reads phytype from property "xlnx,phy-type" instead
od simply looking for "phy-type". This is to be inline with
Linux and also fixes the issue of detecting it wrongly in
u-boot.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.
But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.
Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Update get_phy_id() implementation in cortina.c to check
for Cortina_phy by comparing device phy_id with cortina phy_id
instead of relying on presence of CORTINA macros.
This will allow get_phy_id to work with non-cortina phy devices
which might have same phy address as Cortina device but on
different bus.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
With CONFIG_DM_ETH enabled, aquantia driver compilation fails with
below error. This patch fixes the issue by including dm.h.
drivers/net/phy/aquantia.c: In function ‘aquantia_startup’:
drivers/net/phy/aquantia.c:73:21: error: dereferencing pointer to
incomplete
type ‘struct udevice’
phydev->dev->name);
^~
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Setting PHY_RTL8211E_PINE64_GIGABIT_FIX forces internal rx/tx delays off
on the PHY, as well as flipping some magical undocumented bits. The
magic number comes from the Pine64 engineering team, presumably as a
proxy from Realtek. This configuration fixes the throughput on some
Pine64 models. Packet loss of up to 60-70% has been observed without
this.
Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
CONFIG_PHY_ADDR is used for old-style configuration. This makes
impossible changing the PHY address, if multiple boards share a same
config header file (for example include/configs/sunxi-common.h).
Moving this to Kconfig helps overcoming this issue. It's defined
as entry inside PHYLIB section.
After the implemention, moveconfig was run. The issues are:
- edb9315a - CONFIG_PHYLIB is not enabled. Entry is
deleted.
- ds414 - CONFIG_PHYLIB is in incompatible format:
{ 0x1, 0x0 }. This entry is also deleted.
- devkit3250 - The PHY_ADDR is in hex format (0x1F).
Manually CONFIG_PHY_ADDR=31 is added in
the defconfig.
After the changes the suspicious defconfigs passes building.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Fix some style violations in the generic PHY management code.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Commit 68e6ecadc5 ("net: phy: marvell 88e151x: Fix handling of RGMII
interface types") fixed the initialization of 88e151x phys, but made it
so that interfaces of type PHY_INTERFACE_MODE_RGMII had both RX and TX
delay bits cleared. The default (like in m88e1111s_config) is to have
both bits set.
Hence, this patch changes the behavior in the PHY_INTERFACE_MODE_RGMII
case so that both bits are set.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Fix some style violations (mostly wrong indentions) in the Marvell PHY
driver.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
There is no value to enable phylib without networking support.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Add a b53_reg read/write command which allows inspecting the switch
registers. Because the Broadcom BCM53xx registers have different sizes,
we need to split the accesses in 8, 16, 32, 48 or 64 bits to obtain
expected results.
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add a minimalistic Broadcom BCM53xx (roboswitch) switch driver similar
to the Marvell MV88E617x. This takes care of configuring the minimum
amount out of the switch hardware such that each user visible port
(configurable) and the CPU port can forward packets between each other
while preserving isolation with other ports.
This is useful for e.g: the Lamobo R1 board featuring a Broadcom
BCM53125 switch.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Since the return value is a signed int, if the leading MSB of rdreg is a 1,
it will get signed extended and will return a negative value which is an
error even though we read the correct value.
Fixes: dfcc496ed7 ("net: mii: Changes not made by spatch")
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit allows extended Marvell registers to be read with:
foo > mdio rx FEC 3.10
Reading from bus FEC
PHY at address 0:
3.16 - 0x1063
foo > mdio wx FEC 3.10 0x1011
The above code changes the way ETH connector LEDs blink.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This patch is ported from the Linux patch posted at [1] and applied to
net tree as commit f1e2400a80ff.
The purpose of this change is to fix the incorrect detection of the link
partner (LP) advertised capabilities which sometimes happens with this PHY
(roughly 1 time in a dozen)
This issue may cause the link to be negotiated at 10Mbps/Full or
10Mbps/Half when 100MBps/Full is actually possible. In some case, the link
is even completely broken and no communication is possible.
To detect the corruption, we must look for a magic undocumented bit in the
WOL bank (hint given by the SoC vendor kernel) but this is not enough to
cover all cases. We also have to look at the LPA ack. If the LP supports
Aneg but did not ack our base code when aneg is completed, we assume
something went wrong.
The detection of a corrupted LPA triggers a restart of the aneg process.
This solves the problem but may take up to 6 retries to complete.
[1] https://lkml.kernel.org/r/20171208110811.30789-1-jbrunet@baylibre.com
Fixes: 8995a96d1d ("net: phy: Add Amlogic Meson GXL Internal PHY support")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The Amlogic Meson GXL/GXM families embeds an internal RMII Ethernet PHY.
The PHY acts as a generic PHY but needs a slight configuration right
before it's configuration.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Update the Micrel KSZ90x1 driver for a live tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
All these places seem to inherit the codes from the MMC driver where
a FIXME was put in the comment. However the correct operation after
read should be cache invalidate, not flush.
The underlying drivers should be responsible for the cache operation.
Remove these codes completely.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: York Sun <york.sun@nxp.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: York Sun <york.sun@nxp.com>
The old logic always enabled the TX-delay when the phy-mode was set to
PHY_INTERFACE_MODE_RGMII. With this patch we enable the TX delay for
PHY_INTERFACE_MODE_RGMII_ID and PHY_INTERFACE_MODE_RGMII_TXID and
disable it for PHY_INTERFACE_MODE_RGMII.
Based on a similar change made in the Linux Realtek PHY driver
by Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: York Sun <york.sun@nxp.com>
We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.
Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.
Suggested-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
The environment variable "disable_giga" can now be used to disable
1000baseTx on the Micrel's KSZ9031.
Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Added the AFE (Analog Front End) settings for stability to the
Broadcom Cygnus phy. This improves the time take to perform
auto negotiation.
Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The correct option is PHY_MICREL_KSZ90X1, but some configs still
select the 9021 and 9031 options, which are deprecated.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
There should be no longer be any ksz9000 users that pick up the PHY
driver from ksz8xxx, so remove ksz9000 remnants from there.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The KS8721BL and KSZ9021 PHYs are software-incompatible, yet they
share the same ID. Drivers for bothe PHYs cannot safely coexist, so
the solution was to use #ifdefs to select between the two drivers.
As a result KSZ9031, which has a unique ID, is now caught in the
crossfire. Unless CONFIG_PHY_MICREL_KSZ9031 is defined, the KSZ9031
will not function properly, as some essential configuration code is
ifdef'd-out.
To prevent such situations, move the KSZ9000 drivers to a separate
file, and place them under a separate Kconfig option. While it is
possible to enable both KSZ8000 and KSZ9000 drivers at the same time,
the assumption is that it is highly unlikely for a system to contain
both a KSZ8000 and a KSZ9000 PHY, and that only one of the drivers
will be enabled at any given time.
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Alexandru Gagniuc <alex.g@adaptrum.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
phy_device_create(..) sets the addr of phy_device with a sane value.
There is no need overwrite it.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As part of preparation for nand DM conversion the new API has been
introduced to remove direct access to nand_info array. So, use it here
instead of accessing to nand_info array directly
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Commit a058052c changed the generic phy_reset() to clear all bits in
BMCR. This inevitably clears the ANEG bit. m88e1145 requires any
change to ANEG bit to be followed by a software reset. This seems to
be different from other PHYs. Implement read-modify-write procedure
for this PHY init.
Signed-off-by: York Sun <york.sun@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The 88E1518 code is programming the wrong registers for rgmii-id,
rgmii-txid and rgmii-rxid interfaces.
Since the PHY defaults to rgmii-id, it would appear that the code
was previously only used with sgmii and rgmii-id interfaces.
Tested on 88E1512 PHY in rgmii-id mode which is from the same family
as 88E1518.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This change migrate the following configuration options for Kconfig:
* PHY_GIGE, indicates that a controller (with an appropriate PHY) is
Gigabit capable and enables extra support in the miiutil for
parsing the status of Gigabit PHYs
* adds configuration options for Micrel KSZ9021 and KSZ9031 GbE PHYs,
which previously had to enabled through a board-specific config file
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.
Signed-off-by: Simon Glass <sjg@chromium.org>
The variable 'res' may be unused uninitialized if our call to
mv88e61xx_port_read (register read) fails and we goto the error
handling section. In this case we set 'res' to -EIO to indicate why we
failed.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chris Packham <judge.packham@gmail.com>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This patch adds support for having a "fixed-link" to some other MAC
(like some embedded switch-device).
For this purpose we introduce a new phy-driver, called "Fixed PHY".
Fixed PHY works only with CONFIG_DM_ETH enabled, since the fixed-link is
described with a subnode below ethernet interface.
Most ethernet drivers (unfortunately not all are following same scheme
for searching/attaching phys) are calling "phy_connect(...)" for getting
a phy-device.
At this point we link in, we search here for a subnode called "fixed-
link", once found we start phy_device_create(...) with the special phy-
id PHY_FIXED_ID (0xa5a55a5a).
During init the "Fixed PHY" driver has registered with this id and now
gets probed, during probe we get all the details about fixed-link out of
dts, later on the phy reports this values.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
