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20f7ea4c35
Based on commit c11669a2757e ("net: phy: dp83867: Rework delay rgmii delay
handling") of mainline linux kernel.
The current code is assuming the reset default of the delay control
register was to have delay disabled. This is what the datasheet shows as
the register's initial value. However, that's not actually true: the
default is controlled by the PHY's pin strapping.
This patch:
- insures the other direction's delay is disabled If the interface mode is
selected as RX or TX delay only
- validates the delay values and fail if they are not in range
- checks if the board is strapped to have a delay and is configured to use
"rgmii" mode and warning is generated that "rgmii-id" should have been
used.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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| .. | ||
| aquantia.c | ||
| atheros.c | ||
| b53.c | ||
| broadcom.c | ||
| cortina.c | ||
| davicom.c | ||
| dp83867.c | ||
| et1011c.c | ||
| fixed.c | ||
| generic_10g.c | ||
| Kconfig | ||
| lxt.c | ||
| Makefile | ||
| marvell.c | ||
| meson-gxl.c | ||
| micrel_ksz8xxx.c | ||
| micrel_ksz90x1.c | ||
| miiphybb.c | ||
| mscc.c | ||
| mv88e61xx.c | ||
| mv88e6352.c | ||
| natsemi.c | ||
| phy.c | ||
| realtek.c | ||
| smsc.c | ||
| teranetics.c | ||
| vitesse.c | ||
| xilinx_gmii2rgmii.c | ||
| xilinx_phy.c | ||