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phy: atheros: Clarify the intention of ar8021_config

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Debug register 5 contains TX_CLK DELAY at bit 8 and reserved values at
the other bit positions, just like the other PHYs in the family do.
Therefore, it is not necessary to hardcode the reserved values, but
instead simply follow the read-modify-write procedure from the common
function.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Vladimir Oltean 2020-05-07 00:11:52 +02:00 committed by Tom Rini
parent 13114f38e2
commit 4d4e4cf779
1 changed files with 4 additions and 4 deletions
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8
drivers/net/phy/atheros.c
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@ -56,10 +56,10 @@ static void ar803x_enable_tx_delay(struct phy_device *phydev, bool on)
static int ar8021_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200);
phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG,
AR803x_DEBUG_REG_5);
phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, 0x3D47);
phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR,
BMCR_ANENABLE | BMCR_ANRESTART);
ar803x_enable_tx_delay(phydev, true);
phydev->supported = phydev->drv->features;
return 0;