Commit graph

64 commits

Author SHA1 Message Date
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00
Masahiro Yamada
377e1048d3 board: powerpc: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
2013-11-01 11:42:12 -04:00
Valentin Longchamp
935b402eae fsl/mpc85xx: define common serdes_clock_to_string function
This allows to share some common code for the boards that use a corenet
base SoC.

Two different versions of the function are available in
fsl_corenet_serdes.c and fsl_corenet2_serdes.c files.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: fix t1040qds.c]
Acked-by: York Sun <yorksun@freescale.com>
2013-10-24 09:36:18 -07:00
Priyanka Jain
0dd38a35f4 powerpc: Fix CamelCase warnings in DDR related code
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2013-10-16 16:15:16 -07:00
Zhao Qiang
ffee1dde3c SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII mode
Fix PHY addresses for QSGMII Riser Card working in
SGMII mode on board P3041/P5020/P4080/P5040/B4860.

QSGMII Riser Card can work in SGMII mode, but
having the different PHY addresses.
So the following steps should be done:
	1. Confirm whether QSGMII Riser Card is used.
	2. If yes, set the proper PHY address.
Generally, the function is_qsgmii_riser_card() is
for step 1, and set_sgmii_phy() for step 2.

However, there are still some special situations,
take P5040 and B4860 as examples, the PHY addresses
need to be changed when serdes protocol is changed,
so it is necessary to confirm the protocol before
setting PHY addresses.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16 16:13:11 -07:00
Zhao Qiang
d56898249c Corenet/p5040/SGMII:fix the problem for SGMII5/6
SGMII5/6 and SGMII7/8 are not on the same slot on P5040
according to the serdes protocol.
So it is not proper to organize SGMII5/6 and SGMII7/8
on one bus and SGMII5/6 can't work.
So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for
SGMII5/6

Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16 16:13:11 -07:00
York Sun
c63e137014 powerpc/mpc8xxx: Add memory reset control
JEDEC spec requires the clocks to be stable before deasserting reset
signal for RDIMMs. Clocks start when any chip select is enabled and
clock control register is set. This patch also adds the interface to
toggle memory reset signal if needed by the boards.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:39 -07:00
York Sun
f165bc3528 powerpc/corenet: Move RCW print to cpu.c
The RCW print is common for all corenet platforms. Not necessary to ducplicate
in each board file.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-08-09 12:41:38 -07:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Shaohui Xie
e14cdc0a69 powerpc/p5040: fix mdio mux for 10G port
Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have wrong mdio mux.
So we use dynamic index for 10G ports instead of hardcoded enum value
when doing mdio mux for 10G ports.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:14 -05:00
Shaohui Xie
94025b1cd8 powerpc/p5040: enable PBL tool support
Provided a default RCW for P5040, then it can use PBL to build
ramboot image.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
Anatolij Gustschin
b1e6c4c3d4 Fix references to the documentation files
Many boot image configuration files refer to the
appropriate documentation file, but these references
contain typos in the directory and file name. Fix
them. Also fix reference to doc/README.SPL file.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2013-05-10 08:16:33 -04:00
Simon Glass
67ac13b1b9 ppc: Move lbc_clk and cpu to arch_global_data
Move these fields into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update for bsc9132qds.c, b4860qds.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-02-04 09:04:57 -05:00
Valentin Longchamp
c4d580797d powerpc/p2041: add RCW file for P2041RDB
All the dev boards of Freescale's QorIQ family have a RCW that is
supported by the u-boot.pbl build target. This patch adds one for the
P2041 dev board.

This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the
P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-30 11:25:12 -06:00
York Sun
765ad3cf4d powerpc/corenet_ds: Update DDR timing for single-rank DIMMs
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed
800, 900, 1000, 1200, 1300MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
d31e53b42c powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of
P3041DS/P5020DS ("Hydra") reference board.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-11-27 18:28:06 -06:00
Timur Tabi
61fc52b660 powerpc/85xx: get rid of enum board_slots in P4080 MDIO driver
enum board_slots contained six values, where SLOT1 == 1, SLOT2 == 2, and
so on.  This is pointless, so remove it.  Also move the lane_to_slot[]
array to the top of the file so that it can be used by other functions.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:19 -05:00
Shaohui Xie
5d898a00f3 powerpc/CoreNet: add tool to support pbl image build.
Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-23 10:24:16 -05:00
Timur Tabi
5d065c3e10 powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during boot
Most 85xx boards can be built as a 32-bit or a 36-bit.  Current code sometimes
displays which of these is actually built, but it's inconsistent.  This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used.  Not only that, but each board includes code that displays
the message, so there is duplication.

The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time.  The board-specific code is
deleted.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-04-24 23:58:34 -05:00
Troy Kisky
9fafe7dab9 net: phy: make board_phy_config responsible for calling drv->config
Boards may have things they want done before or after normal phy config.
Letting the boards call drv->config allows them more flexibilty.
Boards affected by this change are corenet_ds and mpc8544ds.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2012-02-27 21:19:25 +01:00
Roy Zang
afc52db2f7 powerpc/QorIQ: fix network frame manager TBI PHY address settings
TBI PHY address (TBIPA) register has been set in general frame manager
phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c

So remove the duplicate code on QorIQ frame manager Ethernet related
platforms, which include Hydra board, P4080DS board and P2041rdb board.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Cc: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-11-08 08:18:16 -06:00
Timur Tabi
a836626cc4 powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9)
The work-around for P4080 erratum SERDES9 says that the SERDES receiver
lanes should be reset after the XAUI starts tranmitting alignment signals.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-20 16:01:37 -05:00
Shengzhou Liu
2a523f5240 fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers
Add common function fdt_set_node_status() to assist in various locations
that we set a nodes status.  This function utilizes the status values
that are part of the EPAPR spec (on power.org).

fdt_set_status_by_alias() is based on fdt_set_node_status() but uses an
alias string to identify the node to update.

We also add some shortcut functions to help the common cases of setting
"okay" and "disabled":

	fdt_status_okay()
	fdt_status_disabled()
	fdt_status_okay_by_alias()
	fdt_status_disabled_by_alias()

Finally, we fixup the corenet_ds ethernet code which previously had
a function by the same name that can be replaced with the new helpers.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Gerald Van Baren <vanbaren@cideas.com>
2011-10-18 00:36:55 -05:00
Mike Frysinger
464c79207c punt unused clean/distclean targets
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used.  Punt them all.

MAKEALL didn't report any errors related to this that I could see.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-10-15 22:20:36 +02:00
York Sun
712cf7ab0b powerpc/mpc8xxx: Merge entries in DDR speed table
It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.

Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.

Removed ODT overriding for P2020DS as it is not necessary.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-09 17:57:53 -05:00
Kumar Gala
360275b362 powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
We currently support 4 SoC/Boards from the P-Series of QorIQ SoCs that
are based on the 'CoreNet' Architecture: P2041RDB, P3041DS, P4080DS, and
P5020DS.  There is a significant amount of commonality shared between
these boards that we can refactor into common code:

* Initial LAW setup
* Initial TLB setup
* PCI setup

We start by moving the shared code between P3041DS, P4080DS, and P5020DS
into a common directory to be shared with other P-Series CoreNet boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
9ec8dec539 powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
RDIMM has different timing parameters from UDIMM. Create new tables for
RDIMMs. Single-, dual- and quad-rank RDIMMs have been verified with speeds
from 800 to 1333MT/s. Speed table expands to include 1600MT/s for future
use. Single- and quad-rank RDIMM entries are copied into UDIMM tables for
future use.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
York Sun
cda1de21de powerpc/mpc8xxx: Move DDR RCW overriding to common code
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:06 -05:00
Kumar Gala
5471370b43 powerpc/85xx: Cleanup extern in corenet_ds board code
Move extern of pci_of_setup() into corenet_ds.h

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Timur Tabi
cba4614862 powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS &
P5020DS ("Hydra").

The lane_to_slot[] array is initialized dynamically, since board switches
can be used to control the muxing of SERDES lanes to slots.

The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate
slot.  The SERDES configuration is queried to help determine the routing
between MACs and slot/phy combination.

If a XAUI card is inserted, muxing for that card is enabled and never
turned off.  The PHY address for the 10G XAUI card depends on the slot in
which it's inserted.  If it's in slot 1, the address is 4.  If it's in
slot 2, the address is 0.

Update the MDIO routing in the P3041DS and P5020DS device trees based on
the board-level muxing.  The SERDES configuration determines which
SGMII/XGMII boards are located in which slots, and so the MDIO bus needs
to be muxed correctly whenever talking to a PHY connected to any Fman MAC.
The Fman Ethernet nodes in the device tree also need to be routed to the
correct PHYs.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Andy Fleming
2915609a91 powerpc/85xx: Add FMan ethernet support to P4080DS
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P4080DS.

The board supports add-on cards for SGMII and XAUI functionality.  Which
slots on the board these cards are in is a function of the SERDES option
selected and muxes on the board.

Additionally because of the high-configurablity which MDIO bus one is
connected to is "selected" via an FPGA register.  We create dummy MDIO
bus for the phy layer and hide the mux manipulation in this dummy layer.

Add fman fdt helper function in board common code it'll be used by several
freescale boards that do various muxing of the MDIO signals based on which
controller/interface one is trying to talk to.

Removed CONFIG_SYS_FMAN_FW as its not used anywhere.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Kumar Gala
86df5142a1 powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
We shouldn't be setting execute permissions on TLB entries that will not
actually have any code run from them.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-09-29 19:01:05 -05:00
Shaohui Xie
a3a3e7b2c3 powerpc/85xx: enable USB2 gadget mode for corenet ds board
to make USB2 worked in gadget mode, we need to set it's 'dr_mode' to
'peripheral' in hwconfig, but driver starts scan from 'usb1', it'll break
out if it cannot find 'usb1', so drop the 'else' clause to make driver scan
all the 'usbx'.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:43 -05:00
Wolfgang Denk
21cd5815a7 MPC8xxx: drop redundant boot messages
Current code would print RAM size information like this:

	DRAM:  DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)

Turn a number of printf()s into debug() to get rid of the redundant
"DDR: " string like this:

	DRAM:  256 MiB (DDR1, 64-bit, CL=2, ECC off)

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:39 -05:00
Stephen George
f110fe940c powerpc/85xx: Adding configuration for DCSRCR to enable 32M access
Configuring DCSRCR to define the DCSR space to be 1G instead
of the default 4M. DCSRCR only allows selection of either 4M
or 1G.
Most DCSR registers are within 4M but the Nexus trace buffer
is located at offset 16M within the DCSR.

Configuring the LAW to be 32M to allow access to the Nexus
trace buffer. No TLB modification is required since accessing
the Nexus trace buffer from within u-boot is not required.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-29 08:53:37 -05:00
York Sun
939e5bf9b3 powerpc/mpc85xx: Display a warning for unsupported DDR data rates
If DDR initialziation uses a speed table and the speed is not matched,
print a warning message instead of silently ignoring.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
York Sun
79fa00af5d powerpc/corenet_ds: Fix RCW overriding for RDIMM
Allow overriding RCW for all RDIMM, not only quad-rank ones.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:20 -05:00
Kumar Gala
58b2f96e38 powerpc/85xx: Fix compile errors if CONFIG_SYS_DPAA_QBMAN isn't set
Add ifdef protection for qp_info and liodn associated with Q/BMan.  Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.

Also add protection around setup_portals() call in corenet_ds board
code.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Kumar Gala
be1ff615ea powerpc/85xx: Fix compile errors if CONFIG_SYS_{B,Q}MAN_MEM_PHYS aren't set
Add ifdef protection in LAW & TLB code to handle the case in which
CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a
build.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-07-11 13:24:19 -05:00
Kumar Gala
e02aea61cb powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)
The P3041DS & P5020DS boards are almost identical (except for the
processor in them).  Additionally they are based on the P4080DS board
design so we use the some board code for all 3 boards.

Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have
meaning on P3041DS/P5020DS.  We utilize some of these for SERDES clock
configuration.

Additionally, the P3041DS/P5020DS support NAND.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-27 22:29:04 -05:00
Shaohui Xie
2a9fab82b7 powerpc/85xx: Add PBL boot from SPI flash support on P4080DS
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and
PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as
1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from
CPC after PBL completes RCW and PBI phases.

Signed-off-by: Chunhe Lan <b25806@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Shaohui Xie <b21989@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-10 11:17:55 -05:00
York Sun
dea8bd627c powerpc/85xx: Update fixed DDR3 timing table for P4080DS
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Kumar Gala
c39f44dc6f powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing.  The only variations are in how many
controllers or DIMMs per controller exist.  To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.

We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:41 -05:00
Kumar Gala
5df4b0ad0d powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq()
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq().  If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Kumar Gala
561e710a97 powerpc: Move cpu specific lmb reserve to arch_lmb_reserve
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems.  We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Kumar Gala
f0f899432e powerpc/85xx: Declare fsl_ddr_set_memctl_regs in <asm/fsl_ddr_sdram.h>
Remove declerations of fsl_ddr_set_memctl_regs in board files with and
place it into a common header.

Based on patch from Poonam Aggrwal.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
Kumar Gala
5cfbc458d4 powerpc/85xx: Remove DATARATE_*_MHZ defines in static ddr init
Rather than having #defines DATARATE_*_MHZ, lets just match what we do on
the SPD code and convert the DDR frequency into MHZ and just compare
with a constant.

Based on patch from Poonam Aggrwal.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-04-04 09:24:40 -05:00
York Sun
d89a976c13 powerpc/corenet_ds: revise platform dependent parameters
This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based
on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-03-05 10:13:50 -06:00
York Sun
59a4089f82 corenet_ds: pick the middle value for all tested timing parameters
For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent.
The best values should be picked up from the middle of all working
combinations. This patch updates the table with confirmed values tested on
Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s,
900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s,
1200MT/s, 1000MT/s.

Signed-off-by: York Sun <yorksun@freescale.com>
2011-03-05 10:13:50 -06:00
York Sun
6b06d7dc07 corenet_ds: Extend board specific parameters
Extend board specific parameters to include cpo, write leveling override
Extend write leveling sample to 0xf
Adding rcw overrid for quad-rank RDIMMs

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-01-19 22:58:24 -06:00