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powerpc/85xx: Update fixed DDR3 timing table for P4080DS

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Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
York Sun 2011-02-04 13:57:59 -08:00 committed by Kumar Gala
parent 7639675131
commit dea8bd627c
1 changed files with 8 additions and 8 deletions
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16
board/freescale/corenet_ds/p4080ds_ddr.c
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@ -334,17 +334,17 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_1200_2nd = {
};
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{800, 900, &ddr_cfg_regs_800},
{900, 1000, &ddr_cfg_regs_900},
{1000, 1200, &ddr_cfg_regs_1000},
{1200, 1300, &ddr_cfg_regs_1200},
{750, 850, &ddr_cfg_regs_800},
{850, 950, &ddr_cfg_regs_900},
{950, 1050, &ddr_cfg_regs_1000},
{1050, 1250, &ddr_cfg_regs_1200},
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{800, 900, &ddr_cfg_regs_800_2nd},
{900, 1000, &ddr_cfg_regs_900_2nd},
{1000, 1200, &ddr_cfg_regs_1000_2nd},
{1200, 1300, &ddr_cfg_regs_1200_2nd},
{750, 850, &ddr_cfg_regs_800_2nd},
{850, 950, &ddr_cfg_regs_900_2nd},
{950, 1050, &ddr_cfg_regs_1000_2nd},
{1050, 1250, &ddr_cfg_regs_1200_2nd},
{0, 0, NULL}
};