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cba4614862
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS &
P5020DS ("Hydra").
The lane_to_slot[] array is initialized dynamically, since board switches
can be used to control the muxing of SERDES lanes to slots.
The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate
slot. The SERDES configuration is queried to help determine the routing
between MACs and slot/phy combination.
If a XAUI card is inserted, muxing for that card is enabled and never
turned off. The PHY address for the 10G XAUI card depends on the slot in
which it's inserted. If it's in slot 1, the address is 4. If it's in
slot 2, the address is 0.
Update the MDIO routing in the P3041DS and P5020DS device trees based on
the board-level muxing. The SERDES configuration determines which
SGMII/XGMII boards are located in which slots, and so the MDIO bus needs
to be muxed correctly whenever talking to a PHY connected to any Fman MAC.
The Fman Ethernet nodes in the device tree also need to be routed to the
correct PHYs.
Removed CONFIG_SYS_FMAN_FW as its not used anywhere.
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| .. | ||
| corenet_ds.c | ||
| corenet_ds.h | ||
| ddr.c | ||
| eth_hydra.c | ||
| eth_p4080.c | ||
| law.c | ||
| Makefile | ||
| p3041ds_ddr.c | ||
| p4080ds_ddr.c | ||
| p5020ds_ddr.c | ||
| pci.c | ||
| tlb.c | ||