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293 commits

Author SHA1 Message Date
Simon Glass
d9d7c20b73 treewide: Drop bootm_headers_t typedef
This is not needed and we should avoid typedefs. Use the struct instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-29 16:07:57 -04:00
Andrew Davis
b661c1bc92 arm: mach-k3: security: Remove certificate if detected on GP device
If the device is a GP and we detect a signing certificate then remove it.
It would fail to authenticate otherwise as the device is GP and has no
secure authentication services in SYSFW.

This shouldn't happen often as trying to boot signed images on GP devices
doesn't make much sense, but if we run into a signed image we should at
least try to ignore the certificate and boot the image anyway. This could
help with users of GP devices who only have HS images available.

If this does happen, print a nice big warning.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-08-04 15:32:20 -04:00
Andrew Davis
a0379c6fe3 arm: mach-k3: security: Bypass image signing at runtime for GP devices
We can skip the image authentication check at runtime if the device is GP.
This reduces the delta between GP and HS U-Boot builds. End goal is
to re-unify the two build types into one build that can run on all
device types.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-04 15:32:20 -04:00
Andrew Davis
e1ef04fb3e arm: mach-k3: security: Allow signing bypass if type is HS-FS
On HS-FS devices signing boot images is optional. To ease use
we check if we are HS-FS and if no certificate is attached
to the image we skip the authentication step with a warning
that this will fail when the device is set to security enforcing.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-08-04 15:32:20 -04:00
Andrew Davis
d1c079557f arm: mach-k3: Add support for device type detection
K3 SoCs are available in a number of device types such as
GP, HS-FS, EMU, etc. Like OMAP SoCs we can detect this at runtime
and should print this out as part of the SoC information line.
We add this as part of the common.c file as it will be used
to also modify our security state early in the device boot.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-08-04 15:32:20 -04:00
Andrew Davis
121596a98f arm: k3: config.mk: Read software revision information from file on HS
Read the swrv.txt file from the TI Security Development Tools when
TI_SECURE_DEVICE is enabled. This allows us to set our software
revision in one place and have it used by all the tools that create
TI x509 boot certificates.

Signed-off-by: Andrew Davis <afd@ti.com>
2022-07-25 14:57:27 -04:00
Yogesh Siraswar
0019427251 k3_gen_x509_cert: Make SWRV configurable for anti-rollback protection
The x509 certificate SWRV is currently hard-coded to 0. This need to be
updated to 1 for j721e 1.1, j7200 and am64x. It is don't care for other
k3 devices.

Added new config K3_X509_SWRV to k3. Default is set to 1.

Signed-off-by: Yogesh Siraswar <yogeshs@ti.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
2022-07-25 14:57:27 -04:00
Andrew Davis
080fe39b8c arm: mach-k3: Remove ROM firewalls on GP devices
This isn't strictly needed as these firewalls should all be disabled on
GP, but it also doesn't hurt, so do this unconditionally to remove this
use of CONFIG_TI_SECURE_DEVICE.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 14:57:27 -04:00
Andrew Davis
80b93bb71c arm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654
The first AM6x device was the AM654x, but being the first we named it
just AM6, since more devices have come out with this same prefix we
should switch it to the normal convention of using the full name of the
first compatibility device the series. This makes what device we are
talking about more clear and matches all the K3 devices added since.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 13:02:04 -04:00
Andrew Davis
46da163b72 arm: mach-k3: Only build init files for SPL
The content of these files are only used in SPL builds. The contents are
already ifdef for the same, remove that and only include the whole file
in the build when building for SPL.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 13:02:04 -04:00
Matt Ranostay
cab8510821 armv8: mach-k3: correct define checking for AM625/AM642 memory maps
Using CONFIG_IS_ENABLED breaks accessing memory map structure when
doing a A53 SPL build for AM625 and AM642 platforms. This is due to
'abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y''
in which there is no CONFIG_SPL_SOC_K3_AM625/CONFIG_SPL_SOC_K3_AM642
defined in the configuration.

For the A53 SPL builds on these platform to access the memory mapping
which it will need for enabling the mmu/cache it must use #if defined(X)
checks and not CONFIG_IS_ENABLED.

Cc: Suman Anna <s-anna@ti.com>
Cc: Neha Francis <n-francis@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-25 13:02:04 -04:00
Julien Panis
169582025a arm64: mach-k3: am625_init: Probe ESM nodes
On AM62x devices, main ESM error event outputs can be routed to
MCU ESM as inputs. So, two ESM device nodes are expected in the
device tree : one for main ESM and another one for MCU ESM.
MCU ESM error output can trigger the reset logic to reset
the device when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is
set to '0'.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2022-07-25 09:38:47 -04:00
Georgi Vlaev
a04bbb83b4 arm: mach-k3: common: Use ddr_init in spl_enable_dcache
The spl_enable_dcache() function calls dram_init_banksize()
to get the total memory size. Normally the dram_init_banksize()
setups the memory banks, while the total size is reported
by ddr_init(). This worked so far for K3 since we set the
gd->ram_size in dram_init_banksize() as well.

Signed-off-by: Georgi Vlaev <g-vlaev@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-07-06 14:30:08 -04:00
Vaishnav Achath
c16b4f14a3 arm: k3: j721e: add dynamic sf bus override support for j721e
implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs()
lookup functions according to bootmode selection, so as to support
both QSPI and OSPI boot using the same build.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
2022-07-06 14:30:08 -04:00
Tom Rini
52af0101be Merge branch 'master' into next
Merge in v2022.07-rc5.
2022-06-20 14:40:59 -04:00
Christian Gmeiner
761157d310 arch: arm: mach-k3: am642_init: bring back MCU_PADCFG_MMR1 unlock
Without this register unlock it is not possible to configure the
pinmux used for mcu spi0.

Fixes: 92e46092f2 ("arch: arm: mach-k3: am642_init: Probe ESM nodes")
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2022-06-16 15:22:54 -04:00
Suman Anna
900349b7dd board: ti: Introduce the basic files to support AM62 SK board
Add basic support for AM62 SK. This has 2GB DDR.
Note that stack for R5 SPL is in OCRAM @ 0x7000ffff so that is away from
BSS and does not step on BSS section

Add only the bare minimum required to support UART and SD.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:33 -04:00
Suman Anna
4b8903a999 arm: mach-k3: am62: Introduce autogenerated SoC data
Introduce autogenerated SoC data support clk and device data for the
AM62. Hook it upto to power-domain and clk frameworks of U-Boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-06-10 13:37:32 -04:00
Suman Anna
d98e860051 arm: mach-k3: Introduce the basic files to support AM62
The AM62 SoC family is the follow on AM335x built on K3 Multicore SoC
architecture platform, providing ultra-low-power modes, dual display,
multi-sensor edge compute, security and other BOM-saving integration.
The AM62 SoC targets broad market to enable applications such as
Industrial HMI, PLC/CNC/Robot control, Medical Equipment, Building
Automation, Appliances and more.

Some highlights of this SoC are:

* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
  Pin-to-pin compatible options for single and quad core are available.
* Cortex-M4F for general-purpose or safety usage.
* Dual display support, providing 24-bit RBG parallel interface and
  OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
  resolution.
* Selectable GPUsupport, up to 8GFLOPS, providing better user experience
  in 3D graphic display case and Android.
* PRU(Programmable Realtime Unit) support for customized programmable
  interfaces/IOs.
* Integrated Giga-bit Ethernet switch supporting up to a total of two
  external ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
  NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
  1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized System Controller for Security, Power, and
  Resource Management.
* Multiple low power modes support, ex: Deep sleep,Standby, MCU-only,
  enabling battery powered system design.

AM625 is the first device of the family. Add DT bindings for the same.

More details can be found in the Technical Reference Manual:
https://www.ti.com/lit/pdf/spruiv7

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2022-06-10 13:37:32 -04:00
Aswath Govindraju
36dafd8045 arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-06-10 13:37:32 -04:00
Vaishnav Achath
09d14d7f10 arm: k3: sysfw-loader: add hyperflash support
add support for loading system firmware from hyperflash.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
2022-06-10 09:03:22 -04:00
Tom Rini
59bffec43a Merge branch '2022-04-04-platform-updates'
- Updates for exynos78x0 and TI K3 platforms
2022-04-05 13:45:22 -04:00
Hari Nagalla
92e46092f2 arch: arm: mach-k3: am642_init: Probe ESM nodes
On AM64x devices, it is possible to route Main ESM0 error events to MCU
ESM. MCU ESM high error output can trigger the reset logic to reset the
device. So, for these devices we expect two ESM device nodes in the
device tree, one for Main ESM and the another MCU ESM in the device tree.
 When these ESM device nodes are properly configired it is possible to
route the Main RTI0 WWDT output to the MCU ESM high output through Main
ESM and trigger a device reset when
CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is set to '0'.

On K3 AM64x devices, the R5 SPL u-boot handles the ESM device node
configurations.

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-04-04 19:02:04 -04:00
Andre Przywara
5907357322 spl: mmc: extend spl_mmc_boot_mode() to take mmc argument
Platforms can overwrite the weak definition of spl_mmc_boot_mode() to
determine where to load U-Boot proper from.
For most of them this is a trivial decision based on Kconfig variables,
but it might be desirable the probe the actual device to answer this
question.

Pass the pointer to the mmc struct to that function, so implementations
can make use of that.

Compile-tested for all users changed.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Ley Foon Tan <ley.foon.tan@inte.com> (for SoCFPGA)
Acked-by: Lokesh Vutla <lokeshvutla@ti.com> (for OMAP and K3)
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-04-04 23:24:17 +01:00
Christian Gmeiner
f7fbe547d9 arm: mach-k3: am6_init: Use CONFIG_TI_I2C_BOARD_DETECT
We only want to call do_board_detect() if CONFIG_TI_I2C_BOARD_DETECT
is set. Same as done for am64.

This makes it possible to add a custom am65 based board design to
U-Boot that does not use this board detection mechanism.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2022-03-04 15:20:06 -05:00
Sinthu Raja
1e82a80d17 arm: j721e: Add support for selecting DT based on board name
Enable support for selecting DTB from FIT within SPL based on the
board name read from EEPROM. This will help to use single defconfig
for both EVM and SK.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
2022-02-16 14:19:30 -05:00
Keerthy
b071a07743 drivers: misc: Makefile: Enable fs_loader compilation at SPL Level
Enable fs_loader compilation at SPL Level.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix compilation failures for J721e platform]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
2022-02-08 11:00:02 -05:00
David Huang
681023aba4 arm: K3: Add basic support for J721S2 SoC definition
Add basic support for J721S2 SoC definition

Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2022-02-08 09:41:26 -05:00
Vignesh Raghavendra
07252f5c71 mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC
This is required to enables spl_net boot on AM64x

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
93c43a8365 mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL
In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
e58d928485 mach-k3: common: Instantiate AM65 CPSW NUSS wrapper
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver
is enabled. Since driver is modeled as UCLASS_MISC, we need to
explicitly probe the driver. Use common misc_init_r() that entire
K3 family of SoCs.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
584216315d ARM: mach-k3: sysfw-loader: Copy sysfw.itb to OCRAM in OSPI/SPI bootmode
In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed
in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image
directly on OSPI flash via MMIO window. So, copy the image to internal
on-chip RAM before parsing the image.

Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform
and thus cannot reside in OSPI/xSPI and needs to be copied over to
internal OCRAM.

This unblocks OSPI/xSPI boot on HS platforms

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-01-15 10:38:26 -05:00
Michael Liebert
67c8678346 arm: mach-k3: am642_init: Unlock MCU PADCFG regs
Currently only the PADCFG registers of the main domain are unlocked.
Also unlock PADCFG registers of MCU domain, so MCU pin muxing can be configured by u-boot or Linux.

Signed-off-by: Michael Liebert <liebert@ibv-augsburg.de>
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Nishanth Menon <nm@ti.com>
2022-01-15 10:38:26 -05:00
Jan Kiszka
a2db09e269 board: siemens: Add support for SIMATIC IOT2050 devices
This adds support for the IOT2050 Basic and Advanced devices. The Basic
used the dual-core AM6528 GP processor, the Advanced one the AM6548 HS
quad-core version.

Both variants are booted via a Siemens-provided FSBL that runs on the R5
cores. Consequently, U-Boot support is targeting the A53 cores. U-Boot
SPL, ATF and TEE have to reside in SPI flash.

Full integration into a bootable image can be found on
https://github.com/siemens/meta-iot2050

Based on original board support by Le Jin, Gao Nian and Chao Zeng.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-03 14:40:56 -04:00
Tom Rini
e908d20fcb Prepare v2021.10-rc5
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Merge tag 'v2021.10-rc5' into next

Prepare v2021.10-rc5
2021-09-27 09:45:36 -04:00
Nishanth Menon
ee91d46557 arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.

However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.

As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.

To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.

We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.

Signed-off-by: Nishanth Menon <nm@ti.com>
2021-09-17 14:48:53 -04:00
Roger Quadros
6887f8e00b arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
NB0 is bridge to SRAM and NB1 is bridge to DDR.

To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).

This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.

This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.

Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: Nishanth Menon<nm@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
cfd50dfb72 clk: ti: k3: Update driver to account for divider flags
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Dave Gerlach
ae8d3d236a arm: mach-k3: Add note to auto-generated files
Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.

Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
326c03b548 arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
f1a815d068 arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
d86a089d29 arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub
Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2021-09-17 14:47:03 -04:00
Simon Glass
103c5f1806 mmc: Rename MMC_SUPPORT to MMC
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup some incorrect renames]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-04 11:42:41 -04:00
Suman Anna
ea985f6d92 arm: mach-k3: Cleanup common start_non_linux_remote_cores()
The mach-k3 common code defined a weak start_non_linux_remote_cores()
function so that the proper implementation can be plugged in the
SoC-specific source files. This won't be needed anymore, so remove the
the common code.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-4-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Suman Anna
536f633d8a arm: mach-k3: j721e: Cleanup MAIN R5 boot code from R5 SPL
The common J7 specific start_non_linux_remote_cores() override function
implements the logic to load and boot the Main R5FSS Core0 from R5 SPL.
This won't be supported any more for either J721E or J7200 after the R5
SPL rearchitecture for the System Firmware split into TI Foundation
Security (TIFS) and Device Management (DM) firmwares. So, cleanup the
corresponding code and the related SPL env variables.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-3-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Suman Anna
05e858aefe arm: mach-k3: j721e: Move booting of Main R5FSS Core0 to A72 U-Boot
The Main R5FSS Core0 on J721E SoCs is originally booted from R5 SPL
itself to achieve certain product-level early-boot metrics. This is
no longer supported after the R5 SPL re-architecture (support merged
for v2021.10-rc1). Move the booting of this core altogether from R5
SPL to A72 U-Boot.

The env variables are left as is for now, and will be cleaned up
in a subsequent patch.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726211311.5977-2-s-anna@ti.com
2021-07-27 11:00:44 +05:30
Aswath Govindraju
2140d6b0ff arch: arm: mach-k3: am642_init: Correct the function name spl_boot_mode() to spl_mmc_boot_mode()
Function spl_boot_mode() is called in common/spl/spl_mmc.c, to find the
boot mode for a given boot device. This function was renamed to
spl_mmc_boot_mode() by commit e97590654a.

Therefore, rename spl_boot_mode to spl_mmc_boot_mode.

Fixes: 57dba04afb ("arm: mach-k3: am642: Add support for boot device detection")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-2-a-govindraju@ti.com
2021-07-27 10:58:49 +05:30
Gowtham Tammana
ba7455a796 arm: mach-k3: am642_init: Add missing ddr guard
The `struct udevice *` reference is needed for either of the
K3_LOAD_SYSFW, K3_AM64_DDRSS config guards. Adding the missing
K3_AM64_DDRSS guard.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210624171614.14244-1-g-tammana@ti.com
2021-07-15 17:56:04 +05:30
Dave Gerlach
61305e00c7 arm: mach-k3: j721e_init: Force early probe of clk-k3 driver
Force the clk-k3 driver to probe early during R5 SPL boot to ensure the
default system clock configuration is completed. Many other drivers
assume a default state of the clock tree and it is currently possible
for them to probe before clk-k3 depending on the exact system
configuration.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reported-by: Keerthy <j-keerthy@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
925698daac arm: mach-k3: sysfw-loader: pass boardcfg to sciserver
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
7acd4d7142 arm: mach-k3: common: Drop main r5 start
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
0714580346 arm: mach-k3: do board config for PM only if supported
If the raw PM support is built in, we are operating in the split
firmware approach mode where PM support is not available. In this
case, skip the board config for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
547b277cd9 arm: mach-k3: add support for detecting firmware images from FIT
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Dave Gerlach
277729eaf3 arm: mach-k3: Add platform data for j721e and j7200
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
df5363a67f tools: k3_fit_atf: add DM binary to the FIT image
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Lokesh Vutla
481d394e77 common: fit: Update board_fit_image_post_process() to pass fit and node_offset
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Tero Kristo
99214c1f48 arm: mach-k3: introduce new config option for sysfw split
On J7 family of SoCs (J721E and J7200), sysfw is being split to be run
under two cores, TIFS portion on DMSC core, and DM firmware under MCU
R5. As MCU R5 is also used to run one phase of the bootloader, we must
prevent access from here towards sysfw services. To support this, add
new config option which can be used to detect presence of RM/PM sysfw
services.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <kristo@kernel.org>
2021-06-11 16:34:52 +05:30
Aswath Govindraju
26f32c32b2 configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy the limitations for USB DFU boot mode
For USB DFU boot mode there is a limitation on the load address of boot
images that they have to be less than 0x70001000. Therefore, move the
SPL_TEXT_BASE address to 0x70000000.

Currently ATF is being loaded at 0x70000000, if the SPL is being loaded at
0x70000000 then ATF would overwrite SPL image when loaded. Therefore, move
the location of ATF to a latter location in SRAM, past the SPL image. Also
rearrange the EEPROM and BSS data on top of ATF.

Given below is the placement of various data sections in SRAM

     ┌──────────────────────────────────────┐0x70000000
     │                                      │
     │                                      │
     │                                      │
     │    SPL IMAGE (Max size 1.5 MB)       │
     │                                      │
     │                                      │
     │                                      │
     ├──────────────────────────────────────┤0x7017FFFF
     │                                      │
     │           SPL STACK                  │
     │                                      │
     ├──────────────────────────────────────┤0x70192727
     │          GLOBAL DATA(216 B)          │
     ├──────────────────────────────────────┤0x701927FF
     │                                      │
     │       INITIAL HEAP (32 KB)           │
     │                                      │
     ├──────────────────────────────────────┤0x7019A7FF
     │                                      │
     │          BSS  (20 KB)                │
     ├──────────────────────────────────────┤0x7019F7FF
     │         EEPROM DATA (2 KB)           │
     ├──────────────────────────────────────┤0x7019FFFF
     │                                      │
     │                                      │
     │            ATF (123 KB)              │
     │                                      │
     │                                      │
     ├──────────────────────────────────────┤0x701BEBFB
     │   BOOT PARAMETER INDEX TABLE (5124 B)│
     ├──────────────────────────────────────┤0x701BFFFF
     │                                      │
     │SYSFW FIREWALLED DUE TO A BUG (128 KB)│
     │                                      │
     ├──────────────────────────────────────┤0x701DFFFF
     │                                      │
     │      DMSC CODE AREA (128 KB)         │
     │                                      │
     └──────────────────────────────────────┘0x701FFFFF

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-9-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
669a03e0ff arm: mach-k3: am642_init: Do USB fixups to facilitate host and device boot modes
U-Boot either supports USB host or device mode for a node at a time in the
device tree nodes. To support both host and dfu bootmodes, dr_mode is set
to "peripheral" by default and then fixed based on the mode selected by
the boot mode config dip switches on the board.

This needs to happen before the cdns3 generic layer binds the usb device
to a host or a device driver. Therefore, use fdtdec_setup_board()
implementation to fixup the device tree property.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-4-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
3ae127c4e2 arm: mach-k3: am642_init: Add support for USB boot mode
Add support for identifying USB host and device boot modes

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-3-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Aswath Govindraju
0c51509224 tools: k3_fit_atf: Add support for providing ATF load address using a Kconfig symbol
Add support for providing ATF load address with a Kconfig symbol.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20210604163043.12811-2-a-govindraju@ti.com
2021-06-09 22:23:44 +05:30
Marek Behún
236f2ec432 treewide: Convert macro and uses of __section(foo) to __section("foo")
This commit does the same thing as Linux commit 33def8498fdd.

Use a more generic form for __section that requires quotes to avoid
complications with clang and gcc differences.

Remove the quote operator # from compiler_attributes.h __section macro.

Convert all unquoted __section(foo) uses to quoted __section("foo").
Also convert __attribute__((section("foo"))) uses to __section("foo")
even if the __attribute__ has multiple list entry forms.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-05-24 14:21:30 -04:00
Lokesh Vutla
b5425a9676 arm: am64x: Add support for selecting DT based on EEPROM
Enable support for selecting DTB within SPL based on EEPROM.
This will help to use single defconfig for both EVM and SK

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Lokesh Vutla
2ee76314a7 board: ti: am64x: Add support for reading eeprom data
I2C EEPROM data contains the board name and its revision.
Add support for:
- Reading EEPROM data and store a copy at end of SRAM
- Updating env variable with relevant board info
- Printing board info during boot.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2021-05-12 16:32:44 +05:30
Dave Gerlach
d411f0973a arm: mach-k3: am642: Add support for triggering ddr init from SPL
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:31:16 +05:30
Dave Gerlach
33b7258947 board: ti: am64x: Add board support for am64x evm
Add board specific initialization for am64x based boards.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Keerthy
7fe7713c2e armv8: mach-k3: am642: Add custom MMU support
Change the memory attributes for the DDR regions used by the remote
processors on AM65x so that the cores can see and execute the proper code.

A separate table based on the previous K3 SoCs is introduced since the
number of remote processors and their DDR usage is different between the
SoC families.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Suman Anna
078332cee3 arm: mach-k3: am642: Shut down R5 core after ATF startup on A53
The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs
the R5 SPL that performs the initialization of the System Controller
processor and starting the Arm Trusted Firmware (ATF) on the Arm
Cortex A53 cluster. The Core0 serves as this boot processor and is
parked in WFE after all the initialization. Core1 does not directly
participate in the boot flow, and is simply parked in a WFI.

Power down these R5 cores (and the associated RTI timer resources
that were indirectly powered up) after starting up ATF on A53 by
using the appropriate SYSFW API in release_resources_for_core_shutdown().
This allows these Main R5F cores to be further controlled from the
A53 to run regular applications.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
f4686c3d5b arm: mach-k3: am642: Use mmc start and stop callbacks
To avoid any glitches on MMC clock line, make use of pm per and post
callbacks when loading sysfw.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
d2edabfa8d arm: mach-k3: am642: Load SYSFW binary and config from boot media
Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the AM642 early initialization sequence. Also
make use of existing logic to detect if ROM has already loaded sysfw
and avoided attempting to reload and instead just prepare to use already
running firmware.

While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW
to print diagnostic messages.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
6d52c9dd90 arm: mach-k3: am642: Store boot info from ROM
For AM642, ROM supports loading system firmware directly
from boot image. ROM passes information about the number of
images that are loaded to bootloader at a specific address
that is temporary.  Add support for storing this information
somewhere permanent before it gets corrupted.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
b4a8c3b242 arm: mach-k3: am642: Unlock all applicable control MMR registers
To access various control MMR functionality the registers need to
be unlocked. Do that for all control MMR regions in the MAIN domain.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Keerthy
57dba04afb arm: mach-k3: am642: Add support for boot device detection
AM642 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Dave Gerlach
eb54168bb0 arm: mach-k3: Add basic support for AM642 SoC definition
The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:27:57 +05:30
Harald Seiler
35b65dd8ef reset: Remove addr parameter from reset_cpu()
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to.  This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value.  Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.

Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g.  COLD vs WARM resets).  As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).

To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely.  Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.

This transformation was done with the following coccinelle patch:

    @@
    expression argvalue;
    @@
    - reset_cpu(argvalue)
    + reset_cpu()

    @@
    identifier argname;
    type argtype;
    @@
    - reset_cpu(argtype argname)
    + reset_cpu(void)
    { ... }

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-03-02 14:03:02 -05:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Simon Glass
65e25bea59 dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET()
In the spirit of using the same base name for all of these related macros,
rename this to have the operation at the end. This is not widely used so
the impact is fairly small.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:26:35 -07:00
Simon Glass
991759196f dm: Drop the unused arg in uclass_find_device_by_seq()
Now that there is only one sequence number (rather than both requested and
assigned ones) we can simplify this function. Also update its caller to
simplify the logic.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-18 20:32:21 -07:00
Suman Anna
7873e9df8f armv8: K3: j7200: Add custom MMU support
The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.

The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-09-15 18:51:53 +05:30
Vignesh Raghavendra
7ce6c8ae58 arm: mach-k3: Add HyperFlash boot mode support
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:52 +05:30
Lokesh Vutla
01dbe366ba arm: mach-k3: j7200: Detect if ROM has already loaded sysfw
Detect if sysfw is already loaded by ROM and pass this information to
sysfw loader. Based on this information sysfw loader either loads the
sysfw image from boot media or just receives the boot notification
message form sysfw.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
9c8f41beea arm: mach-k3: j7200: Add support for storing extended boot info from ROM
Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. ROM passes this information on number of images that are loaded
to bootloader at certain location. Add support for storing this
information before it gets corrupted.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
30de1ba0d3 arm: mach-k3: j7200: Add support for SOC detection
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
  capable dual Cortex-R5F MCUs and a Centralized Device Management and
  Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
  throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
  in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
  20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
  I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.

See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1

Add support for detection J7200 SoC

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
73108dcd7f arm: mach-k3: j721e: Fix unlocking control module registers
In main control mmr there is no partition 4 and partition 6 is available
only on J721e. Fix the same in ctrl_mmr_unlock function

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
2a18be77de arm: mach-k3: j721e: Add detection for j721e
Add an api soc_is_j721e(), and use it to enable certain functionality
that is available only on j721e. This detection is needed when DT is not
available.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
dc57a554a5 arm: mach-k3: sysfw-loader: Add support for rom loading sysfw image
Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. In such cases, SPL need not load sysfw from boot media, but need
to receive boot notification message from sysfw. So separate out
remoteproc calls for system controller from sysfw loader and just
receive the boot notification if sysfw is already loaded.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
58ccd6105c arm: mach-k3: Move mmr_unlock to a common location
mmr_unlock api is common for all k3 devices. Move it to a common
location.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Jean-Jacques Hiblot
d099db2829 arm: mach-k3: Fix platform hang when SPL_MULTI_DTB_FIT is not enabled
If SPL_MULTI_DTB_FIT is not enabled, then CONFIG_SPL_OF_LIST is not defined
And in turn tispl.bin ends up not embedding any DTB.
Fixing it by using CONFIG_DEFAULT_DEVICE_TREE if SPL_OF_LIST is empty.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
b29a7cd09d board: ti: j721e: Probe eeprom only when CONFIG_TI_I2C_BOARD_DETECT is defined
Guard all eeprom probe with TI_I2C_BOARD_DETECT to avoid reading eeprom
when eeprom is not available

Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
897e83f0a5 arm: mach-k3: am6_init: Add support for USB boot mode
Add support for identifying USB host and device boot modes

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
403fc5c9cf arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes
U-boot only supports either USB host or device mode for a node at a
time in dts. To support both host and dfu bootmodes, set "peripheral"
as the default dr_mode but fixup property to "host" if host bootmode
is detected.

This needs to happen before the dwc3 generic layer binds the usb device
to a host or device driver. Therefore, add an fdtdec_setup_board()
implementation to fixup the dt based on the boot mode.

Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe
in both the host and device cases. This is required for accessing the
interface at USB 2.0 speeds.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
febb47ac61 arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config
Gate mmc related system related configurations with DM_MMC to avoid build
errors when MMC is not enabled

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
f5838b1542 arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB
Add support for loading system firmware from a USB mass storage device

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
f9916b6d3b armv7R: K3: am654: Use full malloc in SPL both pre and post reloc
In order to be able to use things like file system drivers early on in
SPL (before relocation) in a memory-constrained environment when DDR is
not yet available we cannot use the simple malloc scheme which does not
implement the freeing of previously allocated memory blocks. To address
this issue go ahead and enable the use of the full malloc by manually
initializing the required functionality inside board_init_f by creating
a full malloc pool inside the pre-relocation malloc pool.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Andrew F. Davis
864e285739 arm: mach-k3: Clean non-coherent lines out of L3 cache
When switching on or off the ARM caches some care must be taken to ensure
existing cache line allocations are not left in an inconsistent state.
An example of this is when cache lines are considered non-shared by
and L3 controller even though the lines are shared. To prevent these
and other issues all cache lines should be cleared before enabling
or disabling a coherent master's cache. ARM cores and many L3 controllers
provide a way to efficiently clean out all cache lines to allow for
this, unfortunately there is no such easy way to do this on current K3
MSMC based systems.

We could explicitly clean out every valid external address tracked by
MSMC (all of DRAM), or we could attempt to identify only the set of
addresses accessed by a given boot stage and flush only those
specifically. This patch attempts the latter. We start with cleaning the
SPL load address. More addresses can be added here later as they are
identified.

Note that we perform a flush operation for both the flush and invalidate
operations, this is not a typo. We do this to avoid the situation that
some ARM cores will promote an invalidate to a clean+invalidate, but only
emit the invalidation operation externally, leading to a loss of data.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Tested-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 10:18:27 +05:30
Simon Glass
a00867b47a sf: Drop dm.h header file from spi_flash.h
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
e6385c7e9c Makefile: Rename ALL-y to INPUTS-y
When binman is in use, most of the targets built by the Makefile are
inputs to binman. We then need a final rule to run binman to produce the
final outputs.

Rename the variable to indicate this, and add a new 'inputs' target.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28 19:30:39 -06:00
Dave Gerlach
5ab71ea4b1 arm: mach-k3: Use SOC driver for device identification
Make use of UCLASS_SOC to find device family and revision for
print_cpuinfo.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25 14:46:57 -06:00
Tom Rini
7208396bbf Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit 5d3a21df66, reversing
changes made to 56d37f1c56.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24 08:42:06 -04:00
Dave Gerlach
469f04e882 arm: mach-k3: Use SOC driver for device identification
Make use of UCLASS_SOC to find device family and revision for
print_cpuinfo.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Patrick Delaunay
865fdfddce arm: k3: use correct weak function name spl_board_prepare_for_linux
Replace the function spl_board_prepare_for_boot_linux by the correct
name of the weak function spl_board_prepare_for_linux defined in spl.h.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-13 20:58:34 +05:30
Jan Kiszka
dde9da82d6 arm: k3: Consolidate and silence k3_fit_atf.sh call
Buiding u-boot-spl-k3[_HS].its is currently unconditionally verbose
about what it does. Change that by wrapping the call to k3_fit_atf.sh
into a cmd, also using that chance to reduce duplicate lines of makefile
code - only IS_HS=1 is different when CONFIG_TI_SECURE_DEVICE is on.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-07-13 20:58:34 +05:30
Tom Rini
60c7facfc9 Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Enable DM_ETH on omap3_logic board
- Enable Caches in SPL for K3 platforms
- Enable backup boot mode support for J721E
- Update the DDR timings for AM654 EVM
- Add automated tests for RX-51
2020-05-25 14:09:42 -04:00
Jan Kiszka
c02712a748 arm: mach-k3: Enable dcache in SPL
Add support for enabling dcache already in SPL. It accelerates the boot
and resolves the risk to run into unaligned 64-bit accesses.

Based on original patch by Lokesh Vulta.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-05-19 14:41:13 +05:30
Andreas Dannenberg
7bf82cc1f8 arm: mach-k3: j721e_init: Add support for backup boot modes
When the boot of J721E devices using the primary bootmode (configured
via device pins) fails a boot using the configured backup bootmode is
attempted. To take advantage of the backup boot mode feature go ahead
and add support to the J721E init code to determine whether the ROM code
performed the boot using the primary or backup boot mode, and if booted
from the backup boot mode, decode the bootmode settings into the
appropriate U-Boot mode accordingly so that the boot can proceed.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-05-19 14:40:54 +05:30
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
4d72caa5b9 common: Drop image.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
90526e9fba common: Drop net.h from common header
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:31 -04:00
Andrew F. Davis
b76bea1205 arm: K3: Increase default SYSFW image size allocation
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
Some additions to the board configuration data has pushed us slightly
over the current defined size on some HS devices, expand to 278000.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2020-05-11 10:16:49 +05:30
Harald Seiler
e97590654a spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()
The function's name is misleading as one might think it is used
generally to select the boot-mode when in reality it is only used by the
MMC driver to find out in what way it should try reading U-Boot Proper
from a device (either using a filesystem, a raw sector/partition, or an
eMMC boot partition).

Rename it to spl_mmc_boot_mode() to make it more obvious what this
function is about.

Link: https://lists.denx.de/pipermail/u-boot/2020-April/405979.html
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-22 20:41:57 +08:00
Lokesh Vutla
e7510d443d arm: mach-k3: Use JTAD_ID register for device identification
JTAG ID register is defined by IEEE 1149.1 for device identification.
Use this JTAG ID register for identifying AM65x[0] and J721E[1] devices
instead of using SoC specific registers.

[0] http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
[1] http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf

Reported-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-04-19 16:20:53 +05:30
Tom Rini
2738f0edea Merge tag 'ti-v2020.07-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
K3 J721E:
* OSPI boot support
* Support for loading remote cores in R5 SPL
* PMIC ESM Support
* Minor fixes for R5F and C7x remoteproc drivers

K3 AM654:
* Update AVS class 0 voltages.
* Add I2C nodes

DRA7xx/AM57xx:
* Fixed Android boot on AM57xx

AM33/AM43/Davinci:
* switch to driver model for the net and mdio driver for baltos
* Add DM/DTS support for omap video driver
* Enable fastboot on am335x-evm
2020-03-17 11:59:58 -04:00
Suman Anna
8f4109e09d armv8: K3: j721e: Add DSP internal memory regions in MMU table
The A72 U-Boot code supports early load and boot of a number of
remote processors including the C66_0 and C66_1 DSPs. The current
code supports only loading into the DDR regions which were already
given the appropriate memory attributes. The C66 DSPs also have L1
and L2 internal memory regions that can behave as normal-memories.

Add a new entry to the J721E MMU table covering these regions with
the appropriate memory attributes to allow the A72 U-Boot code to
support loading directly into these memory regions.

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-03-16 12:32:47 +05:30
Lokesh Vutla
6e44aebdbb arm: mach-k3: Add a separate function for printing sysfw version
Add a separate function for printing sysfw version so that it can be
called independently of k3_sysfw_loader.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-11 08:56:49 +05:30
Faiz Abbas
d45ffb7937 arm: K3: sysfw-loader: Add a config_pm_pre_callback()
System firmware does not guarantee that clocks going out of the device
will be stable during power management configuration. There are some
DCRC errors when SPL tries to get the next stage during eMMC boot after
sysfw pm configuration.

Therefore add a config_pm_pre_callback() to switch off the eMMC clock
before power management and restart it after it is done.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-09 08:33:16 +08:00
Keerthy
d154252fc9 armv7R: K3: Add support for jumping to firmware
MCU Domain rf50 is currently shutting down after loading the ATF.
Load elf firmware and jump to firmware post loading ATF.

ROM doesn't enable ATCM memory, so make sure that firmware that
is being loaded doesn't use ATCM memory or override SPL.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-03 13:08:14 +05:30
Keerthy
6dce1cfa56 armv7R: K3: r5_mpu: Enable execute permission for MCU0 BTCM
Enable execute permission for mcu_r5fss0_core0 BTCM so that we can jump
to a firmware directly from SPL.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-03 13:08:14 +05:30
Keerthy
3ab34bc028 arm: k3: Add support for loading non linux remote cores
Add MAIN domain R5FSS0 remoteproc support from spl. This enables
loading the elf firmware in SPL and starting the remotecore.

In order to start the core, there should be a file with path
"/lib/firmware/j7-main-r5f0_0-fw" under filesystem
of respective boot mode.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[Guard start_non_linux_remote_cores under CONFIG_FS_LOADER]
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2020-03-03 13:08:14 +05:30
Lokesh Vutla
7d0866b9be ARM: mach-k3: sysfw-loader: Use SPI memmapped addr when loading SYSFW
Since ROM configures OSPI controller to be in memory mapped mode in OSPI
boot, R5 SPL can directly pass the memory mapped pointer to ROM. With
this ROM can directly pull the SYSFW image from OSPI.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-03 13:08:13 +05:30
Vignesh Raghavendra
8915a40da4 ARM: mach-k3: arm64-mmu: map 64bit FSS MMIO space in A53 MMU
Populate address mapping entries in A53 MMU for 4 GB of MMIO space
reserved for providing MMIO access to multiple flash devices through
OSPI/HBMC IPs within FSS.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-03-03 13:08:13 +05:30
Andreas Dannenberg
96dd223c29 armV7R: K3: am654: Activate early console functionality
Activate early console functionality on AM65x devices to allow for
early diagnostic messages until the main console is ready
to get activated.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-13 21:39:18 +05:30
Andreas Dannenberg
a06df8f339 arm: K3: j721e: Fix boot parameter table index memory address
The boot parameter table index memory address for J721E was configured
to an incorrect value which prevented the use of this definition to
determine which boot parameter table is active which is needed to be
able to distinguish between primary and backup boot modes. Fix this
issue by updating the value to the correct one also in alignment with
the J721E Technical Reference Manual (TRM).

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-13 21:39:18 +05:30
Lokesh Vutla
b9c268c90e arm: mach-k3: Fix nomenclature on Silicon Revisions
Data manual mentions the new silicon revisions as SR instead of PG. Use
the same nomenclature inside U-Boot as well.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-13 21:39:18 +05:30
Vignesh Raghavendra
e15b6e35b1 arm: mach-k3: sysfw-loader: Add support to download SYSFW via DFU
Add support to download SYSFW into internal RAM via DFU in DFU boot
mode. Prepare a DFU config entity entry dynamically using buffer address
allocated for SYSFW and start DFU gadget to get SYSFW.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Vignesh Raghavendra
eabd591015 arm: mach-k3: j721e: Rename BOOT_DEVICE_USB to BOOT_DEVICE_DFU
J721e does not support USB Host MSC boot, but only supports DFU boot.
Since BOOT_DEVICE_USB is often used for host boot mode and
BOOT_DEVICE_DFU is used for DFU boot, rename BOOT_DEVICE_USB macro to
BOOT_DEVICE_DFU

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-02-04 09:07:24 +05:30
Tom Rini
07add22cab Merge tag '2020-01-20-ti-2020.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodes

K3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA support

DRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/ti

AM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
2020-01-20 14:54:55 -05:00
Andrew F. Davis
c0910bb3a0 arm: K3: Increase default SYSFW image size allocation
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
This was 276000 bytes but now needs to be grown to 277000 to make room
for the slightly larger SYSFW image used on J721e High-Security devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Andrew F. Davis
ea70da142c arm: K3: Disable ROM configured firewalls
ROM configures certain firewalls based on its usage, which includes
the one in front of boot peripherals. In specific case of boot
peripherals, ROM does not open up the full address space corresponding
to the peripherals. Like in OSPI, ROM only configures the firewall region
for 32 bit address space and mark 64bit address space flash regions
as in-accessible.

When security-cfg is initialized by sysfw, all the non-configured
firewalls are kept in bypass state using a global setting. Since ROM
configured firewalls for certain peripherals, these will not be touched.
So when bootloader touches any of the address space that ROM marked as
in-accessible, system raises a firewall exception causing boot hang.

It would have been ideal if sysfw cleans up the ROM configured boot
peripheral firewalls. Given the memory overhead to store this
information provided by ROM and the boot time increase in re configuring
the firewalls, it is concluded to clean this up in bootloaders.

So disable all the firewalls that ROM doesn't open up the full address
space.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Andrew F. Davis
9b322dbd52 arm: K3: Fix header comment match AM6 specific file function
This file used to be the common location for K3 init when AM6 was the
only device, but common code was moved to common.c and this file became
AM6 specific, correct this header text.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Andrew F. Davis
95b256ec3f arm: mach-k3: security: Clean image out of cache before authentication
On K3 systems U-Boot runs on both an R5 and a large ARM cores (usually
A53 or A72). The large ARMs are coherent with the DMA controllers and
the SYSFW that perform authentication. And previously the R5 core did
not enable caches. Now that R5 does enable caching we need to be sure
to clean out any of the image that may still only be in cache before we
read it using external DMA for authentication.

Although not expected to happen, it may be possible that the data was
read back into cache after the flush but before the external operation,
in this case we must invalidate our stale local cached version.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Andrew F. Davis
28b90a4656 arm: mach-k3: Warn when node to disable is not found
Not finding a node that we try to disable does not always need to be
fatal to boot but should at least print out a warning. Return error
from fdt_disable_node as it did fail to disable the node, but only
warn in the case of disabling the TRNG as this will not prevent boot.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Andreas Dannenberg
643eb6ea07 board: ti: j721e: Use EEPROM-based board detection
The TI J721E EVM system on module (SOM), the common processor board, and
the associated daughtercards have on-board I2C-based EEPROMs containing
board config data. Use the board detection infrastructure to do the
following:

1) Parse the J721E SOM EEPROM and populate items like board name, board
   HW and SW revision as well as board serial number into the TI common
   EEPROM data structure residing in SRAM scratch space
2) Check for presence of daughter card(s) by probing associated I2C
   addresses used for on-board EEPROMs containing daughter card-specific
   data. If such a card is found, parse the EEPROM data such as for
   additional Ethernet MAC addresses and populate those into U-Boot
   accordingly
3) Dynamically apply daughter card DTB overlays to the U-Boot (proper)
   DTB during SPL execution
4) Dynamically create an U-Boot ENV variable called name_overlays
   during U-Boot execution containing a list of daugherboard-specific
   DTB overlays based on daughercards found to be used during Kernel
   boot.

This patch adds support for the J721E system on module boards containing
the actual SoC ("J721EX-PM2-SOM", accessed via CONFIG_EEPROM_CHIP_ADDRESS),
the common processor board ("J7X-BASE-CPB"), the Quad-Port Ethernet
Expansion Board ("J7X-VSC8514-ETH"), the infotainment board
("J7X-INFOTAN-EXP") as well as for the gateway/Ethernet switch/industrial
expansion board ("J7X-GESI-EXP").

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-20 10:10:28 +05:30
Simon Glass
db41d65a97 common: Move hang() to the same header as panic()
At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Migrate a few more files]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-01-17 17:53:40 -05:00
Simon Glass
9a3b4ceb37 common: Move reset_cpu() to the CPU header
Move this function out of common.h and into a relevant header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-01-17 14:02:31 -05:00
Lokesh Vutla
40109f4d7e arm: mach-k3: Enable WA for R5F deadlock
On K3 devices there are 2 conditions where R5F can deadlock:
1.When software is performing series of store operations to
  cacheable write back/write allocate memory region and later
  on software execute barrier operation (DSB or DMB). R5F may
  hang at the barrier instruction.
2.When software is performing a mix of load and store operations
  within a tight loop and store operations are all writing to
  cacheable write back/write allocates memory regions, R5F may
  hang at one of the load instruction.

To avoid the above two conditions disable linefill optimization
inside Cortex R5F which will make R5F to only issue up to 2 cache
line fills at any point of time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-01-03 09:47:11 -05:00
Keerthy
7b13493088 arm: mach-k3: j721e_init: Initialize avs class 0
Initialize avs class 0

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Keerthy
27380cb7e9 arm: mach-k3: am6_init: Initialize AVS class 0
Initialize AVS class 0 so that mpu voltage rail is
programmed to the AVS class 0 compensated value.

Signed-off-by: Keerthy <j-keerthy@ti.com>
2019-11-07 18:39:17 -05:00
Lokesh Vutla
22b548044b armv7R: K3: j721e: Add support for triggering ddr init from SPL
In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
Lokesh Vutla
e938b22521 arm: K3: Clean and invalidate Linux Image before jumping to Linux
U-Boot cleans and invalidate L1 and L2 caches before jumping to Linux
by set/way in cleanup_before_linux(). Additionally there is a custom
hook provided to clean and invalidate L3 cache.

Unfortunately on K3 devices(having a coherent architecture), there is no
easy way to quickly clean all the cache lines for L3. The entire address
range needs to be cleaned and invalidated by Virtual Address. This can
be implemented using the L3 custom hook but it take lot of time to clean
the entire address range. In the interest of boot time this might not be
a viable solution.

The best hit is to make sure the loaded Linux image is flushed so that
the entire image is written to DDR from L3. When Linux starts running with
caches disabled the full image is available from DDR.

Reported-by: Andrew F. Davis <afd@ti.com>
Reported-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-25 17:33:21 -04:00
Lokesh Vutla
e69ffdb763 arm: k3: Use driver_name to get ti_sci handle
Use the driver name to get ti_sci handle rather than relying
on just the FIRMWARE uclass.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 13:32:20 -04:00
Lokesh Vutla
f8ca912189 arm: k3: Add support for printing CPUINFO
Add support for printing CPU info for all K3 devices.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 13:31:18 -04:00
Kedar Chitnis
8bdd83ee50 armv8: K3: j721e: Updated ddr address regions in MMU table
The A72 U-Boot code loads and boots a number of remote processors
including the C71x DSP, both the C66_0 and C66_1 DSPs, and the various
Main R5FSS Cores. In order to view the code loaded by the U-Boot by
remote cores, U-Boot should configure the memory region with right
memory attributes. Right now U-Boot carves out a memory region which
is not sufficient for all the images to be loaded. So, increase this
carve out region by 256MB.

Signed-off-by: Kedar Chitnis <kedarc@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:59 -04:00
Suman Anna
60bdc6b9f3 armv8: K3: am65x: Update DDR address regions in MMU table
The A53 U-Boot code can load and boot the MCU domain R5F cores (either a
single core in LockStep mode or 2 cores in Split mode) to achieve various
early system functionalities. Change the memory attributes for the DDR
regions used by the remote processors so that the cores can see and
execute the proper code loaded by U-Boot.

These regions are currently limited to 0xa0000000 to 0xa2100000 as per
the DDR carveouts assigned for these R5F cores in the overall DDR memory
map.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-11 10:07:59 -04:00
Andreas Dannenberg
921b325854 arm: K3: sysfw-loader: Allow loading SYSFW via Y-Modem
In order to allow booting TI K3 family SoCs via Y-Modem add support for
loading System Firmware by tapping into the associated SPL core loader
function.

In this context also make sure a console is available and if not go
ahead and activate the early console feature which allows bringing up
an alternate full console before the main console is activated. Such
an alternate console is typically setup in a way that the associated
UART can be fully initialized prior to SYSFW services being available.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-10-11 10:07:33 -04:00
Andreas Dannenberg
e630afe1de arm: K3: common: Allow for early console functionality
Implement an early console functionality in SPL that can be used before
the main console is being brought up. This helps in situations where the
main console is dependent on System Firmware (SYSFW) being up and running,
which is usually not the case during the very early stages of boot. Using
this early console functionality will allow for an alternate serial port
to be used to support things like UART-based boot and early diagnostic
messages until the main console is ready to get activated.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
2019-10-11 10:07:33 -04:00
Andrew F. Davis
29c9db4d98 board: ti: am654: Disable TRNG node for HS devices
On HS devices the access to TRNG is restricted on the non-secure
ARM side, disable the node in DT to prevent firewall violations.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-10-04 12:21:23 -04:00
Andrew F. Davis
c9e6c13deb arm: K3: Increase default SYSFW image size allocation
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
This was 269000 bytes but now needs to be grown to 276000 to make room
for the signatures attached to the board configuration data on High
Security devices.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2019-10-04 12:21:23 -04:00
Lokesh Vutla
78e512129b arm: k3: Use get_ti_sci_handle() where ever possible
Instead of calling uclass apis everywhere, use get_ti_sci_handle()
when ever ti_sci is needed.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-09-13 11:56:30 -04:00