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05e858aefe
The Main R5FSS Core0 on J721E SoCs is originally booted from R5 SPL itself to achieve certain product-level early-boot metrics. This is no longer supported after the R5 SPL re-architecture (support merged for v2021.10-rc1). Move the booting of this core altogether from R5 SPL to A72 U-Boot. The env variables are left as is for now, and will be cleaned up in a subsequent patch. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210726211311.5977-2-s-anna@ti.com |
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.. | ||
include/mach | ||
j721e | ||
j7200 | ||
am6_init.c | ||
am642_init.c | ||
arm64-mmu.c | ||
cache.S | ||
common.c | ||
common.h | ||
config.mk | ||
config_secure.mk | ||
j721e_init.c | ||
Kconfig | ||
lowlevel_init.S | ||
Makefile | ||
r5_mpu.c | ||
security.c | ||
sysfw-loader.c |