2016-12-28 16:43:40 +00:00
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config SYS_FSL_DDR
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bool
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help
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|
Select Freescale General DDR driver, shared between most Freescale
|
2021-05-15 01:34:26 +00:00
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PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
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Layerscape SoCs (such as ls2080a).
|
2016-12-28 16:43:40 +00:00
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config SYS_FSL_MMDC
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bool
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help
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Select Freescale Multi Mode DDR controller (MMDC).
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|
2021-08-21 17:50:18 +00:00
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if SYS_FSL_DDR || SYS_FSL_MMDC
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2016-12-28 16:43:40 +00:00
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config SYS_FSL_DDR_BE
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bool
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help
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Access DDR registers in big-endian
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config SYS_FSL_DDR_LE
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bool
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help
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Access DDR registers in little-endian
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2019-02-01 05:22:01 +00:00
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config FSL_DDR_BIST
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bool
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config FSL_DDR_INTERACTIVE
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bool
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config FSL_DDR_SYNC_REFRESH
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bool
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config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
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bool
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2016-12-28 16:43:40 +00:00
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menu "Freescale DDR controllers"
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depends on SYS_FSL_DDR
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2016-12-28 16:43:45 +00:00
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config SYS_NUM_DDR_CTLRS
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2016-12-28 16:43:44 +00:00
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int "Maximum DDR controllers"
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default 3 if ARCH_LS2080A || \
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ARCH_T4240
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default 2 if ARCH_B4860 || \
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ARCH_BSC9132 || \
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ARCH_P4080 || \
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ARCH_P5040 || \
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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ARCH_LX2160A || \
|
2021-05-23 14:58:05 +00:00
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ARCH_LX2162A
|
2016-12-28 16:43:44 +00:00
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default 1
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|
2022-02-25 16:19:53 +00:00
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config CHIP_SELECTS_PER_CTRL
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int "Number of chip selects per controller"
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default 4
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|
2022-03-30 22:07:31 +00:00
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config DIMM_SLOTS_PER_CTLR
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int "Number of DIMM slots per controller"
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default 1
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2016-12-28 16:43:40 +00:00
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config SYS_FSL_DDR_VER
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int
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default 50 if SYS_FSL_DDR_VER_50
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default 47 if SYS_FSL_DDR_VER_47
|
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default 46 if SYS_FSL_DDR_VER_46
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default 44 if SYS_FSL_DDR_VER_44
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config SYS_FSL_DDR_VER_50
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bool
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config SYS_FSL_DDR_VER_47
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bool
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config SYS_FSL_DDR_VER_46
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bool
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config SYS_FSL_DDR_VER_44
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bool
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config SYS_FSL_DDRC_GEN1
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bool
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help
|
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Enable Freescale DDR controller.
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config SYS_FSL_DDRC_GEN2
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bool
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depends on !MPC86xx
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help
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|
Enable Freescale DDR2 controller.
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config SYS_FSL_DDRC_GEN3
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bool
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depends on PPC
|
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help
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Enable Freescale DDR3 controller for PowerPC SoCs.
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config SYS_FSL_DDRC_ARM_GEN3
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bool
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depends on ARM
|
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|
help
|
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|
|
Enable Freescale DDR3 controller for ARM SoCs.
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config SYS_FSL_DDRC_GEN4
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|
|
bool
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|
|
|
help
|
|
|
|
Enable Freescale DDR4 controller.
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config SYS_FSL_HAS_DDR4
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bool
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config SYS_FSL_HAS_DDR3
|
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bool
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config SYS_FSL_HAS_DDR2
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bool
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config SYS_FSL_HAS_DDR1
|
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bool
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|
choice
|
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prompt "DDR technology"
|
|
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default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
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|
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default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
|
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default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
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|
default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
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|
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config SYS_FSL_DDR4
|
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bool "Freescale DDR4 controller"
|
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|
depends on SYS_FSL_HAS_DDR4
|
2021-08-21 17:50:16 +00:00
|
|
|
imply DDR_SPD
|
2016-12-28 16:43:40 +00:00
|
|
|
select SYS_FSL_DDRC_GEN4
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config SYS_FSL_DDR3
|
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|
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bool "Freescale DDR3 controller"
|
|
|
|
depends on SYS_FSL_HAS_DDR3
|
2021-08-21 17:50:16 +00:00
|
|
|
imply DDR_SPD
|
2016-12-28 16:43:40 +00:00
|
|
|
select SYS_FSL_DDRC_GEN3 if PPC
|
|
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|
select SYS_FSL_DDRC_ARM_GEN3 if ARM
|
|
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config SYS_FSL_DDR2
|
|
|
|
bool "Freescale DDR2 controller"
|
|
|
|
depends on SYS_FSL_HAS_DDR2
|
2021-08-21 17:50:16 +00:00
|
|
|
imply DDR_SPD
|
2016-12-28 16:43:40 +00:00
|
|
|
select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
|
|
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|
|
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|
|
config SYS_FSL_DDR1
|
|
|
|
bool "Freescale DDR1 controller"
|
|
|
|
depends on SYS_FSL_HAS_DDR1
|
2021-08-21 17:50:16 +00:00
|
|
|
imply DDR_SPD
|
2016-12-28 16:43:40 +00:00
|
|
|
select SYS_FSL_DDRC_GEN1
|
|
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|
|
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|
endchoice
|
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|
|
|
endmenu
|
2016-12-28 16:43:41 +00:00
|
|
|
|
2021-08-21 17:50:18 +00:00
|
|
|
config FSL_DMA
|
|
|
|
def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
|
|
|
|
|
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|
|
config DDR_ECC
|
|
|
|
bool "ECC DDR memory support"
|
|
|
|
|
|
|
|
config DDR_ECC_CMD
|
|
|
|
bool "Access the ECC features of the memory controller"
|
|
|
|
depends on DDR_ECC && MPC83xx
|
|
|
|
default y
|
|
|
|
|
|
|
|
config ECC_INIT_VIA_DDRCONTROLLER
|
|
|
|
bool "DDR Memory controller initializes memory."
|
|
|
|
help
|
|
|
|
Use the DDR controller to auto initialize memory. If not enabled,
|
|
|
|
the DMA controller is responsible for doing this.
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
2021-11-13 23:10:40 +00:00
|
|
|
menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
|
|
|
|
depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
|
|
|
|
|
|
|
|
config SYS_BR0_PRELIM_BOOL
|
|
|
|
bool "Define Bank 0"
|
|
|
|
|
|
|
|
config SYS_BR0_PRELIM
|
|
|
|
hex "Preliminary value for BR0"
|
|
|
|
depends on SYS_BR0_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR0_PRELIM
|
|
|
|
hex "Preliminary value for OR0"
|
|
|
|
depends on SYS_BR0_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_BR1_PRELIM_BOOL
|
|
|
|
bool "Define Bank 1"
|
|
|
|
|
|
|
|
config SYS_BR1_PRELIM
|
|
|
|
hex "Preliminary value for BR1"
|
|
|
|
depends on SYS_BR1_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR1_PRELIM
|
|
|
|
hex "Preliminary value for OR1"
|
|
|
|
depends on SYS_BR1_PRELIM_BOOL
|
|
|
|
|
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|
|
config SYS_BR2_PRELIM_BOOL
|
|
|
|
bool "Define Bank 2"
|
|
|
|
|
|
|
|
config SYS_BR2_PRELIM
|
|
|
|
hex "Preliminary value for BR2"
|
|
|
|
depends on SYS_BR2_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR2_PRELIM
|
|
|
|
hex "Preliminary value for OR2"
|
|
|
|
depends on SYS_BR2_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_BR3_PRELIM_BOOL
|
|
|
|
bool "Define Bank 3"
|
|
|
|
|
|
|
|
config SYS_BR3_PRELIM
|
|
|
|
hex "Preliminary value for BR3"
|
|
|
|
depends on SYS_BR3_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR3_PRELIM
|
|
|
|
hex "Preliminary value for OR3"
|
|
|
|
depends on SYS_BR3_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_BR4_PRELIM_BOOL
|
|
|
|
bool "Define Bank 4"
|
|
|
|
|
|
|
|
config SYS_BR4_PRELIM
|
|
|
|
hex "Preliminary value for BR4"
|
|
|
|
depends on SYS_BR4_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR4_PRELIM
|
|
|
|
hex "Preliminary value for OR4"
|
|
|
|
depends on SYS_BR4_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_BR5_PRELIM_BOOL
|
|
|
|
bool "Define Bank 5"
|
|
|
|
|
|
|
|
config SYS_BR5_PRELIM
|
|
|
|
hex "Preliminary value for BR5"
|
|
|
|
depends on SYS_BR5_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR5_PRELIM
|
|
|
|
hex "Preliminary value for OR5"
|
|
|
|
depends on SYS_BR5_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_BR6_PRELIM_BOOL
|
|
|
|
bool "Define Bank 6"
|
|
|
|
|
|
|
|
config SYS_BR6_PRELIM
|
|
|
|
hex "Preliminary value for BR6"
|
|
|
|
depends on SYS_BR6_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR6_PRELIM
|
|
|
|
hex "Preliminary value for OR6"
|
|
|
|
depends on SYS_BR6_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_BR7_PRELIM_BOOL
|
|
|
|
bool "Define Bank 7"
|
|
|
|
|
|
|
|
config SYS_BR7_PRELIM
|
|
|
|
hex "Preliminary value for BR7"
|
|
|
|
depends on SYS_BR7_PRELIM_BOOL
|
|
|
|
|
|
|
|
config SYS_OR7_PRELIM
|
|
|
|
hex "Preliminary value for OR7"
|
|
|
|
depends on SYS_BR7_PRELIM_BOOL
|
|
|
|
endmenu
|
|
|
|
|
2016-12-28 16:43:41 +00:00
|
|
|
config SYS_FSL_ERRATUM_A008378
|
|
|
|
bool
|
|
|
|
|
2019-11-20 16:07:34 +00:00
|
|
|
config SYS_FSL_ERRATUM_A008109
|
|
|
|
bool
|
|
|
|
|
2016-12-28 16:43:41 +00:00
|
|
|
config SYS_FSL_ERRATUM_A008511
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_A009663
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_A009801
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_A009803
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_A009942
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_A010165
|
|
|
|
bool
|
2016-12-28 16:43:43 +00:00
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_NMG_DDR120
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_DDR_115
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_DDR111_DDR134
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_DDR_A003
|
|
|
|
bool
|
|
|
|
|
|
|
|
config SYS_FSL_ERRATUM_DDR_A003474
|
|
|
|
bool
|