2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2011-01-19 09:05:26 +00:00
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/*
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powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-04-24 20:16:49 +00:00
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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2011-01-19 09:05:26 +00:00
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*/
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#ifndef _ASM_MPC85xx_CONFIG_H_
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#define _ASM_MPC85xx_CONFIG_H_
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/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
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2012-10-28 08:12:54 +00:00
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/*
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* This macro should be removed when we no longer care about backwards
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* compatibility with older operating systems.
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*/
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#define CONFIG_PPC_SPINTABLE_COMPATIBLE
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2014-03-28 00:54:47 +00:00
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#include <fsl_ddrc_version.h>
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2012-10-08 07:44:22 +00:00
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2016-12-28 16:43:47 +00:00
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#if defined(CONFIG_ARCH_MPC8548)
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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2011-01-19 09:05:26 +00:00
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2016-11-16 21:08:52 +00:00
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#elif defined(CONFIG_ARCH_P1010)
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2013-05-16 02:18:13 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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2011-01-19 09:05:26 +00:00
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2016-11-18 18:59:02 +00:00
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#elif defined(CONFIG_ARCH_P1021)
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2011-02-11 07:25:30 +00:00
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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2011-01-19 09:05:26 +00:00
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2016-11-16 23:45:31 +00:00
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#elif defined(CONFIG_ARCH_P1023)
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 2
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_QMAN_NUM_PORTALS 3
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#define CFG_SYS_BMAN_NUM_PORTALS 3
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#define CFG_SYS_FM_MURAM_SIZE 0x10000
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2011-02-04 04:14:19 +00:00
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2011-02-05 19:45:07 +00:00
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/* P1025 is lower end variant of P1021 */
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2016-11-18 19:05:38 +00:00
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#elif defined(CONFIG_ARCH_P1025)
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2011-02-11 07:25:30 +00:00
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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2011-02-05 19:45:07 +00:00
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2016-11-18 19:08:43 +00:00
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#elif defined(CONFIG_ARCH_P2020)
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun <yorksun@freescale.com>
2014-05-23 20:15:00 +00:00
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2016-11-18 19:15:21 +00:00
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#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_SYS_NUM_FM1_10GEC 1
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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2011-05-13 06:16:07 +00:00
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2016-11-18 19:20:40 +00:00
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#elif defined(CONFIG_ARCH_P3041)
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_SYS_NUM_FM1_10GEC 1
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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2011-01-19 09:05:26 +00:00
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2016-11-18 19:24:40 +00:00
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#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 2
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#define CFG_SYS_NUM_FM1_DTSEC 4
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#define CFG_SYS_NUM_FM2_DTSEC 4
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_NUM_FM2_10GEC 1
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
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2011-01-19 09:05:26 +00:00
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2016-11-18 19:39:36 +00:00
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#elif defined(CONFIG_ARCH_P5040)
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 2
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#define CFG_SYS_NUM_FM1_DTSEC 5
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_NUM_FM2_DTSEC 5
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#define CFG_SYS_NUM_FM2_10GEC 1
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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powerpc/85xx: Add P5040 processor support
Add support for the Freescale P5040 SOC, which is similar to the P5020.
Features of the P5040 are:
Four P5040 single-threaded e5500 cores built
Up to 2.4 GHz with 64-bit ISA support
Three levels of instruction: user, supervisor, hypervisor
CoreNet platform cache (CPC)
2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric
Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support Up to 1600MT/s
Memory pre-fetch engine
DPAA incorporating acceleration for the following functions
Packet parsing, classification, and distribution (FMAN)
Queue management for scheduling, packet sequencing and
congestion management (QMAN)
Hardware buffer management for buffer allocation and
de-allocation (BMAN)
Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes
20 lanes at up to 5 Gbps
Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces
Two 10 Gbps Ethernet MACs
Ten 1 Gbps Ethernet MACs
High-speed peripheral interfaces
Two PCI Express 2.0/3.0 controllers
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Two I2C controllers
Four UARTs
Integrated flash controller supporting NAND and NOR flash
DMA
Dual four channel
Support for hardware virtualization and partitioning enforcement
Extra privileged level for hypervisor support
QorIQ Trust Architecture 1.1
Secure boot, secure debug, tamper detection, volatile key storage
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-05 11:09:19 +00:00
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2016-11-15 22:09:50 +00:00
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#elif defined(CONFIG_ARCH_BSC9131)
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2013-05-16 02:18:13 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
- BSC9131 is integrated device that targets Femto base station market.
It combines Power Architecture e500v2 and DSP StarCore SC3850 core
technologies with MAPLE-B2F baseband acceleration processing elements.
- BSC9130 is exactly same as BSC9131 except that the max e500v2
core and DSP core frequencies are 800M(these are 1G in case of 9131).
- BSC9231 is similar to BSC9131 except no MAPLE
The BSC9131 SoC includes the following function and features:
. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
L2 cache
. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
Processing (MAPLE-B2F)
. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
and CRC algorithms
. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
operations
. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
ECC, up to 400-MHz clock/800 MHz data rate
. Dedicated security engine featuring trusted boot
. DMA controller
. OCNDMA with four bidirectional channels
. Interfaces
. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
including IEEE 1588. v2 hardware support and virtualization (eTSEC)
. eTSEC 1 supports RGMII/RMII
. eTSEC 2 supports RGMII
. High-speed USB 2.0 host and device controller with ULPI interface
. Enhanced secure digital (SD/MMC) host controller (eSDHC)
. Antenna interface controller (AIC), supporting three industry standard
JESD207/three custom ADI RF interfaces (two dual port and one single port)
and three MAXIM's MaxPHY serial interfaces
. ADI lanes support both full duplex FDD support and half duplex TDD support
. Universal Subscriber Identity Module (USIM) interface that facilitates
communication to SIM cards or Eurochip pre-paid phone cards
. TDM with one TDM port
. Two DUART, four eSPI, and two I2C controllers
. Integrated Flash memory controller (IFC)
. TDM with 256 channels
. GPIO
. Sixteen 32-bit timers
The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.
This patch takes care of code pertaining to power side functionality only.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2012-04-24 20:16:49 +00:00
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2016-11-15 22:09:50 +00:00
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#elif defined(CONFIG_ARCH_BSC9132)
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2013-04-19 02:31:01 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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powerpc/mpc85xx: Add BSC9132/BSC9232 processor support
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-01-23 17:59:57 +00:00
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2021-05-23 14:58:05 +00:00
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#elif defined(CONFIG_ARCH_T4240)
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2016-11-21 21:35:41 +00:00
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#ifdef CONFIG_ARCH_T4240
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FM1_DTSEC 8
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#define CFG_SYS_NUM_FM1_10GEC 2
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#define CFG_SYS_NUM_FM2_DTSEC 8
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#define CFG_SYS_NUM_FM2_10GEC 2
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2013-03-25 07:40:05 +00:00
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#else
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FM1_DTSEC 6
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#define CFG_SYS_NUM_FM1_10GEC 1
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#define CFG_SYS_NUM_FM2_DTSEC 8
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#define CFG_SYS_NUM_FM2_10GEC 1
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2013-03-25 07:40:05 +00:00
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#endif
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2013-07-31 11:26:41 +00:00
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SRDS_2
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRDS_3
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#define CFG_SYS_FSL_SRDS_4
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 2
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_PME_CLK 0
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2013-05-16 02:18:13 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM1_CLK 3
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#define CFG_SYS_FM2_CLK 3
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#define CFG_SYS_FM_MURAM_SIZE 0x60000
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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2013-03-25 07:33:29 +00:00
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2016-11-18 19:56:57 +00:00
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#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
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2013-07-31 11:26:41 +00:00
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SRDS_2
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 1
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM1_CLK 0
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2013-05-16 02:18:13 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM_MURAM_SIZE 0x60000
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2012-12-23 19:24:16 +00:00
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2016-11-18 19:44:43 +00:00
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#ifdef CONFIG_ARCH_B4860
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powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-01-19 07:16:54 +00:00
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#define CONFIG_NUM_DSP_CPUS 6
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FM1_DTSEC 6
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#define CFG_SYS_NUM_FM1_10GEC 2
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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2013-03-25 07:40:20 +00:00
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#else
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FM1_DTSEC 4
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#define CFG_SYS_NUM_FM1_10GEC 0
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2013-03-25 07:40:20 +00:00
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#endif
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powerpc/mpc85xx: Add B4860 and variant SoCs
Add support for Freescale B4860 and variant SoCs. Features of B4860 are
(incomplete list):
Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
clusters-each core runs up to 1.2 GHz, with an architecture highly
optimized for wireless base station applications
Four dual-thread e6500 Power Architecture processors organized in one
cluster-each core runs up to 1.8 GHz
Two DDR3/3L controllers for high-speed, industry-standard memory interface
each runs at up to 1866.67 MHz
MAPLE-B3 hardware acceleration-for forward error correction schemes
including Turbo or Viterbi decoding, Turbo encoding and rate matching,
MIMO MMSE equalization scheme, matrix operations, CRC insertion and
check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration,
and UMTS chip rate acceleration
CoreNet fabric that fully supports coherency using MESI protocol between
the e6500 cores, SC3900 FVP cores, memories and external interfaces.
CoreNet fabric interconnect runs at 667 MHz and supports coherent and
non-coherent out of order transactions with prioritization and
bandwidth allocation amongst CoreNet endpoints.
Data Path Acceleration Architecture, which includes the following:
Frame Manager (FMan), which supports in-line packet parsing and general
classification to enable policing and QoS-based packet distribution
Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
of queue management, task management, load distribution, flow ordering,
buffer management, and allocation tasks from the cores
Security engine (SEC 5.3)-crypto-acceleration for protocols such as
IPsec, SSL, and 802.16
RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and
outbound). Supports types 5, 6 (outbound only)
Large internal cache memory with snooping and stashing capabilities for
bandwidth saving and high utilization of processor elements. The
9856-Kbyte internal memory space includes the following:
32 Kbyte L1 ICache per e6500/SC3900 core
32 Kbyte L1 DCache per e6500/SC3900 core
2048 Kbyte unified L2 cache for each SC3900 FVP cluster
2048 Kbyte unified L2 cache for the e6500 cluster
Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
Sixteen 10-GHz SerDes lanes serving:
Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total
of up to 8 lanes
Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-
less antenna connection
Two 10-Gbit Ethernet controllers (10GEC)
Six 1G/2.5-Gbit Ethernet controllers for network communications
PCI Express controller
Debug (Aurora)
Two OCeaN DMAs
Various system peripherals
182 32-bit timers
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-10-08 07:44:20 +00:00
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2016-12-28 16:43:32 +00:00
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#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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2013-09-03 05:49:54 +00:00
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#define CONFIG_SYS_FSL_SRDS_1
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 5
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2013-09-03 05:50:15 +00:00
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#define CONFIG_PME_PLAT_CLK_DIV 2
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
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2013-09-03 05:49:54 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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2013-09-03 05:50:15 +00:00
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#define CONFIG_FM_PLAT_CLK_DIV 1
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
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#define CFG_SYS_FM_MURAM_SIZE 0x30000
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2014-03-18 09:04:23 +00:00
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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2014-03-21 08:21:45 +00:00
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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2013-03-25 07:40:06 +00:00
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2021-05-15 01:34:22 +00:00
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#elif defined(CONFIG_ARCH_T1024)
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
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2014-11-24 09:11:54 +00:00
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#define CONFIG_SYS_FSL_SRDS_1
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 1
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#define CFG_SYS_NUM_FM1_DTSEC 4
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#define CFG_SYS_NUM_FM1_10GEC 1
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2014-11-24 09:11:54 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM1_CLK 0
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2014-11-24 09:11:54 +00:00
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#define CONFIG_QBMAN_CLK_DIV 1
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM_MURAM_SIZE 0x30000
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2014-11-24 09:11:54 +00:00
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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2021-02-21 01:06:21 +00:00
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#elif defined(CONFIG_ARCH_T2080)
|
2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FMAN 1
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
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2013-11-22 09:39:10 +00:00
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#define CONFIG_SYS_FSL_SRDS_1
|
2016-11-21 20:54:19 +00:00
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#if defined(CONFIG_ARCH_T2080)
|
2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_FM1_DTSEC 8
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#define CFG_SYS_NUM_FM1_10GEC 4
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2013-11-22 09:39:10 +00:00
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#define CONFIG_SYS_FSL_SRDS_2
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2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
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2013-11-22 09:39:10 +00:00
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#endif
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#define CONFIG_PME_PLAT_CLK_DIV 1
|
2022-11-16 18:10:41 +00:00
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#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
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#define CFG_SYS_FM1_CLK 0
|
2013-11-22 09:39:10 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FM_MURAM_SIZE 0x28000
|
2014-03-18 09:04:23 +00:00
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#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
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2013-11-22 09:39:10 +00:00
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2016-11-16 02:44:22 +00:00
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#elif defined(CONFIG_ARCH_C29X)
|
2013-07-04 09:30:36 +00:00
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
2022-10-29 00:27:13 +00:00
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#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
|
2013-07-04 09:30:36 +00:00
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2011-01-19 09:05:26 +00:00
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#endif
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#endif /* _ASM_MPC85xx_CONFIG_H_ */
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