u-boot/arch/powerpc/include/asm/config_mpc85xx.h
Tom Rini 3a581af21a Convert CONFIG_FLASH_SPANSION_S29WS_N et al to Kconfig
This converts the following to Kconfig:

   CONFIG_FLASH_SPANSION_S29WS_N
   CONFIG_FLASH_VERIFY
   CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
   CONFIG_FSL_ISBC_KEY_EXT
   CONFIG_FSL_TRUST_ARCH_v1
   CONFIG_FSL_SDHC_V2_3
   CONFIG_MAX_DSP_CPUS
   CONFIG_MIU_2BIT_INTERLEAVED
   CONFIG_SERIAL_BOOT
   CONFIG_SPI_BOOTING
   CONFIG_X86EMU_RAW_IO

Signed-off-by: Tom Rini <trini@konsulko.com>
2022-12-22 10:31:48 -05:00

206 lines
6.1 KiB
C

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#ifndef _ASM_MPC85xx_CONFIG_H_
#define _ASM_MPC85xx_CONFIG_H_
/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
/*
* This macro should be removed when we no longer care about backwards
* compatibility with older operating systems.
*/
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
#include <fsl_ddrc_version.h>
#if defined(CONFIG_ARCH_MPC8548)
#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#elif defined(CONFIG_ARCH_P1021)
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P1023)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 2
#define CFG_SYS_QMAN_NUM_PORTALS 3
#define CFG_SYS_BMAN_NUM_PORTALS 3
#define CFG_SYS_FM_MURAM_SIZE 0x10000
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P2020)
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM2_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_10GEC 1
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040)
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_DTSEC 5
#define CFG_SYS_NUM_FM2_10GEC 1
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_NUM_FM2_DTSEC 8
#define CFG_SYS_NUM_FM2_10GEC 2
#else
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_NUM_FM2_DTSEC 8
#define CFG_SYS_NUM_FM2_10GEC 1
#endif
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRDS_3
#define CFG_SYS_FSL_SRDS_4
#define CFG_SYS_NUM_FMAN 2
#define CFG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM1_CLK 3
#define CFG_SYS_FM2_CLK 3
#define CFG_SYS_FM_MURAM_SIZE 0x60000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CFG_SYS_FM_MURAM_SIZE 0x60000
#ifdef CONFIG_ARCH_B4860
#define CONFIG_NUM_DSP_CPUS 6
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 6
#define CFG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 0
#endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_PME_PLAT_CLK_DIV 2
#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
#define CFG_SYS_FM_MURAM_SIZE 0x30000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024)
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 4
#define CFG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
#define CFG_SYS_FM_MURAM_SIZE 0x30000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T2080)
#define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080)
#define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CFG_SYS_FM1_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FM_MURAM_SIZE 0x28000
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
#endif /* _ASM_MPC85xx_CONFIG_H_ */