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u-boot/arch/arm/mach-socfpga/Kconfig

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ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
if ARCH_SOCFPGA
arm: socfpga: gen5: fix ERR_PTR_OFFSET The default implementation of ERR_PTR/PTR_ERR maps errno values at the and of the address range (e.g. -EINVAL/-22 gets 0xFFFFFFEA). For socfpga gen5 SPL, this doesn't really work, as the heap is nearly at the end of the 32 bit address range. This patch adjusts the ERR_PTR_OFFSET to map errno values into the range of the Boot ROM, which should not be used for valid pointers. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-10-22 19:29:48 +00:00
config ERR_PTR_OFFSET
default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
arm: socfpga: imply/default common config options This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:05 +00:00
config NR_DRAM_BANKS
default 1
arm: socfpga: provide default SPL_SIZE_LIMIT for gen5 This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-13 19:50:28 +00:00
config SPL_SIZE_LIMIT
spl: Convert CONFIG_SPL_SIZE_LIMIT to hex This is currently a decimal value which is not as convenient or meaningful. Also U-Boot tends to use hex everywhere. Convert this option to hex and add a comment for the size_check macro. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the typo in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-25 14:56:28 +00:00
default 0x10000 if TARGET_SOCFPGA_GEN5
arm: socfpga: provide default SPL_SIZE_LIMIT for gen5 This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-13 19:50:28 +00:00
config SPL_SIZE_LIMIT_PROVIDE_STACK
default 0x200 if TARGET_SOCFPGA_GEN5
arm: socfpga: imply/default common config options This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:05 +00:00
config SPL_STACK_R_ADDR
default 0x00800000 if TARGET_SOCFPGA_GEN5
arm: socfpga: gen5: reduce SPL pre-reloc malloc By enabling debug prints in malloc_simple, we can see that SPL for socfpga gen5 does by far not need the 8 KiB malloc pool currently allocated for SPL in pre-reloc phase. On socfpga_socrates, 1304 bytes are currently used (and this increases by ~200 bytes only for the sdram/reset fixes in socfpga-next). To prevent wasting precious SRAM space, let's reduce the initial heap used for SPL to 2 KiB. This is still some hundred bytes more than currently used. Also, the gen5 SPL enables stack and heap in DDR memory pretty early. Only the initial uclass/dm parsing, serial console and DDR initialization is done in the initial heap, so these 2 KiB should be enough for all boards. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:06 +00:00
config SPL_SYS_MALLOC_F_LEN
default 0x800 if TARGET_SOCFPGA_GEN5
SPL: add support to boot from a partition type the socfpga bootrom supports mmc booting from either a raw image starting at 0x0, or from a partition of type 0xa2. This patch adds support for locating the boot image in the first type 0xa2 partition found. Assigned a partition number of -1 will cause a search for a partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE and use it to find the u-boot image Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
2017-02-11 01:15:34 +00:00
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
default 0xa2
arm: socfpga: imply/default common config options This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:05 +00:00
config SYS_MALLOC_F_LEN
default 0x2000 if TARGET_SOCFPGA_ARRIA10
default 0x2000 if TARGET_SOCFPGA_GEN5
config SYS_TEXT_BASE
default 0x01000040 if TARGET_SOCFPGA_ARRIA10
default 0x01000040 if TARGET_SOCFPGA_GEN5
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
config TARGET_SOCFPGA_AGILEX
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
arm: socfpga: soc64: Enable FIT image generation using binman Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2020-12-24 10:21:12 +00:00
select BINMAN if SPL_ATF
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
select CLK
arm: socfpga: agilex: Enable FPGA Full Reconfiguration support Enable FPGA full reconfiguration support with Intel FPGA SDM Mailbox driver for Agilex. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-08-07 03:50:05 +00:00
select FPGA_INTEL_SDM_MAILBOX
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
select NCORE_CACHE
select SPL_CLK if SPL
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
config TARGET_SOCFPGA_ARRIA5
bool
arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV || AV. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-02 19:31:25 +00:00
select TARGET_SOCFPGA_GEN5
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:48 +00:00
config TARGET_SOCFPGA_ARRIA10
bool
ddr: altera: Compile ALTERA SDRAM in SPL only Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-06 01:55:59 +00:00
select SPL_ALTERA_SDRAM
Kconfig: Sort bool, default, select and imply options Another round of sorting Kconfig entries aplhabetically. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-23 13:55:15 +00:00
select SPL_BOARD_INIT if SPL
arm: socfpga: arria10: Enable cache driver in SPL Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE to enable cache driver in SPL. This fixed error below in SPL: cache controller driver NOT found! Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-07 07:43:14 +00:00
select SPL_CACHE if SPL
ARM: socfpga: clk: Obtain handoff base clock via DM Bind fixed clock driver to the base clock instantiated in the handoff DT and use DM clock framework to get their clock rate. This replaces the ad-hoc DT parsing present thus far. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-07-30 13:56:19 +00:00
select CLK
select SPL_CLK if SPL
ARM: socfpga: Enable DM I2C framework on A10 Enable the DM I2C framework on Arria10, so that the DM capable Designware I2C driver can handle the reset via DM reset framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 16:32:38 +00:00
select DM_I2C
ARM: socfpga: Enable DM reset framework on A10 Enable the DM reset framework and DM reset driver on Arria10 both in U-Boot and in SPL. This lets U-Boot parse reset control from DT. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 16:32:38 +00:00
select DM_RESET
select SPL_DM_RESET if SPL
ARM: socfpga: Remove adhoc ethernet reset and configuration Remove ad-hoc ethernet syscon registers configuration and reset support. Reset is now handled by the reset framework and the syscon registers are set in the dwmac_socfpga.c driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
2018-08-13 18:06:46 +00:00
select REGMAP
select SPL_REGMAP if SPL
select SYSCON
select SPL_SYSCON if SPL
select ETH_DESIGNWARE_SOCFPGA
arm: socfpga: imply/default common config options This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:05 +00:00
imply FPGA_SOCFPGA
spl: Allow tiny printf() to be controlled in SPL and TPL At present there is only one control for this and it is used for both SPL and TPL. But SPL might have a lot more space than TPL so the extra cost of a full printf() might be acceptable. Split the option into two, providing separate SPL and TPL controls. The TPL setting defaults to the same as SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-25 14:56:27 +00:00
imply SPL_USE_TINY_PRINTF
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:48 +00:00
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
config TARGET_SOCFPGA_CYCLONE5
bool
arm: socfpga: introduce TARGET_SOCFPGA_GEN5 config property In order to re-use as much Cyclone5 and Arria5 code as possible to support the Arria10 platform, we need to wrap some of the code with #ifdef's. By adding CONFIG_TARGET_SOCFPGA_GEN5, we can shorten the check by not having to check for both AV || AV. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-02 19:31:25 +00:00
select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_GEN5
bool
ddr: altera: Compile ALTERA SDRAM in SPL only Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-05-06 01:55:59 +00:00
select SPL_ALTERA_SDRAM
arm: socfpga: imply/default common config options This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:05 +00:00
imply FPGA_SOCFPGA
arm: socfpga: provide default SPL_SIZE_LIMIT for gen5 This provides an SPL_SIZE_LIMIT that makes the build check that the SPL binary loaded from flash fits into the SRAM (64 KiB) and leaves enough room for global data, heap and stack (512 bytes assumed stack usage). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-13 19:50:28 +00:00
imply SPL_SIZE_LIMIT_SUBTRACT_GD
imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
arm: socfpga: imply/default common config options This commit moves common config options used in all socfpga boards to select/imply in Kconfig. This both cleans up the defconfig files as well as makes future changes easier. Options implied/defaulted for all sub-arches: - SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS Options implied/defaulted for implied for A10 & gen5: - FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE Options implied/defaulted for gen5: - SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Marek Vasut <marex@denx.de>
2019-04-09 19:02:05 +00:00
imply SPL_STACK_R
imply SPL_SYS_MALLOC_SIMPLE
spl: Allow tiny printf() to be controlled in SPL and TPL At present there is only one control for this and it is used for both SPL and TPL. But SPL might have a lot more space than TPL so the extra cost of a full printf() might be acceptable. Split the option into two, providing separate SPL and TPL controls. The TPL setting defaults to the same as SPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-25 14:56:27 +00:00
imply SPL_USE_TINY_PRINTF
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
arm: socfpga: stratix10: Enable Stratix10 SoC build Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-05-23 16:17:32 +00:00
config TARGET_SOCFPGA_STRATIX10
bool
select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN
arm: socfpga: soc64: Enable FIT image generation using binman Enable BINMAN when using Arm-Trusted-Firmware (ATF) to generate FIT images. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2020-12-24 10:21:12 +00:00
select BINMAN if SPL_ATF
fpga: altera: Rename Stratix10 FPGA to Intel FPGA SDM Mailbox Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-08-07 03:50:03 +00:00
select FPGA_INTEL_SDM_MAILBOX
arm: socfpga: stratix10: Enable Stratix10 SoC build Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-05-23 16:17:32 +00:00
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
choice
prompt "Altera SOCFPGA board select"
arch: Make board selection choices optional By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
2015-05-12 19:46:23 +00:00
optional
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
config TARGET_SOCFPGA_AGILEX_SOCDK
bool "Intel SOCFPGA SoCDK (Agilex)"
select TARGET_SOCFPGA_AGILEX
arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board Re-add support for Aries Embedded MCV SoM, which is CycloneV based and the associated MCVEVK and MCVEVP baseboard. The board can boot from eMMC. Ethernet and USB is supported. The Aries Embedded boards have been removed with commit 03b54997d568 ("board/aries: Remove"). I will now take care of them. The device-tree files are from mainline Linux commit e93c9c99a629 ("Linux v5.1)". Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> CC: Marek Vasut <marex@denx.de> CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-12 17:25:18 +00:00
config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:48 +00:00
config TARGET_SOCFPGA_ARRIA10_SOCDK
bool "Altera SOCFPGA SoCDK (Arria 10)"
select TARGET_SOCFPGA_ARRIA10
ARM: socfpga: Add initial support for the ABB SECU board Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-19 18:55:14 +00:00
config TARGET_SOCFPGA_ARRIA5_SECU1
bool "ABB SECU1 (Arria V)"
select TARGET_SOCFPGA_ARRIA5
select VENDOR_KM
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board Add support for a new boards from devboards.de , the DBM-SoC1 . This board has one ethernet port, one USB OTG port and USB UART. Signed-off-by: Marek Vasut <marex@denx.de>
2018-02-24 22:34:00 +00:00
config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
bool "Devboards DBM-SoC1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 16:06:27 +00:00
config TARGET_SOCFPGA_EBV_SOCRATES
bool "EBV SoCrates (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: add support for IS1 board This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
2016-06-07 10:37:23 +00:00
config TARGET_SOCFPGA_IS1
bool "IS1 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: vining_fpga: Rename VINING|FPGA The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-26 22:19:31 +00:00
config TARGET_SOCFPGA_SOFTING_VINING_FPGA
bool "Softing VIN|ING FPGA (Cyclone V)"
Kconfig: Migrate BOARD_LATE_INIT to a select This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
2017-01-23 00:43:11 +00:00
select BOARD_LATE_INIT
arm: socfpga: Add samtec VIN|ING board Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
2015-12-01 17:09:52 +00:00
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: Sort Kconfig entries Just sort the board entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-08 00:57:05 +00:00
config TARGET_SOCFPGA_SR1500
bool "SR1500 (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: stratix10: Enable Stratix10 SoC build Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-05-23 16:17:32 +00:00
config TARGET_SOCFPGA_STRATIX10_SOCDK
bool "Intel SOCFPGA SoCDK (Stratix 10)"
select TARGET_SOCFPGA_STRATIX10
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 22:41:52 +00:00
config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 15:11:16 +00:00
config TARGET_SOCFPGA_TERASIC_DE10_NANO
bool "Terasic DE10-Nano (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 15:07:10 +00:00
config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 15:28:53 +00:00
config TARGET_SOCFPGA_TERASIC_SOCKIT
bool "Terasic SoCkit (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
endchoice
config SYS_BOARD
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
arm: socfpga: Split Altera socfpga into AV and CV SoCDK The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-10 19:24:53 +00:00
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:48 +00:00
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
arm: socfpga: Split Altera socfpga into AV and CV SoCDK The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-10 19:24:53 +00:00
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board Add support for a new boards from devboards.de , the DBM-SoC1 . This board has one ethernet port, one USB OTG port and USB UART. Signed-off-by: Marek Vasut <marex@denx.de>
2018-02-24 22:34:00 +00:00
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 22:41:52 +00:00
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 15:07:10 +00:00
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 15:11:16 +00:00
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
ARM: socfpga: add support for IS1 board This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
2016-06-07 10:37:23 +00:00
default "is1" if TARGET_SOCFPGA_IS1
arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board Re-add support for Aries Embedded MCV SoM, which is CycloneV based and the associated MCVEVK and MCVEVP baseboard. The board can boot from eMMC. Ethernet and USB is supported. The Aries Embedded boards have been removed with commit 03b54997d568 ("board/aries: Remove"). I will now take care of them. The device-tree files are from mainline Linux commit e93c9c99a629 ("Linux v5.1)". Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> CC: Marek Vasut <marex@denx.de> CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-12 17:25:18 +00:00
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
ARM: socfpga: Add initial support for the ABB SECU board Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-19 18:55:14 +00:00
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 15:28:53 +00:00
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 16:06:27 +00:00
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
arm: socfpga: Add SoCFPGA SR1500 board The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2015-11-18 10:06:09 +00:00
default "sr1500" if TARGET_SOCFPGA_SR1500
arm: socfpga: stratix10: Enable Stratix10 SoC build Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-05-23 16:17:32 +00:00
default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
ARM: socfpga: vining_fpga: Rename VINING|FPGA The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-26 22:19:31 +00:00
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
config SYS_VENDOR
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:48 +00:00
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
arm: socfpga: Unbind CPU type from board type The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-02 19:57:57 +00:00
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
arm: socfpga: stratix10: Enable Stratix10 SoC build Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-05-23 16:17:32 +00:00
default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board Re-add support for Aries Embedded MCV SoM, which is CycloneV based and the associated MCVEVK and MCVEVP baseboard. The board can boot from eMMC. Ethernet and USB is supported. The Aries Embedded boards have been removed with commit 03b54997d568 ("board/aries: Remove"). I will now take care of them. The device-tree files are from mainline Linux commit e93c9c99a629 ("Linux v5.1)". Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> CC: Marek Vasut <marex@denx.de> CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-12 17:25:18 +00:00
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board Add support for a new boards from devboards.de , the DBM-SoC1 . This board has one ethernet port, one USB OTG port and USB UART. Signed-off-by: Marek Vasut <marex@denx.de>
2018-02-24 22:34:00 +00:00
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 16:06:27 +00:00
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
ARM: socfpga: Add initial support for the ABB SECU board Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-19 18:55:14 +00:00
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
ARM: socfpga: vining_fpga: Rename VINING|FPGA The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-26 22:19:31 +00:00
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 22:41:52 +00:00
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 15:07:10 +00:00
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 15:11:16 +00:00
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 15:28:53 +00:00
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
arm: socfpga: agilex: Enable Agilex SoC build Add build support for Agilex SoC. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-11-27 07:55:32 +00:00
default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
ARM: socfpga: Add initial support for the ABB SECU board Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-19 18:55:14 +00:00
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-22 22:01:32 +00:00
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
arm: socfpga: Enable build for Arria 10 Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-04-25 18:44:48 +00:00
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files Rename the socfpga_cyclone5.h to socfpga_cyclone5_socdk.h, and socfpga_arria.h to socfpga_arria5_socdk.h. This matches the other SoCFPGA board config files. Suggested-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-22 22:01:32 +00:00
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
ARM: socfpga: Add new CycloneV SoC Devboards DBM-SoC1 board Add support for a new boards from devboards.de , the DBM-SoC1 . This board has one ethernet port, one USB OTG port and USB UART. Signed-off-by: Marek Vasut <marex@denx.de>
2018-02-24 22:34:00 +00:00
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
arm: socfpga: Add support for the Terasic DE-0 Atlas board Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-01 22:41:52 +00:00
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
socfpga: add support for Terasic DE1-SoC board Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
2016-11-14 15:07:10 +00:00
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
arm: socfpga: add cyclone5 based de10-nano board Add support for the Terasic DE10-Nano board. The board is based on the DE0-Nano-Soc board but adds a larger FPGA and an HDMI output. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
2017-04-18 15:11:16 +00:00
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
ARM: socfpga: add support for IS1 board This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
2016-06-07 10:37:23 +00:00
default "socfpga_is1" if TARGET_SOCFPGA_IS1
arm: socfpga: Re-add support for Aries MCV SoM and MCVEV[KP] board Re-add support for Aries Embedded MCV SoM, which is CycloneV based and the associated MCVEVK and MCVEVP baseboard. The board can boot from eMMC. Ethernet and USB is supported. The Aries Embedded boards have been removed with commit 03b54997d568 ("board/aries: Remove"). I will now take care of them. The device-tree files are from mainline Linux commit e93c9c99a629 ("Linux v5.1)". Signed-off-by: Wolfgang Grandegger <wg@aries-embedded.de> CC: Marek Vasut <marex@denx.de> CC: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-05-12 17:25:18 +00:00
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
arm: socfpga: Add support for Terasic SoCkit board Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
2015-06-21 15:28:53 +00:00
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
arm: socfpga: Repair SoCrates board This board was constantly parasiting on the CV SoCDK, so split it into it's own separate directory. Moreover, the board config was missing important bits, like simple-bus support in SPL, the DRAM configuration was incorrect and the DTS was also missing the pre reloc bits. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Jan Viktorin <viktorin@rehivetech.com>
2015-11-23 16:06:27 +00:00
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
arm: socfpga: Add SoCFPGA SR1500 board The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2015-11-18 10:06:09 +00:00
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
arm: socfpga: stratix10: Enable Stratix10 SoC build Add build support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Conflicts: arch/arm/Kconfig arch/arm/mach-socfpga/Kconfig
2018-05-23 16:17:32 +00:00
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
ARM: socfpga: vining_fpga: Rename VINING|FPGA The company Samtec was merged into Softing, migrate the board over to the new name and update copyright headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Silvio Fricke <silvio.fricke@softing.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-06-26 22:19:31 +00:00
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
ARM: socfpga: Add initial support for the ABB SECU board Add initial support for the ABB SECU board, which is an ArriaV-based SoCFPGA system with ethernet and booting from Denali NAND. Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2020-02-19 18:55:14 +00:00
source "board/keymile/Kconfig"
ARM: socfpga: move board select into mach-socfpga/Kconfig Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-04-21 11:38:20 +00:00
endif
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