2015-04-21 11:38:20 +00:00
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|
|
if ARCH_SOCFPGA
|
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|
|
|
2019-10-22 19:29:48 +00:00
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|
|
config ERR_PTR_OFFSET
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|
|
|
default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
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|
|
|
|
2019-04-09 19:02:05 +00:00
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|
|
config NR_DRAM_BANKS
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|
default 1
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|
2021-03-01 12:04:11 +00:00
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|
|
config SOCFPGA_SECURE_VAB_AUTH
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|
|
|
bool "Enable boot image authentication with Secure Device Manager"
|
2021-08-10 03:26:42 +00:00
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|
|
depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
|
2021-03-01 12:04:11 +00:00
|
|
|
select FIT_IMAGE_POST_PROCESS
|
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|
|
select SHA384
|
2021-09-03 00:54:18 +00:00
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|
|
select SHA512
|
2021-03-01 12:04:11 +00:00
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|
|
select SPL_FIT_IMAGE_POST_PROCESS
|
|
|
|
help
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|
|
All images loaded from FIT will be authenticated by Secure Device
|
|
|
|
Manager.
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|
|
config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
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|
|
bool "Allow non-FIT VAB signed images"
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|
|
|
depends on SOCFPGA_SECURE_VAB_AUTH
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|
|
|
|
2019-06-13 19:50:28 +00:00
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|
|
config SPL_SIZE_LIMIT
|
2019-09-25 14:56:28 +00:00
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|
|
default 0x10000 if TARGET_SOCFPGA_GEN5
|
2019-06-13 19:50:28 +00:00
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|
|
|
|
|
|
config SPL_SIZE_LIMIT_PROVIDE_STACK
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|
|
|
default 0x200 if TARGET_SOCFPGA_GEN5
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|
|
|
|
2019-04-09 19:02:05 +00:00
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|
|
config SPL_STACK_R_ADDR
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|
|
default 0x00800000 if TARGET_SOCFPGA_GEN5
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|
|
|
|
2019-04-09 19:02:06 +00:00
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|
|
config SPL_SYS_MALLOC_F_LEN
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|
|
default 0x800 if TARGET_SOCFPGA_GEN5
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|
|
|
2017-02-11 01:15:34 +00:00
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|
|
config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
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default 0xa2
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|
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|
2019-04-09 19:02:05 +00:00
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|
|
config SYS_MALLOC_F_LEN
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|
default 0x2000 if TARGET_SOCFPGA_ARRIA10
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|
default 0x2000 if TARGET_SOCFPGA_GEN5
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|
|
|
|
|
|
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config SYS_TEXT_BASE
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default 0x01000040 if TARGET_SOCFPGA_ARRIA10
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|
|
|
default 0x01000040 if TARGET_SOCFPGA_GEN5
|
|
|
|
|
2019-11-27 07:55:32 +00:00
|
|
|
config TARGET_SOCFPGA_AGILEX
|
|
|
|
bool
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|
|
|
select ARMV8_MULTIENTRY
|
|
|
|
select ARMV8_SET_SMPEN
|
2020-12-24 10:21:12 +00:00
|
|
|
select BINMAN if SPL_ATF
|
2019-11-27 07:55:32 +00:00
|
|
|
select CLK
|
2020-08-07 03:50:05 +00:00
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|
|
select FPGA_INTEL_SDM_MAILBOX
|
2019-11-27 07:55:32 +00:00
|
|
|
select NCORE_CACHE
|
|
|
|
select SPL_CLK if SPL
|
2021-03-01 12:04:10 +00:00
|
|
|
select TARGET_SOCFPGA_SOC64
|
2019-11-27 07:55:32 +00:00
|
|
|
|
2015-08-02 19:57:57 +00:00
|
|
|
config TARGET_SOCFPGA_ARRIA5
|
|
|
|
bool
|
2015-12-02 19:31:25 +00:00
|
|
|
select TARGET_SOCFPGA_GEN5
|
2015-08-02 19:57:57 +00:00
|
|
|
|
2017-04-25 18:44:48 +00:00
|
|
|
config TARGET_SOCFPGA_ARRIA10
|
|
|
|
bool
|
2019-05-06 01:55:59 +00:00
|
|
|
select SPL_ALTERA_SDRAM
|
2018-07-23 13:55:15 +00:00
|
|
|
select SPL_BOARD_INIT if SPL
|
2020-04-07 07:43:14 +00:00
|
|
|
select SPL_CACHE if SPL
|
2018-07-30 13:56:19 +00:00
|
|
|
select CLK
|
|
|
|
select SPL_CLK if SPL
|
2018-08-13 16:32:38 +00:00
|
|
|
select DM_I2C
|
2018-08-13 16:32:38 +00:00
|
|
|
select DM_RESET
|
|
|
|
select SPL_DM_RESET if SPL
|
2018-08-13 18:06:46 +00:00
|
|
|
select REGMAP
|
|
|
|
select SPL_REGMAP if SPL
|
|
|
|
select SYSCON
|
|
|
|
select SPL_SYSCON if SPL
|
|
|
|
select ETH_DESIGNWARE_SOCFPGA
|
2019-04-09 19:02:05 +00:00
|
|
|
imply FPGA_SOCFPGA
|
2019-09-25 14:56:27 +00:00
|
|
|
imply SPL_USE_TINY_PRINTF
|
2017-04-25 18:44:48 +00:00
|
|
|
|
2015-08-02 19:57:57 +00:00
|
|
|
config TARGET_SOCFPGA_CYCLONE5
|
|
|
|
bool
|
2015-12-02 19:31:25 +00:00
|
|
|
select TARGET_SOCFPGA_GEN5
|
|
|
|
|
|
|
|
config TARGET_SOCFPGA_GEN5
|
|
|
|
bool
|
2019-05-06 01:55:59 +00:00
|
|
|
select SPL_ALTERA_SDRAM
|
2019-04-09 19:02:05 +00:00
|
|
|
imply FPGA_SOCFPGA
|
2019-06-13 19:50:28 +00:00
|
|
|
imply SPL_SIZE_LIMIT_SUBTRACT_GD
|
|
|
|
imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
|
2019-04-09 19:02:05 +00:00
|
|
|
imply SPL_STACK_R
|
|
|
|
imply SPL_SYS_MALLOC_SIMPLE
|
2019-09-25 14:56:27 +00:00
|
|
|
imply SPL_USE_TINY_PRINTF
|
2015-08-02 19:57:57 +00:00
|
|
|
|
2021-08-10 03:26:42 +00:00
|
|
|
config TARGET_SOCFPGA_N5X
|
|
|
|
bool
|
|
|
|
select ARMV8_MULTIENTRY
|
|
|
|
select ARMV8_SET_SMPEN
|
|
|
|
select BINMAN if SPL_ATF
|
|
|
|
select CLK
|
|
|
|
select FPGA_INTEL_SDM_MAILBOX
|
|
|
|
select NCORE_CACHE
|
|
|
|
select SPL_ALTERA_SDRAM
|
|
|
|
select SPL_CLK if SPL
|
|
|
|
select TARGET_SOCFPGA_SOC64
|
|
|
|
|
|
|
|
config TARGET_SOCFPGA_N5X_SOCDK
|
|
|
|
bool "Intel eASIC SoCDK (N5X)"
|
|
|
|
select TARGET_SOCFPGA_N5X
|
|
|
|
|
2021-03-01 12:04:10 +00:00
|
|
|
config TARGET_SOCFPGA_SOC64
|
|
|
|
bool
|
|
|
|
|
2018-05-23 16:17:32 +00:00
|
|
|
config TARGET_SOCFPGA_STRATIX10
|
|
|
|
bool
|
|
|
|
select ARMV8_MULTIENTRY
|
|
|
|
select ARMV8_SET_SMPEN
|
2020-12-24 10:21:12 +00:00
|
|
|
select BINMAN if SPL_ATF
|
2020-08-07 03:50:03 +00:00
|
|
|
select FPGA_INTEL_SDM_MAILBOX
|
2021-03-01 12:04:10 +00:00
|
|
|
select TARGET_SOCFPGA_SOC64
|
2018-05-23 16:17:32 +00:00
|
|
|
|
2015-04-21 11:38:20 +00:00
|
|
|
choice
|
|
|
|
prompt "Altera SOCFPGA board select"
|
2015-05-12 19:46:23 +00:00
|
|
|
optional
|
2015-04-21 11:38:20 +00:00
|
|
|
|
2019-11-27 07:55:32 +00:00
|
|
|
config TARGET_SOCFPGA_AGILEX_SOCDK
|
|
|
|
bool "Intel SOCFPGA SoCDK (Agilex)"
|
|
|
|
select TARGET_SOCFPGA_AGILEX
|
|
|
|
|
2019-05-12 17:25:18 +00:00
|
|
|
config TARGET_SOCFPGA_ARIES_MCVEVK
|
|
|
|
bool "Aries MCVEVK (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2017-04-25 18:44:48 +00:00
|
|
|
config TARGET_SOCFPGA_ARRIA10_SOCDK
|
|
|
|
bool "Altera SOCFPGA SoCDK (Arria 10)"
|
|
|
|
select TARGET_SOCFPGA_ARRIA10
|
|
|
|
|
2020-02-19 18:55:14 +00:00
|
|
|
config TARGET_SOCFPGA_ARRIA5_SECU1
|
|
|
|
bool "ABB SECU1 (Arria V)"
|
|
|
|
select TARGET_SOCFPGA_ARRIA5
|
|
|
|
select VENDOR_KM
|
|
|
|
|
2015-08-02 19:57:57 +00:00
|
|
|
config TARGET_SOCFPGA_ARRIA5_SOCDK
|
|
|
|
bool "Altera SOCFPGA SoCDK (Arria V)"
|
|
|
|
select TARGET_SOCFPGA_ARRIA5
|
2015-04-21 11:38:20 +00:00
|
|
|
|
2015-08-02 19:57:57 +00:00
|
|
|
config TARGET_SOCFPGA_CYCLONE5_SOCDK
|
|
|
|
bool "Altera SOCFPGA SoCDK (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
2015-04-21 11:38:20 +00:00
|
|
|
|
2018-02-24 22:34:00 +00:00
|
|
|
config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
|
|
|
|
bool "Devboards DBM-SoC1 (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-11-23 16:06:27 +00:00
|
|
|
config TARGET_SOCFPGA_EBV_SOCRATES
|
|
|
|
bool "EBV SoCrates (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2016-06-07 10:37:23 +00:00
|
|
|
config TARGET_SOCFPGA_IS1
|
|
|
|
bool "IS1 (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2019-06-26 22:19:31 +00:00
|
|
|
config TARGET_SOCFPGA_SOFTING_VINING_FPGA
|
|
|
|
bool "Softing VIN|ING FPGA (Cyclone V)"
|
2017-01-23 00:43:11 +00:00
|
|
|
select BOARD_LATE_INIT
|
2015-12-01 17:09:52 +00:00
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2016-06-08 00:57:05 +00:00
|
|
|
config TARGET_SOCFPGA_SR1500
|
|
|
|
bool "SR1500 (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2018-05-23 16:17:32 +00:00
|
|
|
config TARGET_SOCFPGA_STRATIX10_SOCDK
|
|
|
|
bool "Intel SOCFPGA SoCDK (Stratix 10)"
|
|
|
|
select TARGET_SOCFPGA_STRATIX10
|
|
|
|
|
2015-09-01 22:41:52 +00:00
|
|
|
config TARGET_SOCFPGA_TERASIC_DE0_NANO
|
|
|
|
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2017-04-18 15:11:16 +00:00
|
|
|
config TARGET_SOCFPGA_TERASIC_DE10_NANO
|
|
|
|
bool "Terasic DE10-Nano (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2022-05-23 01:54:57 +00:00
|
|
|
config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
|
|
|
|
bool "Terasic DE10-Standard (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2016-11-14 15:07:10 +00:00
|
|
|
config TARGET_SOCFPGA_TERASIC_DE1_SOC
|
|
|
|
bool "Terasic DE1-SoC (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-06-21 15:28:53 +00:00
|
|
|
config TARGET_SOCFPGA_TERASIC_SOCKIT
|
|
|
|
bool "Terasic SoCkit (Cyclone V)"
|
|
|
|
select TARGET_SOCFPGA_CYCLONE5
|
|
|
|
|
2015-04-21 11:38:20 +00:00
|
|
|
endchoice
|
|
|
|
|
|
|
|
config SYS_BOARD
|
2019-11-27 07:55:32 +00:00
|
|
|
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
|
2015-08-10 19:24:53 +00:00
|
|
|
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
2017-04-25 18:44:48 +00:00
|
|
|
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
|
2015-08-10 19:24:53 +00:00
|
|
|
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
2018-02-24 22:34:00 +00:00
|
|
|
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
|
2015-09-01 22:41:52 +00:00
|
|
|
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
2016-11-14 15:07:10 +00:00
|
|
|
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
|
2017-04-18 15:11:16 +00:00
|
|
|
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
|
2022-05-23 01:54:57 +00:00
|
|
|
default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
|
2016-06-07 10:37:23 +00:00
|
|
|
default "is1" if TARGET_SOCFPGA_IS1
|
2019-05-12 17:25:18 +00:00
|
|
|
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
|
2021-08-10 03:26:42 +00:00
|
|
|
default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
|
2020-02-19 18:55:14 +00:00
|
|
|
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
|
2015-06-21 15:28:53 +00:00
|
|
|
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
2015-11-23 16:06:27 +00:00
|
|
|
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
|
2015-11-18 10:06:09 +00:00
|
|
|
default "sr1500" if TARGET_SOCFPGA_SR1500
|
2018-05-23 16:17:32 +00:00
|
|
|
default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
|
2019-06-26 22:19:31 +00:00
|
|
|
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
|
2015-04-21 11:38:20 +00:00
|
|
|
|
|
|
|
config SYS_VENDOR
|
2019-11-27 07:55:32 +00:00
|
|
|
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
|
2021-08-10 03:26:42 +00:00
|
|
|
default "intel" if TARGET_SOCFPGA_N5X_SOCDK
|
2015-08-02 19:57:57 +00:00
|
|
|
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
2017-04-25 18:44:48 +00:00
|
|
|
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
|
2015-08-02 19:57:57 +00:00
|
|
|
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
2018-05-23 16:17:32 +00:00
|
|
|
default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
|
2019-05-12 17:25:18 +00:00
|
|
|
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
|
2018-02-24 22:34:00 +00:00
|
|
|
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
|
2015-11-23 16:06:27 +00:00
|
|
|
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
|
2020-02-19 18:55:14 +00:00
|
|
|
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
|
2019-06-26 22:19:31 +00:00
|
|
|
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
|
2015-09-01 22:41:52 +00:00
|
|
|
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
2016-11-14 15:07:10 +00:00
|
|
|
default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
|
2017-04-18 15:11:16 +00:00
|
|
|
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
|
2022-05-23 01:54:57 +00:00
|
|
|
default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
|
2015-06-21 15:28:53 +00:00
|
|
|
default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
2015-04-21 11:38:20 +00:00
|
|
|
|
|
|
|
config SYS_SOC
|
|
|
|
default "socfpga"
|
|
|
|
|
|
|
|
config SYS_CONFIG_NAME
|
2019-11-27 07:55:32 +00:00
|
|
|
default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
|
2020-02-19 18:55:14 +00:00
|
|
|
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
|
2015-09-22 22:01:32 +00:00
|
|
|
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
|
2017-04-25 18:44:48 +00:00
|
|
|
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
|
2015-09-22 22:01:32 +00:00
|
|
|
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
|
2018-02-24 22:34:00 +00:00
|
|
|
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
|
2015-09-01 22:41:52 +00:00
|
|
|
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
|
2016-11-14 15:07:10 +00:00
|
|
|
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
|
2017-04-18 15:11:16 +00:00
|
|
|
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
|
2022-05-23 01:54:57 +00:00
|
|
|
default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
|
2016-06-07 10:37:23 +00:00
|
|
|
default "socfpga_is1" if TARGET_SOCFPGA_IS1
|
2019-05-12 17:25:18 +00:00
|
|
|
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
|
2021-08-10 03:26:42 +00:00
|
|
|
default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
|
2015-06-21 15:28:53 +00:00
|
|
|
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
|
2015-11-23 16:06:27 +00:00
|
|
|
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
|
2015-11-18 10:06:09 +00:00
|
|
|
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
|
2018-05-23 16:17:32 +00:00
|
|
|
default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
|
2019-06-26 22:19:31 +00:00
|
|
|
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
|
2015-04-21 11:38:20 +00:00
|
|
|
|
|
|
|
endif
|