Commit graph

46 commits

Author SHA1 Message Date
Simon Glass
21ccce1ba5 dm: pci: Add a dm_ prefix to pci_get_bdf()
Most driver model PCI functions have a dm_ prefix. At some point, when the
old code is converted to driver model and the old functions are removed, we
will drop that prefix.

For consistency, we should use the dm_ prefix for all driver model
functions. Update pci_get_bdf() accordingly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Marek Vasut
2b26109219 net: designware: Zap trailing backslash
Trailing backslashes are necessary only in macros, not in the actual
code, so remove them.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2015-12-22 04:42:27 +01:00
Thomas Chou
25af71c4bf net: eth_designware: select PHYLIB in Kconfig
Select PHYLIB in drivers/net/Kconfig. And remove CONFIG_PHYLIB
from legacy board header files.

This fixed the warnings when both ALTERA_TSE and ETH_DESIGNWARE
are selected.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reported-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
Tested-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-12-22 04:42:27 +01:00
Bin Meng
5d2459fd46 net: designware: Add driver remove support
In designware_eth_probe(), some additional resources are allocated
(eg: mdio, phy). We should free these in the driver remove phase.
Add designware_eth_remove() to clean it up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-29 14:05:50 -05:00
Bin Meng
8b7ee66cec net: designware: Add support to PCI designware devices
The Designware ethernet controller is also seen on PCI bus, e.g.
on Intel Quark SoC. Add this support in the DM version driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-16 19:53:52 -06:00
Bin Meng
f0dc73c090 net: designware: Fix build warnings
When building dm version of designware eth driver on a platform
with 64-bit phys_addr_t, it reports the following warnings:

  drivers/net/designware.c: In function 'designware_eth_probe':
  drivers/net/designware.c:599:2:
    warning: format '%lx' expects argument of type 'long unsigned int',
    but argument 3 has type 'phys_addr_t' [-Wformat]
  drivers/net/designware.c:600:21:
    warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  drivers/net/designware.c:601:21:
    warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

This commit fixes the build warnings.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Marek Vasut
9f76f105c7 net: designware: Rename the driver var name to eth_designware
The driver variable name is eth_sandbox, which is probably a copy-paste
mistake. Fix it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-08 14:14:05 +02:00
Marek Vasut
b9628595b4 net: designware: Add SoCFPGA GMAC DT compatible string
Add the OF compatible property to match the SoCFPGA GMAC.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-08 14:14:05 +02:00
Simon Glass
a1ca92eaaf dm: eth: Avoid blocking on packet reception
Some devices can take a long time to work out whether they have a new packet
or now. For example the ASIX USB Ethernet dongle can take 5 seconds to do
this, since it waits until it gets a new packet on the wire before allowing
the USB bulk read packet to be submitted.

At present with driver mode the Ethernet receive code reads 32 packets. This
can take a very long time if we must wait for all 32 packets. The old code
(before driver model) worked by reading a single set of packets from the USB
device, then processing all the packets with in. It would be nice to use
the same behaviour with driver model.

Add a flag to the receive method which indicates that the driver should try
to find a packet if available, by consulting the hardware. When the flag is
not set, it should just return any packet data it has already received. If
there is none, it should return -EAGAIN so that the loop will terminate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-07-21 17:39:40 -06:00
Bin Meng
f3edfd3054 net: designware: Program MAC address to hardware after soft reset
commit f566c99 "net: Update hardware MAC address if it changes in env"
removes writing MAC address to designware controller after soft reset.
This makes designware ethernet port fail to work. Actually the MAC
address should always be programmed after soft reset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-07-08 13:43:19 -04:00
Joe Hershberger
f566c9949f net: Update hardware MAC address if it changes in env
When the ethaddr changes in the env, the hardware should also be updated
so that MAC filtering will work properly without resetting U-Boot.

Also remove the manual calls to set the hwaddr that was included in a
few drivers as a result of the framework not doing it.

Reported-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
2015-05-19 13:33:21 -05:00
Simon Glass
75577ba45a dm: net: Adjust designware driver to support driver model
Add driver model support to the designware driver. This reuses most of the
existing code except for some duplication in the probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-18 11:11:37 -06:00
Simon Glass
64dcd25f55 dm: net: Tidy up designware driver ready for driver model
Adjust the error handling to use errno.h instead of returning -1. Change
leaf functions to pass in the arguments they require rather than struct
eth_device. Apart from simplifying the code it makes is easier to reuse
these functions for driver model, since mostly they actually only use
struct dw_eth_priv (which we can keep).

Create a stub for each Ethernet operation function. This will allow use to
share code with the driver model versions.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-04-18 11:11:37 -06:00
Joe Hershberger
1fd92db83d net: cosmetic: Fix var naming net <-> eth drivers
Update the naming convention used in the network stack functions and
variables that Ethernet drivers use to interact with it.

This cleans up the temporary hacks that were added to this interface
along with the DM support.

This patch has a few remaining checkpatch.pl failures that would be out
of the scope of this patch to fix (drivers that are in gross violation
of checkpatch.pl).

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:33 -06:00
Sonic Zhang
d227922150 net: Support DMA threshold mode in DWMAC driver
- DMA threshold mode can be selected in board config head file.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
2015-03-05 11:17:53 -05:00
Sonic Zhang
2ddaf13bd2 net: configure DWMAC DMA by default AXI burst length
Board can define its own AXI burst length to improve DWMAC DMA performance.

v2-changes:
- Avoid write burst len register when the Macro is not defined.

v3-changes:
- Add axi_bus register member to struct eth_dma_regs.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-03-05 11:17:53 -05:00
Alexey Brodkin
875143f324 net/designware: add error message on DMA reset timeout
If for some reason DMA module fails to reset user oserves only this:
--->---
# dhcp
Trying dwmac.e0018000
FAIL
--->---

This message makes not much sense.
With proposed change error message will be more helpful:
--->---
# dhcp
Trying dwmac.e0018000
DMA reset timeout
FAIL
--->---

For example user may do power toggle to recover board functionality.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2015-01-30 15:55:00 -06:00
Marek Vasut
96cec17d3c net: dwc: Make the cache handling less cryptic
Add a few new variables to make the cache handling less cryptic.
Add a variable for DMA and DATA descriptor start and end, so the
correctness of the code is easier to inspect.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Chin Liang See <clsee@altera.com>
2014-10-06 17:36:40 +02:00
Marek Vasut
4f68678b19 net: dwc: Fix cache alignment issues
Fix remaining cache alignment issues in the DWC Ethernet driver.
Please note that the cache handling in the driver is making the
code hideous and thus the next patch cleans that up. In order to
make this change reviewable though, the cleanup is split from it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06 17:36:40 +02:00
Ian Campbell
49692c5f51 net/designware: Make DMA burst length configurable and reduce by default
The correct value for this setting can vary across SoCs and boards, so make it
configurable.

Also reduce the default value to 8, which is the same default as used in the
Linux driver.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
2014-05-25 17:23:58 +02:00
Ian Campbell
964ea7c1ce net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGN
This is required at least on ARM.

When sending instead of simply invalidating the entire descriptor, flush
as little as possible while still respecting ARCH_DMA_MINALIGN, as
requested by Alexey.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
2014-05-25 17:23:15 +02:00
Ian Campbell
1c848a2586 net/designware: ensure device private data is DMA aligned.
struct dw_eth_dev contains fields which are accessed via DMA, so make sure it
is aligned to a dma boundary. Without this I see:
    ERROR: v7_dcache_inval_range - start address is not aligned - 0x7fb677e0

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Marek Vasut <marex@denx.de>
2014-05-25 17:23:12 +02:00
Ian Campbell
15e82e5309 net/designware: call phy_connect_dev() to properly setup phylib device
This sets up the linkage from the phydev back to the ethernet device. This
symptom of not doing this which I noticed was:
    <NULL> Waiting for PHY auto negotiation to complete....
rather than:
    dwmac.1c50000 Waiting for PHY auto negotiation to complete....

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
2014-05-12 16:31:51 -04:00
Alexey Brodkin
50b0df814b net/designware: make driver compatible with data cache
Up until now this driver only worked with data cache disabled.
To make it work with enabled data cache following changes were required:

 * Flush Tx/Rx buffer descriptors their modification
 * Invalidate Tx/Rx buffer descriptors before reading its values
 * Flush cache for data passed from CPU to GMAC
 * Invalidate cache for data passed from GMAC to CPU

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2014-02-07 09:17:05 -05:00
Alexey Brodkin
92a190aaab net/designware - switch driver to phylib usage
With this change driver will benefit from existing phylib and thus
custom phy functionality implemented in the driver will go away:
 * Instantiation of the driver is now much shorter - 2 parameters
instead of 4.
 * Simplified phy management/functoinality in driver is replaced with
rich functionality of phylib.
 * Support of custom phy initialization is now done with existing
"board_phy_config".

Note that after this change some previously used config options
(driver-specific PHY configuration) will be obsolete and they are simply
substituted with similar options of phylib.

For example:
 * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled
by default.
 * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy
explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise
automatically the first discovered on MDIO bus phy will be used

I believe there's no need now in "doc/README.designware_eth" because
user only needs to instantiate the driver with "designware_initialize"
whose prototype exists in "include/netdev.h".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2014-02-07 09:16:46 -05:00
Alexey Brodkin
74cb708d58 net/designware: add explicit reset of {tx|rx}_currdescnum
Driver "init" function might be called multiple times.
On every "init" Tx/Rx buffer descriptors are initialized: "descs_init"
-> "{tx|rx}_descs_init".

In its turn those init functions set MAC's "{tx|rx}desclistaddr" to
point on the first buffer descriptor in the list.

So CPU to start operation from the first buffer descriptor as well after
every "init" we have to reset "{tx|rx}_currdescnum".

Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Mischa Jonker <mjonker@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2014-02-07 09:16:26 -05:00
Alexey Brodkin
227ad7b2b6 net: designware: Respect "bus mode" register contents on SW reset
"bus mode" register contains lots of fields and some of them don't
expect to be written with 0 (zero). So since we're only interested in
resetting MAC (which is done with setting the least significant bit of
this register with "0") I believe it's better to modify only 1 bit of
the register.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Vipin Kumar <vipin.kumar@st.com>
Patch: 277864
2013-11-22 16:50:54 -06:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Vipin Kumar
7091915ad7 net/designware: Do not select MIIPORT for RGMII interface
Do not select MIIPORT for RGMII interface

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>
2013-06-24 19:10:16 -05:00
Dinh Nguyen
66f119e50c net/designware: Consecutive writes to the same register to be avoided
This commit is an add-on to f6c4191f. There are a few registers where
consecutive writes to the same location should be avoided or have a delay.

According to Synopsys, here is a list of the registers and bit(s) where
consecutive writes should be avoided or a delay is required:

DMA Registers:
Register 0        Bit 7
Register 6        All bits except for 24, 16-13, 2-1.

GMAC Registers:
Registers 0-3     All bits
Registers 6-7     All bits
Register 10       All bits
Register 11       All bits except for 5-6.
Registers 16-47   All bits
Register 48       All bits except for 18-16, 14.
Register 448      Bit 4.
Register 459      Bits 0-3.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Reviewed-by: Matthew Gerlach <mgerlach@altera.com>
Acked-by: Amit Virdi <amit.virdi@st.com>
2012-07-11 13:15:31 -05:00
Stefan Roese
ef76025a99 net: Multiple updates/enhancements to designware.c
This patch adds the following changes to designware ethernet driver
found on the ST SPEAr SoC:

- Don't init MAC & PHY upon startup. This causes a delay, waiting for
  the auto negotiation to complete. And we don't want this delay to
  always happen. Especially not on platforms where ethernet is not
  used at all (e.g. booting via flash).
  Instead postpone the MAC / PHY configuration to the stage, where
  ethernet is first used.
- Add possibility for board specific PHY init code. This is needed
  for example on the X600 board, where the Vitesse PHY needs to be
  configured for GMII mode.
  This board specific PHY init is done via the function
  designware_board_phy_init(). And this driver now adds a weak default
  which can be overridden by board code.
- Use common functions miiphy_speed() & miiphy_duplex() to read
  link status from PHY.
- Print status and progress of auto negotiation.
- Print link status (speed, dupex) upon first usage.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
2012-07-07 14:07:42 +02:00
Vipin Kumar
9afc1af01f SPEAr: Add interface information in initialization
Few Designware peripheral registers need to be modified based on the
ethernet interface selected by the board. This patch supports interface
information in ethernet driver

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2012-07-07 14:07:40 +02:00
Joe Hershberger
10cbe3b6a4 net: Fix remaining API interface breakage
These are all the files which use the API incorrectly but did not get
built using MAKEALL -a powerpc|arm.  I have no compiler for them, but
the remaining issues should be far less than without this patch.

Any outstanding issues are left to the maintainers of boards that use
these drivers.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2012-05-23 14:19:21 -05:00
Amit Virdi
cafabe1995 net/designware: Change timeout loop implementation
The new implementation changes the timeout loop implementation to avoid 1 ms
delay in each failing test. It also configures the delay to 10usec.

Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:53 -05:00
Armando Visconti
20a5dde149 net/designware: Set ANAR to 0x1e1
This patch forces the advertised capabilities during auto
negotiation to always be 10/100 Mbps and half/full as duplexing.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:40 -05:00
Vikas Manocha
e25c90b45c net/designware: Program phy registers when auto-negotiation is ON
If AN(auto-negotiation) is ON, speed bit of control register are not
applicable.  Also phy registers were not getting programmed as per the
result of AN. This patch sets only AN bit & restart AN bit for AN ON
selection & programs PHY registers as per AN result.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:34 -05:00
Vipin Kumar
13edd1706c net/designware: Try configuring phy on each dw_eth_init
Phy autonegotiation works only when the ethernet cable is plugged in.
Since the phy was configured only at the init time, a plugged in cable
was necessary to initialize the phy properly.

This patch keeps a flag to check if the phy initialization has
succeeded, and calls configure_phy routine at every init if this flag
reports otherwise.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:21 -05:00
Armando Visconti
aa51005c3f net/designware: Consecutive writes must have delay
This patch solves a TX/RX problem which happens at 10Mbps, due to the
fact that we are not respecting 4 cyles of the phy_clk (2.5MHz) between
two consecutive writes on the same register.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:47:09 -05:00
Vipin KUMAR
024333c96f net/designware: Phy address fix
The code assumes the phy address to be > 0, which is not true, the phy address
can be in the range 0-31.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:46:59 -05:00
Vipin KUMAR
c7f6dbe736 net/designware: Fix to restore hw mac address
The network controller mac resets hardware address stored in MAC_HI and MAC_LO
registers if mac is resetted. So, hw mac address needs to be restored in case
mac is explicitly resetted from driver.

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
2012-04-04 10:46:39 -05:00
Simon Glass
7616e78508 Add Ethernet hardware MAC address framework to usbnet
Built-in Ethernet adapters support setting the mac address by means of a
ethaddr environment variable for each interface (ethaddr, eth1addr, eth2addr).

This adds similar support to the USB network side, using the names
usbethaddr, usbeth1addr, etc. They are kept separate since we don't want
a USB device taking the MAC address of a built-in device or vice versa.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Eric Bénard <eric@eukrea.com>
2011-08-08 21:05:23 +02:00
Mike Frysinger
f0ece9e934 net: designware: fix uninitialized phy_addr usage
When CONFIG_DW_SEARCH_PHY is disabled, the local phy_addr variable
never gets initialized which causes random behavior at runtime and a
gcc warning.  So set it by default to the stored phy address.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>

Fix commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-07-25 22:20:10 +02:00
Mike Frysinger
ee7f5bfd12 net: designware: fix unused warning when CONFIG_DW_AUTONEG is enabled
The ctrl variable is only used when autoneg support is disabled, so only
declare it under those conditions to avoid an unused variable warning.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Reviewed-by: Vipin Kumar <vipin.kumar@st.com>
2011-07-25 22:19:40 +02:00
Mike Frysinger
8ef583a035 miiphy: convert to linux/mii.h
The include/miiphy.h header duplicates a lot of things from linux/mii.h.
So punt all the things that overlap to keep the API simple and to make
merging between U-Boot and Linux simpler.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-01-09 18:06:50 +01:00
Mike Frysinger
5700bb6352 miiphy: constify device name
The driver name does not need to be writable, so constify it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-08-09 11:52:29 -07:00
Vipin KUMAR
5b1b1883ff SPEAr : Network driver support added
Designware network driver support added.
This is a Synopsys ethernet controller

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2010-07-12 00:08:05 -07:00