mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
net/designware - switch driver to phylib usage
With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Mischa Jonker <mjonker@synopsys.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Amit Virdi <amit.virdi@st.com> Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin
Tom Rini
parent
27ee59af28
commit
92a190aaab
13 changed files with 183 additions and 385 deletions
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@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis)
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if (CONFIG_DW_PORTS & 1) {
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static const unsigned short pins[] = P_RMII0;
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if (!peripheral_request_list(pins, "emac0"))
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ret += designware_initialize(0, EMAC0_MACCFG, 1, 0);
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ret += designware_initialize(EMAC0_MACCFG, 0);
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}
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if (CONFIG_DW_PORTS & 2) {
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static const unsigned short pins[] = P_RMII1;
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if (!peripheral_request_list(pins, "emac1"))
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ret += designware_initialize(1, EMAC1_MACCFG, 1, 0);
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ret += designware_initialize(EMAC1_MACCFG, 0);
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}
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return ret;
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@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis)
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#if defined(CONFIG_DESIGNWARE_ETH)
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u32 interface = PHY_INTERFACE_MODE_MII;
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if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
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interface) >= 0)
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if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
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ret++;
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#endif
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return ret;
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@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis)
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#if defined(CONFIG_DESIGNWARE_ETH)
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u32 interface = PHY_INTERFACE_MODE_MII;
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if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
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interface) >= 0)
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if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
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ret++;
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#endif
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#if defined(CONFIG_MACB)
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@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis)
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#if defined(CONFIG_DESIGNWARE_ETH)
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u32 interface = PHY_INTERFACE_MODE_MII;
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if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
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interface) >= 0)
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if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
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ret++;
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#endif
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#if defined(CONFIG_MACB)
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@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis)
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#if defined(CONFIG_DW_AUTONEG)
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interface = PHY_INTERFACE_MODE_GMII;
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#endif
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if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY,
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interface) >= 0)
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if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0)
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ret++;
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#endif
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return ret;
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@ -67,31 +67,32 @@ void board_nand_init(void)
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fsmc_nand_init(nand);
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}
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int designware_board_phy_init(struct eth_device *dev, int phy_addr,
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int (*mii_write)(struct eth_device *, u8, u8, u16),
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int dw_reset_phy(struct eth_device *))
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int board_phy_config(struct phy_device *phydev)
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{
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/* Extended PHY control 1, select GMII */
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mii_write(dev, phy_addr, 23, 0x0020);
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phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020);
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/* Software reset necessary after GMII mode selction */
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dw_reset_phy(dev);
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phy_reset(phydev);
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/* Enable extended page register access */
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mii_write(dev, phy_addr, 31, 0x0001);
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001);
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/* 17e: Enhanced LED behavior, needs to be written twice */
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mii_write(dev, phy_addr, 17, 0x09ff);
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mii_write(dev, phy_addr, 17, 0x09ff);
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phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
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phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff);
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/* 16e: Enhanced LED method select */
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mii_write(dev, phy_addr, 16, 0xe0ea);
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phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea);
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/* Disable extended page register access */
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mii_write(dev, phy_addr, 31, 0x0000);
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phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
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/* Enable clock output pin */
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mii_write(dev, phy_addr, 18, 0x0049);
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phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
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if (designware_initialize(CONFIG_SPEAR_ETHBASE,
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PHY_INTERFACE_MODE_GMII) >= 0)
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ret++;
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@ -1,25 +0,0 @@
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This driver supports Designware Ethernet Controller provided by Synopsis.
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The driver is enabled by CONFIG_DESIGNWARE_ETH.
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The driver has been developed and tested on SPEAr platforms. By default, the
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MDIO interface works at 100/Full. #defining the below options in board
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configuration file changes this behavior.
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Call an subroutine from respective board/.../board.c
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designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
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The various options suported by the driver are
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1. CONFIG_DW_ALTDESCRIPTOR
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Define this to use the Alternate/Enhanced Descriptor configurations.
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1. CONFIG_DW_AUTONEG
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Define this to autonegotiate with the host before proceeding with mac
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level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
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and CONFIG_DW_DUPLEXHALF.
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2. CONFIG_DW_SPEED10M
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Define this to change the default behavior from 100Mbps to 10Mbps.
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3. CONFIG_DW_DUPLEXHALF
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Define this to change the default behavior from Full Duplex to Half.
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4. CONFIG_DW_SEARCH_PHY
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Define this to search the phy address. This would overwrite the value
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passed as 3rd arg from designware_initialize routine.
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@ -17,7 +17,75 @@
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#include <asm/io.h>
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#include "designware.h"
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static int configure_phy(struct eth_device *dev);
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#if !defined(CONFIG_PHYLIB)
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# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
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#endif
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static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct eth_mac_regs *mac_p = bus->priv;
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ulong start;
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u16 miiaddr;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
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((reg << MIIREGSHIFT) & MII_REGMSK);
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY))
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return readl(&mac_p->miidata);
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udelay(10);
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};
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return -1;
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}
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static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct eth_mac_regs *mac_p = bus->priv;
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ulong start;
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u16 miiaddr;
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int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
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writel(val, &mac_p->miidata);
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
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((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
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writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
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ret = 0;
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break;
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}
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udelay(10);
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};
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return ret;
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}
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static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate MDIO bus\n");
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return -1;
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}
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bus->read = dw_mdio_read;
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bus->write = dw_mdio_write;
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sprintf(bus->name, name);
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bus->priv = (void *)mac_regs_p;
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return mdio_register(bus);
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}
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static void tx_descs_init(struct eth_device *dev)
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{
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@ -83,38 +151,6 @@ static void rx_descs_init(struct eth_device *dev)
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priv->rx_currdescnum = 0;
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}
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static void descs_init(struct eth_device *dev)
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{
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tx_descs_init(dev);
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rx_descs_init(dev);
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}
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static int mac_reset(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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ulong start;
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int timeout = CONFIG_MACRESET_TIMEOUT;
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writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
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if (priv->interface != PHY_INTERFACE_MODE_RGMII)
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writel(MII_PORTSELECT, &mac_p->conf);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
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return 0;
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/* Try again after 10usec */
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udelay(10);
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};
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return -1;
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}
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static int dw_write_hwaddr(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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@ -122,8 +158,8 @@ static int dw_write_hwaddr(struct eth_device *dev)
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u32 macid_lo, macid_hi;
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u8 *mac_id = &dev->enetaddr[0];
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macid_lo = mac_id[0] + (mac_id[1] << 8) + \
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(mac_id[2] << 16) + (mac_id[3] << 24);
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macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
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(mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, &mac_p->macaddr0hi);
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@ -132,60 +168,86 @@ static int dw_write_hwaddr(struct eth_device *dev)
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return 0;
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}
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static void dw_adjust_link(struct eth_mac_regs *mac_p,
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struct phy_device *phydev)
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{
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u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return;
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}
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if (phydev->speed != 1000)
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conf |= MII_PORTSELECT;
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if (phydev->speed == 100)
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conf |= FES_100;
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if (phydev->duplex)
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conf |= FULLDPLXMODE;
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writel(conf, &mac_p->conf);
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printf("Speed: %d, %s duplex%s\n", phydev->speed,
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(phydev->duplex) ? "full" : "half",
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(phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
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}
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static void dw_eth_halt(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
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writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
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phy_shutdown(priv->phydev);
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}
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static int dw_eth_init(struct eth_device *dev, bd_t *bis)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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struct eth_dma_regs *dma_p = priv->dma_regs_p;
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u32 conf;
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unsigned int start;
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if (priv->phy_configured != 1)
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configure_phy(dev);
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writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
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/* Print link status only once */
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if (!priv->link_printed) {
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printf("ENET Speed is %d Mbps - %s duplex connection\n",
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priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
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priv->link_printed = 1;
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}
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start = get_timer(0);
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while (readl(&dma_p->busmode) & DMAMAC_SRST) {
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if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT)
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return -1;
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/* Reset ethernet hardware */
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if (mac_reset(dev) < 0)
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return -1;
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mdelay(100);
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};
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/* Resore the HW MAC address as it has been lost during MAC reset */
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/* Soft reset above clears HW address registers.
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* So we have to set it here once again */
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dw_write_hwaddr(dev);
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writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
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&dma_p->busmode);
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rx_descs_init(dev);
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tx_descs_init(dev);
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writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD |
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TXSECONDFRAME, &dma_p->opmode);
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writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
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conf = FRAMEBURSTENABLE | DISABLERXOWN;
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writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
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&dma_p->opmode);
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if (priv->speed != 1000)
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conf |= MII_PORTSELECT;
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writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
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if ((priv->interface != PHY_INTERFACE_MODE_MII) &&
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(priv->interface != PHY_INTERFACE_MODE_GMII)) {
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if (priv->speed == 100)
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conf |= FES_100;
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/* Start up the PHY */
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if (phy_startup(priv->phydev)) {
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printf("Could not initialize PHY %s\n",
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priv->phydev->dev->name);
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return -1;
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}
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if (priv->duplex == FULL)
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conf |= FULLDPLXMODE;
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dw_adjust_link(mac_p, priv->phydev);
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writel(conf, &mac_p->conf);
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descs_init(dev);
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/*
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* Start/Enable xfer at dma as well as mac level
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*/
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writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
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writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
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if (!priv->phydev->link)
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return -1;
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writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
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@ -267,251 +329,30 @@ static int dw_eth_recv(struct eth_device *dev)
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return length;
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}
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static void dw_eth_halt(struct eth_device *dev)
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static int dw_phy_init(struct eth_device *dev)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct phy_device *phydev;
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int mask = 0xffffffff;
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mac_reset(dev);
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priv->tx_currdescnum = priv->rx_currdescnum = 0;
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}
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static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
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{
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struct dw_eth_dev *priv = dev->priv;
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struct eth_mac_regs *mac_p = priv->mac_regs_p;
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ulong start;
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u32 miiaddr;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
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((reg << MIIREGSHIFT) & MII_REGMSK);
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|
||||
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
|
||||
|
||||
start = get_timer(0);
|
||||
while (get_timer(start) < timeout) {
|
||||
if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
|
||||
*val = readl(&mac_p->miidata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Try again after 10usec */
|
||||
udelay(10);
|
||||
};
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
|
||||
{
|
||||
struct dw_eth_dev *priv = dev->priv;
|
||||
struct eth_mac_regs *mac_p = priv->mac_regs_p;
|
||||
ulong start;
|
||||
u32 miiaddr;
|
||||
int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
|
||||
u16 value;
|
||||
|
||||
writel(val, &mac_p->miidata);
|
||||
miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
|
||||
((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
|
||||
|
||||
writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
|
||||
|
||||
start = get_timer(0);
|
||||
while (get_timer(start) < timeout) {
|
||||
if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Try again after 10usec */
|
||||
udelay(10);
|
||||
};
|
||||
|
||||
/* Needed as a fix for ST-Phy */
|
||||
eth_mdio_read(dev, addr, reg, &value);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DW_SEARCH_PHY)
|
||||
static int find_phy(struct eth_device *dev)
|
||||
{
|
||||
int phy_addr = 0;
|
||||
u16 ctrl, oldctrl;
|
||||
|
||||
do {
|
||||
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
|
||||
oldctrl = ctrl & BMCR_ANENABLE;
|
||||
|
||||
ctrl ^= BMCR_ANENABLE;
|
||||
eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
|
||||
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
|
||||
ctrl &= BMCR_ANENABLE;
|
||||
|
||||
if (ctrl == oldctrl) {
|
||||
phy_addr++;
|
||||
} else {
|
||||
ctrl ^= BMCR_ANENABLE;
|
||||
eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
|
||||
|
||||
return phy_addr;
|
||||
}
|
||||
} while (phy_addr < 32);
|
||||
|
||||
return -1;
|
||||
}
|
||||
#ifdef CONFIG_PHY_ADDR
|
||||
mask = 1 << CONFIG_PHY_ADDR;
|
||||
#endif
|
||||
|
||||
static int dw_reset_phy(struct eth_device *dev)
|
||||
{
|
||||
struct dw_eth_dev *priv = dev->priv;
|
||||
u16 ctrl;
|
||||
ulong start;
|
||||
int timeout = CONFIG_PHYRESET_TIMEOUT;
|
||||
u32 phy_addr = priv->address;
|
||||
|
||||
eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
|
||||
|
||||
start = get_timer(0);
|
||||
while (get_timer(start) < timeout) {
|
||||
eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
|
||||
if (!(ctrl & BMCR_RESET))
|
||||
break;
|
||||
|
||||
/* Try again after 10usec */
|
||||
udelay(10);
|
||||
};
|
||||
|
||||
if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT)
|
||||
phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
|
||||
if (!phydev)
|
||||
return -1;
|
||||
|
||||
#ifdef CONFIG_PHY_RESET_DELAY
|
||||
udelay(CONFIG_PHY_RESET_DELAY);
|
||||
#endif
|
||||
return 0;
|
||||
phydev->supported &= PHY_GBIT_FEATURES;
|
||||
phydev->advertising = phydev->supported;
|
||||
|
||||
priv->phydev = phydev;
|
||||
phy_config(phydev);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Add weak default function for board specific PHY configuration
|
||||
*/
|
||||
int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr,
|
||||
int (*mii_write)(struct eth_device *, u8, u8, u16),
|
||||
int dw_reset_phy(struct eth_device *))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int configure_phy(struct eth_device *dev)
|
||||
{
|
||||
struct dw_eth_dev *priv = dev->priv;
|
||||
int phy_addr;
|
||||
u16 bmcr;
|
||||
#if defined(CONFIG_DW_AUTONEG)
|
||||
u16 bmsr;
|
||||
u32 timeout;
|
||||
ulong start;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DW_SEARCH_PHY)
|
||||
phy_addr = find_phy(dev);
|
||||
if (phy_addr >= 0)
|
||||
priv->address = phy_addr;
|
||||
else
|
||||
return -1;
|
||||
#else
|
||||
phy_addr = priv->address;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Some boards need board specific PHY initialization. This is
|
||||
* after the main driver init code but before the auto negotiation
|
||||
* is run.
|
||||
*/
|
||||
if (designware_board_phy_init(dev, phy_addr,
|
||||
eth_mdio_write, dw_reset_phy) < 0)
|
||||
return -1;
|
||||
|
||||
if (dw_reset_phy(dev) < 0)
|
||||
return -1;
|
||||
|
||||
#if defined(CONFIG_DW_AUTONEG)
|
||||
/* Set Auto-Neg Advertisement capabilities to 10/100 half/full */
|
||||
eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1);
|
||||
|
||||
bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
|
||||
#else
|
||||
bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
|
||||
|
||||
#if defined(CONFIG_DW_SPEED10M)
|
||||
bmcr &= ~BMCR_SPEED100;
|
||||
#endif
|
||||
#if defined(CONFIG_DW_DUPLEXHALF)
|
||||
bmcr &= ~BMCR_FULLDPLX;
|
||||
#endif
|
||||
#endif
|
||||
if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
|
||||
return -1;
|
||||
|
||||
/* Read the phy status register and populate priv structure */
|
||||
#if defined(CONFIG_DW_AUTONEG)
|
||||
timeout = CONFIG_AUTONEG_TIMEOUT;
|
||||
start = get_timer(0);
|
||||
puts("Waiting for PHY auto negotiation to complete");
|
||||
while (get_timer(start) < timeout) {
|
||||
eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
|
||||
if (bmsr & BMSR_ANEGCOMPLETE) {
|
||||
priv->phy_configured = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Print dot all 1s to show progress */
|
||||
if ((get_timer(start) % 1000) == 0)
|
||||
putc('.');
|
||||
|
||||
/* Try again after 1msec */
|
||||
udelay(1000);
|
||||
};
|
||||
|
||||
if (!(bmsr & BMSR_ANEGCOMPLETE))
|
||||
puts(" TIMEOUT!\n");
|
||||
else
|
||||
puts(" done\n");
|
||||
#else
|
||||
priv->phy_configured = 1;
|
||||
#endif
|
||||
|
||||
priv->speed = miiphy_speed(dev->name, phy_addr);
|
||||
priv->duplex = miiphy_duplex(dev->name, phy_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MII)
|
||||
static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
|
||||
dev = eth_get_dev_by_name(devname);
|
||||
if (dev)
|
||||
eth_mdio_read(dev, addr, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
|
||||
dev = eth_get_dev_by_name(devname);
|
||||
if (dev)
|
||||
eth_mdio_write(dev, addr, reg, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
|
||||
int designware_initialize(ulong base_addr, u32 interface)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
struct dw_eth_dev *priv;
|
||||
|
|
@ -533,19 +374,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
|
|||
memset(dev, 0, sizeof(struct eth_device));
|
||||
memset(priv, 0, sizeof(struct dw_eth_dev));
|
||||
|
||||
sprintf(dev->name, "mii%d", id);
|
||||
sprintf(dev->name, "dwmac.%lx", base_addr);
|
||||
dev->iobase = (int)base_addr;
|
||||
dev->priv = priv;
|
||||
|
||||
eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]);
|
||||
|
||||
priv->dev = dev;
|
||||
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
|
||||
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
|
||||
DW_DMA_BASE_OFFSET);
|
||||
priv->address = phy_addr;
|
||||
priv->phy_configured = 0;
|
||||
priv->interface = interface;
|
||||
|
||||
dev->init = dw_eth_init;
|
||||
dev->send = dw_eth_send;
|
||||
|
|
@ -555,8 +391,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface)
|
|||
|
||||
eth_register(dev);
|
||||
|
||||
#if defined(CONFIG_MII)
|
||||
miiphy_register(dev->name, dw_mii_read, dw_mii_write);
|
||||
#endif
|
||||
return 1;
|
||||
priv->interface = interface;
|
||||
|
||||
dw_mdio_init(dev->name, priv->mac_regs_p);
|
||||
priv->bus = miiphy_get_dev_by_name(dev->name);
|
||||
|
||||
return dw_phy_init(dev);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@
|
|||
|
||||
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
|
||||
|
||||
struct eth_mac_regs {
|
||||
u32 conf; /* 0x00 */
|
||||
|
|
@ -217,14 +215,9 @@ struct dmamacdescr {
|
|||
#endif
|
||||
|
||||
struct dw_eth_dev {
|
||||
u32 address;
|
||||
u32 interface;
|
||||
u32 speed;
|
||||
u32 duplex;
|
||||
u32 tx_currdescnum;
|
||||
u32 rx_currdescnum;
|
||||
u32 phy_configured;
|
||||
u32 link_printed;
|
||||
|
||||
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
|
||||
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
|
||||
|
|
@ -236,15 +229,8 @@ struct dw_eth_dev {
|
|||
struct eth_dma_regs *dma_regs_p;
|
||||
|
||||
struct eth_device *dev;
|
||||
struct phy_device *phydev;
|
||||
struct mii_dev *bus;
|
||||
};
|
||||
|
||||
/* Speed specific definitions */
|
||||
#define SPEED_10M 1
|
||||
#define SPEED_100M 2
|
||||
#define SPEED_1000M 3
|
||||
|
||||
/* Duplex mode specific definitions */
|
||||
#define HALF_DUPLEX 1
|
||||
#define FULL_DUPLEX 2
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -72,12 +72,13 @@
|
|||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_HOSTNAME "bf609-ezkit"
|
||||
#define CONFIG_DESIGNWARE_ETH
|
||||
#define CONFIG_PHY_ADDR 1
|
||||
#define CONFIG_DW_PORTS 1
|
||||
#define CONFIG_DW_AUTONEG
|
||||
#define CONFIG_DW_ALTDESCRIPTOR
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_PHYLIB
|
||||
|
||||
/* i2c Settings */
|
||||
#define CONFIG_BFIN_TWI_I2C
|
||||
|
|
|
|||
|
|
@ -17,11 +17,9 @@
|
|||
/* Ethernet driver configuration */
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DESIGNWARE_ETH
|
||||
#define CONFIG_DW_SEARCH_PHY
|
||||
#define CONFIG_DW0_PHY 1
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
|
||||
#define CONFIG_DW_AUTONEG
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
|
||||
/* USBD driver configuration */
|
||||
|
|
|
|||
|
|
@ -37,6 +37,9 @@
|
|||
#define CONFIG_SYS_FSMC_NAND_8BIT
|
||||
#define CONFIG_SYS_NAND_BASE 0xD2000000
|
||||
|
||||
/* Ethernet PHY configuration */
|
||||
#define CONFIG_PHY_NATSEMI
|
||||
|
||||
/* Environment Settings */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr);
|
|||
int cs8900_initialize(u8 dev_num, int base_addr);
|
||||
int davinci_emac_initialize(void);
|
||||
int dc21x4x_initialize(bd_t *bis);
|
||||
int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface);
|
||||
int designware_initialize(ulong base_addr, u32 interface);
|
||||
int dm9000_initialize(bd_t *bis);
|
||||
int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
|
||||
int e1000_initialize(bd_t *bis);
|
||||
|
|
|
|||
Loading…
Reference in a new issue