Commit graph

27374 commits

Author SHA1 Message Date
Bin Meng
fe0c33a5ac x86: Clean up asm-offsets
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
c7016234f7 x86: Refactor u-boot.rom build rules
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Simon Glass
7dfb172d67 x86: ifdtool: Separate out filenames for -D and -i
To allow these options to be specified together, separate them out.

Change-Id: Ib93f11cd51eb3302127f4c82936ff2b44c88d5a2
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
673ed2f8c2 tools/ifdtool: Support writing multiple files (-w) simultaneously
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
64542f4616 x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:03 -07:00
Bin Meng
996467172e x86: ich-spi: Set the tx operation mode for ich 7
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
fa388bca3e x86: ich-spi: Set the rx operation mode for ich 7
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Jagannadha Sutradharudu Teki
54ba653ab6 sf: Enable byte program support
Enabled byte program support for sst flashes in sf.

Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 15:08:04 -07:00
Bin Meng
74c2cee4e8 spi: sf: Support byte program for sst spi flash
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Simon Glass
b648742a17 spi: Fix flag collision for SST_WP
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.

Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-13 15:08:04 -07:00
Jagannadha Sutradharudu Teki
6dd6e90e13 sf: Fix look for the fastest read command
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.

So this fix on sf will correctly handle the slow read supported
controllers.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2014-12-13 15:08:04 -07:00
Simon Glass
f46f3f356f bios_emulator: Correct ordering of includes
We should include common.h before other includes. This actually causes
a build error on chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Axel Lin
0a54745fc2 gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()
Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Bin Meng
15c7c6b31a x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Tom Rini
a5a5882611 Merge git://git.denx.de/u-boot-dm 2014-12-11 20:47:34 -05:00
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Tom Rini
2c49323d5d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-12-11 18:28:09 -05:00
Xiubo Li
d0419f400a ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7i
Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ.
It should be CONFIG_TIMER_CLK_FREQ.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
[York Sun: This is the difference between two patch versions]
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 12:37:42 -08:00
Simon Glass
b0e6ef4640 dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:44 -07:00
Allen Martin
a6c7b46181 ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.

This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.

The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
2014-12-11 13:18:44 -07:00
Simon Glass
754204b5c2 tegra: dts: Sync tegra124.dtsi with linux kernel
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
2014-12-11 13:18:44 -07:00
Simon Glass
6ee350bb93 dts: Bring in Chrome OS keyboard device tree definition
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:43 -07:00
Simon Glass
964d153c0e dm: device: Add newline to debug() messages
Some of these are missing a newline. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:43 -07:00
Simon Glass
ecc2ed55ee dm: i2c: Add tests for I2C
Add some basic tests to check that the system works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
2014-12-11 13:18:43 -07:00
Simon Glass
20142019a9 dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:43 -07:00
Simon Glass
776f96f513 dm: i2c: dts: Add an I2C bus for sandbox
Add an I2C bus to the device tree, with an EEPROM emulator attached to one
of the addresses.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:43 -07:00
Simon Glass
ac395f088f dm: i2c: config: Enable I2C for sandbox using driver model
Enable the options to bring up I2C on sandbox. Also enable all the available
I2C commands for testing purposes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
2014-12-11 13:18:43 -07:00
Simon Glass
6ec1b75358 dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
d19de0d314 dm: i2c: Add a sandbox I2C driver
This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
c70c71d833 dm: i2c: Add I2C emulation driver for sandbox
In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
63656b762e dm: i2c: Implement driver model support in the i2c command
The concept of a 'current bus' is now implemented in the command line
rather than in the uclass. Also the address length does not need to
be specified with each command - really we should consider dropping
this from most commands but it works OK for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
c6202d857e dm: i2c: Add a uclass for I2C
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:

- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions

Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:42 -07:00
Przemyslaw Marczak
59345b1f0f lib: errno: introduce errno_str(): returns errno related message
The functions error's numbers are standarized - but the error
messages are not.

The errors are often handled with unclear error messages,
so why not use an errno standarized messages.

Advantages:
- This could decrease the binary size.
- Appended with a detailed information,
  the error message will be clear.

This commit introduces new function:
- const char *errno_to_str(int errno)

The functions returns a pointer to the errno corresponding text message:
- if errno is null or positive number - a pointer to "Success" message
- if errno is negative - a pointer to errno related message

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-11 13:18:41 -07:00
Simon Glass
115066666c dm: rpi: Move serial to driver model
Adjust the configuration to use the driver model version of the pl01x
serial driver. Add the required platform data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-11 13:18:41 -07:00
Simon Glass
59c73d7555 dm: serial_pl01x: Add missing private data size
The private data size is missing from the driver, so we store it at 0,
which causes problems when something overwrites memory at 0.

Fix this.

Change-Id: I6f551ee905b0064ae8343e41e46450c37c8c8c1a
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-11 13:18:41 -07:00
Masahiro Yamada
a56642c7ba dm_test: improve the appearance shown by "dm tree" command
The command "dm tree" lists devices in a tree-like format.
This commit makes it look more like what the Unix command "tree"
shows.

=> dm tree
 Class       Probed   Name
----------------------------------------
 root        [ + ]    root_driver
 demo        [   ]    |-- demo_shape_drv
 demo        [   ]    |-- demo_simple_drv
 demo        [   ]    |-- demo_shape_drv
 demo        [   ]    |-- demo_simple_drv
 demo        [   ]    |-- demo_shape_drv
 test        [   ]    |-- test_drv
 test        [   ]    |-- test_drv
 test        [   ]    |-- test_drv
 gpio        [   ]    |-- gpio_sandbox
 serial      [   ]    |-- serial_sandbox
 serial      [ + ]    |-- serial
 demo        [   ]    |-- triangle
 demo        [   ]    |-- square
 demo        [   ]    |-- hexagon
 gpio        [   ]    |-- gpios
 spi         [   ]    |-- spi@0
 spi_emul    [   ]    |   `-- flash@0
 cros_ec     [ + ]    `-- cros-ec@0

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:41 -07:00
Masahiro Yamada
80d9ef8d40 lib: string: move strlcpy() to a common place
Move strlcpy() definition from drivers/usb/gadget/ether.c to
lib/string.c because it is a very useful function.
Let's add the prototype to include/linux/string.h too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:41 -07:00
Alison Wang
0de15707a7 kconfig: ls102xa: Change the prompt messages
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message "Support ls1021aqds_nor" in
Kconfig is not clear. This patch changes it to
"Support ls1021aqds".

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:41 -08:00
Jaiprakash Singh
1d421cc677 driver/mtd: Fix IFC compilation warnings
'eccstat' array elements might be used uninitialized

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:32 -08:00
Xiubo Li
660673af4f ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:22 -08:00
Xiubo Li
e87f3b308c ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:12 -08:00
Xiubo Li
1a2826f6e0 ls102xa: changing a few targets' configurations.
Enable hypervisors utilizing the ARMv7 virtualization extension
on the LS1021A-QDS/TWR boards with the A7 core tile, we add the
required configuration variable.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:03 -08:00
Xiubo Li
290e6e921f ls1021a: adding a secondary core boot address and kick functions
Define the board specific smp_set_cpu_boot_addr() function to set
the start address for secondary cores in the LS1021A specific manner.

Define the board specific smp_kick_all_cpus() functioin to boot a
secondary core. Here the BRR contains control bits for enabling boot
for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field
optionally allows for logical core 0 to be released for booting or to
remain in boot holdoff. All other cores remain in boot holdoff until
their corresponding bit is set.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:53 -08:00
Xiubo Li
73a1cb27c0 ARM: HYP/non-sec: Fix the ARCH Timer frequency setting.
For some SoCs, the system clock frequency may not equal to the
ARCH Timer's frequency.

This patch uses the CONFIG_TIMER_CLK_FREQ instead of
CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer
macor could be set separately and without interfering each other.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:45 -08:00
Xiubo Li
b8e5c7f94a ARM: HYP/non-sec: add the pen address BE mode support.
For some SoCs, the pen address register maybe in BE mode and the
CPUs are in LE mode.

This patch adds BE mode support for smp pen address.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:30 -08:00
Tang Yuantian
a7787b7850 fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:18 -08:00
Nikhil Badola
da5ce448c7 drivers: usb: fsl: Check USB Erratum A007792 applicability
Check USB Erratum A007792 applicability. If applicable, add
corresponding  property in the device tree via device tree fixup

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:11 -08:00
Nikhil Badola
ecfc19f31f drivers: usb: fsl: Add USB device-tree errata framework
Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:03 -08:00
Nikhil Badola
a1c04e2785 drivers: usb: Make usb device-tree fixup code architecture independent
move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:50 -08:00
Yao Yuan
bca11bd7c3 ls1021aqds: add hwconfig setting to do pin mux
The Freescale LS1021AQDS share some pins, so Add the hwconfig option
that allows the user to choose which the function he wants.

The main pin mux IP is:
eSDHC, SAI, IIC2, RGMII, CAN, SAI.

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:32 -08:00