Commit graph

55546 commits

Author SHA1 Message Date
Andy Shevchenko
edf18a83f8 x86: acpi: Not every platform has serial console a first device
We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.

For example, on properly described Intel Edison board the console UART
is a third one.

Use current serial device as described in global data.

Fixes: a61cbad78e ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
c652dd1557 x86: acpi: Add DMA descriptors for I2C1 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Note, I2C6, which is available to user, has no DMA request lines connected.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Andy Shevchenko
1d2825aa30 x86: acpi: Add DMA descriptors for SPI5 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.

Provide DMA descriptors to utilize this capability in the future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-03-10 08:17:00 +08:00
Tom Rini
e8e3f2d2d4 Merge branch '2019-03-08-master-imports'
- Assorted minor fixes:
  - ARM: qemu-arm: enable USB boot in distro boot with UEFI
  - image: fdt: handle coalesced reserve region
  - cmd: thordown: Fix spelling of download.
  - fdt: Fix FIT header verification in mkimage and conduct same checks
    as bootm
  - test: Update test-imagetools.sh to match new syntax
2019-03-08 18:04:13 -05:00
AKASHI Takahiro
279dc04f25 ARM: qemu-arm: enable USB boot in distro boot with UEFI
With this patch which adds a removable USB mass storage to a list
of bootable devices, USB boot is supported in distro boot if UEFI is
configured.

Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
2019-03-08 18:03:58 -05:00
Patrick Delaunay
e1d7ed3401 image: fdt: handle coalesced reserve region
Handle in boot_fdt_reserve_region
any return value > 0 of lmb_reserve() function;
it occurs when coalesced region are found:
adjacent reserved region are merged.

This patch avoid the error trace:
  ERROR: reserving fdt memory region failed..
when reserved region are merged (return value = 1).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-08 11:31:44 -05:00
Vagrant Cascadian
c8087f67f1 cmd: thordown: Fix spelling of download.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-03-08 11:31:44 -05:00
Jordan Hand
d32aa3cae4 fdt: Fix FIT header verification in mkimage and conduct same checks as bootm
FIT header verification in mkimage was treating a return code as a boolean,
which meant that failures in validating the fit were seen as successes.

Additionally, mkimage was checking all formats to find a header which
passes validation, rather than using the image type specified to
mkimage.

checkpatch.pl checks for lines ending with '(' and alignment matching
open parentheses are ignored to keep with existing coding style.

Signed-off-by: Jordan Hand <jorhand@microsoft.com>
2019-03-08 11:31:44 -05:00
Martyn Welch
280fafff16 test: Update test-imagetools.sh to match new syntax
The syntax of dumpimage was simplified in commit 12b831879a ("tools:
dumpimage: Simplify arguments"), but the test
(test/image/test-imagetools.sh) was not updated and is now failing.

Update the test to use the new syntax.

Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
2019-03-08 11:31:44 -05:00
Tom Rini
606b239a6c Merge branch 'master' of git://git.denx.de/u-boot-i2c
This pull request contains bugfixes for rcar_i2c, rcar_ii2c and
i2c_cdns driver.

Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek
is a bugfix for arm64 builds, as discussed with Marek on list.
2019-03-08 07:26:29 -05:00
Ismael Luceno Cortes
c64eb297e7 i2c: rcar_i2c: Move FSDA check to rcar_i2c_recover
Cosmetic change.  Any call to the recover function would need to do the
same check afterwards, so it's sensible to make it part of the function.

Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
2019-03-08 05:53:40 +01:00
Ismael Luceno Cortes
7c8f821e5d i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer
It needs to be done for both reads and writes, so do it at rcar_i2c_xfer
to avoid duplication.

Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08 05:53:33 +01:00
Ismael Luceno Cortes
ff4035be9b i2c: rcar_i2c: Don't mask errors with EREMOTEIO at rcar_i2c_xfer
Fix rcar_i2c_xfer return value, previously it was always returning
-EREMOTEIO when dealing with errors from calls to the read/write
functions.

Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08 05:53:23 +01:00
Ismael Luceno Cortes
3ad31eb1cc i2c: rcar_i2c: Fix sending of slave addresses
Do the reset before clearing the MSR, otherwise it may result in a read
or write operation instead if the start condition is repeated.

Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08 05:53:17 +01:00
Ismael Luceno Cortes
3b59eaef4f i2c: rcar_i2c: Add comments about registers & values
Document the meaning of macros related to registers and values to be
written to them.

Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08 05:53:11 +01:00
Ismael Luceno Cortes
4fcff08c4b i2c: rcar_i2c: Setup SCL/SDA delay at rcar_i2c_set_speed
Setting up the delay only needs to be done once; move it to
rcar_i2c_set_speed so it's done at initialization time.

Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08 05:53:03 +01:00
Siva Durga Prasad Paladugu
bc00512438 i2c: i2c_cdns: Add support for handling arbitration lost
This patch adds support for handling arbitration lost
in case of multi master mode. When an arbitration lost
is detected, it retries for 10 times before failing.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08 05:52:38 +01:00
Siva Durga Prasad Paladugu
006265d063 i2c: i2c_cdns: Fix clearing of all interrupts
The arbitration lost interrupt was not getting cleared
while clearing interrupts. This patch fixes this by adding
arbitration lost interrupt as well during clear. This patch
also removes hardcoded value and defined a macro for it.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-08 05:52:30 +01:00
Marek Vasut
da53b0543d i2c: rcar_i2c: Add Gen3 SoC support
Add support for R-Car Gen3 SoCs into the driver, which encompases
the Gen3 SoC extra timing register handling and 64bit build fixes.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-07 09:41:43 +01:00
Marek Vasut
eb54682e91 i2c: rcar_iic: Read ICSR only once
Read ICSR only once to avoid missing interrupts. This happens on R8A7791
Porter during reset, when reading the PMIC register 0x13, which may fail
sometimes because of the missed DTE interrupt.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-07 06:20:09 +01:00
Tom Rini
f18b7b2798 Merge branch 'master' of git://git.denx.de/u-boot-spi
- dw spi include file fix
- Allwinner A31 spi, been in ML in many releases.
2019-03-06 20:25:09 -05:00
Tom Rini
ca1e50063a Pull request for the UEFI subsystem for v2019.04-rc4
This pull request contains only bug fixes.
 
 The most notable bug fixed was writing to random memory addresses when
 trying to add a HII package of a yet unsupported package type.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAlx+IBUACgkQxIHbvCwF
 GsRj7A//ePmUU3cPrmtgFj7VMvDfRWsIfgwgrtW0uynjmDRYx9msNXUz0YQBEmmU
 iXe61B6V8dfZhuj65vTRGwUUkZJfikDHf/uFCczhbSj1KdY1qV8eMI6ZgNPYYvkk
 UlPL4BF/rnOSV5rqL1eXN/MC8Ka4FZwHseKuJupSj0WK9oyQqD0zEL6coJT5tpCh
 ZydsBT4UhbFxN5vAP2V40zFRUKwH+n6oQ/dohJgTdppnEpZuUTmmymzmxh323+nj
 gYqMQB2TArfLcEZL6+VR/sRqSUTewPdVxkdgEN02Gtl7Kuew1irxc85yEJEEJjc8
 u2MXlmf0nTAole1R7ZHY6MnwGUeYtiUKcKtp4BKnFssL8Pg2bPCIqjd/US0OZKwZ
 aZhUqFvXx89Sk2PXW9VO1WCNqkIEtnOS4Ze3V6wFxUlcaup2Re9iKMcyWnhbhmV8
 mkWuDJFjSt90q+lzEK64gN2ROHZfWz7tXZOaxtGe1fDdvuw+ijOxNaPfOZYRDPW/
 BOTmFyS3o+UrOdNQo7JAuoXNhVIz1N1rSxW2ZWgPOVgH015l9OEj7WLR1WmyC4oV
 mc5YquouT8jDoy9SiINP+t+ZVDtpa8RfBQ9Bxq2eew/v1BjOjRKDJep74moZtxrA
 WJ1pWiH3O0XFXhkZXBdl3P5WXmUukaIkduU7lxw3JS7gh+U0ZLw=
 =HuZ2
 -----END PGP SIGNATURE-----

Merge tag 'efi-2019-04-rc4' of https://github.com/xypron2/u-boot

Pull request for the UEFI subsystem for v2019.04-rc4

This pull request contains only bug fixes.

The most notable bug fixed was writing to random memory addresses when
trying to add a HII package of a yet unsupported package type.
2019-03-05 08:51:48 -05:00
Tom Rini
f08023c07d Prepare v2019.04-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-03-04 21:46:24 -05:00
Tom Rini
e102f74d65 Merge branch 'master' of git://git.denx.de/u-boot-sh
- Assorted PFC fixes
2019-03-04 16:35:40 -05:00
Tom Rini
c507d30694 First set of u-boot-atmel fixes for 2019.04 cycle
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJcfNQTAAoJEB6zHgIOrC/Iv6EH/3GGs0wbTSoXPyqpFkiFCH0p
 niOGHK0KjS0/U9hhlAzPyD9pgm9nXhwEXxrwPTznOAFIPNI3gARdO2ofwAOL7hFR
 ORsB3rWpoX/r2XOunHz7bExpTlXQnXZue0SFrWl4aatWTATb8zcbpp2l+8ljSXs+
 /MFhyyqTogLq92t+4+ekwsTZkHvcDxeHGbnlBiQH0bcUw1vYs6AoYjAvC7duu/Y/
 5ZL4lozJnMGCiFA5XZmqDkTwCSExt/Un8pEORUlwf7Rngwx37jdCeOgmKDR/WjOx
 EFQxKTXotzYqJtQzCCT0NidI/2QG3PJHw2yx9Q7IsGFk97JYMq+gT4CyJj5Wgks=
 =BIAO
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-atmel-2019.04-a' of git://git.denx.de/u-boot-atmel

First set of u-boot-atmel fixes for 2019.04 cycle
2019-03-04 13:06:22 -05:00
Tom Rini
85887300ae Merge git://git.denx.de/u-boot-fsl-qoriq
- Enable DHCP as boot-source in distro boot for NXP layerscape
  platforms
- fix register layout for SEC on Layerscape architectures
- fixes related to DPAA2 ethernet
2019-03-04 13:05:53 -05:00
Jagan Teki
a51cd54eff spi: Rename sun4i_spi.c into spi-sunxi.c
Now the same SPI controller driver is reusable in all Allwinner
SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c
which eventually look like a common sunxi driver.

Also update the function, variable, structure names in driver from
sun4i into sunxi.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04 18:08:56 +05:30
Jagan Teki
903e7cf37c spi: sun4i: Driver cleanup
- drop unused macros.
- use base instead of base_addr, for better code readability
- move .probe and .ofdata_to_platdata functions in required
  places to add platdata support in future.
- use sentinel sun4i_spi_ids.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04 18:08:56 +05:30
Jagan Teki
853f4511e9 spi: sun4: Add A31 spi controller support
The usual SPI transmission protocol in Allwinner A10 and A31
controllers share similar context with minimal changes in register
offsets along with few additional register bits on A31.

So, add A31 spi controller support in existing sun4i_spi with A31
specific register offsets and bits.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04 18:08:56 +05:30
Jagan Teki
8d71a19edd spi: sun4i: Add CLK support
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.

Clock disablement could be done while releasing the bus transfer, but
the existing code doesn't disable the clocks it only taken care of clock
enablement globally in probe.

So to make a proper clock handling, the clocks should enable it in claim
and disable it in release.

This patch would also do that change, by enable and disable clock in
proper order.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04 18:08:56 +05:30
Jagan Teki
178fbd243d spi: sun4i: Support fifo_depth via drvdata
Support fifo_depth via drvdata instead of macro definition, this would
eventually reduce another macro definition for new SPI controller fifo
depth support addition.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04 18:08:56 +05:30
Jagan Teki
8d9bf46847 spi: sun4i: Access registers and bits via enum offsets
Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave remains nearly similar.

Add enum offsets for register set and register bits, so-that
it can access both classes of SPI controllers.

Assign same control register for global, transfer and fifo control
registers to make the same code compatible with A31 SPI controller.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204
2019-03-04 18:08:56 +05:30
Jagan Teki
8cbf09ba1c spi: sun4i: Simplify reg writes using set/clrbits_le32
Update the existing register writes using setbits_le32 and
clrbits_le32 in required places.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-03-04 18:08:56 +05:30
Jagan Teki
82111469a5 clk: sunxi: Implement SPI clocks, resets
- Implement SPI AHB, MOD clocks via ccu_clk_gate for all
  supported Allwinner SoCs
- Implement SPI resets via ccu_reset for all supported
  Allwinner SoCs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04 18:08:56 +05:30
Jagan Teki
6cb6aa602b spi: sun4i: Poll for rxfifo to be filled up
To drain rx fifo the fifo need to poll for how much data has
been filled up in rx fifo.

To achieve this, the current code is using wait_for_bit logic
on control register with exchange burst mode mask, which is not
a proper way of waiting for fifo filled up.

So, add code for polling rxfifo to be filled up using fifo
status register.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-03-04 18:08:56 +05:30
Horatiu.Vultur@microchip.com
1b77de4476 spi: designware: Change include order
With current order of include files, the file designware_spi.c
can't see that the struct global_data has the member
board_type when CONFIG_BOARD_TYPES is defined. By not seeing this
then all the members are shifted in the struct global_data.
So when the driver is trying to read from device tree blob, it
would pass the wrong address to the function 'fdtdev_get_int'.
This will make to use the default frequency 500000.

The fix consists of changing the order of include files in
designware_spi.c to include first common.h file.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-03-04 17:56:26 +05:30
Eugen Hristev
57f76c2a47 configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from non-nand configs
SPL_GENERATE_ATMEL_PMECC_HEADER will generate a header for the SPL for NAND
information. The initial stage 1 bootloader will use this header in case the
NAND flash doesn't support commands to retrieve sector size, etc.
However this header is bad for different boot media, like MMC or SPI.
In case SD_BOOT or SPI_BOOT is used, remove the config for this.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2019-03-04 09:13:04 +02:00
Alexander Dahl
0ecab03d65 configs: sama5d27_som1_ek: Activate misc init for uSD variant
This was already set for 'sama5d27_som1_ek_mmc_defconfig' (first SD
card, full size). Without this option set, the MAC address is not read
from the I²C EEPROM at boot, and remains unset:

    U-Boot 2019.01 (Jan 01 2019 - 00:00:00 +0000)

    CPU: SAMA5D27 1G bits DDR2 SDRAM
    Crystal frequency:       24 MHz
    CPU clock        :      492 MHz
    Master clock     :      164 MHz
    DRAM:  128 MiB
    MMC:   sdio-host@a0000000: 0, sdio-host@b0000000: 1
    Loading Environment from FAT... OK
    In:    serial
    Out:   serial
    Err:   serial
    Net:
    Error: ethernet@f8008000 address not set.
    eth-1: ethernet@f8008000
    Hit any key to stop autoboot:  0

Signed-off-by: Alexander Dahl <ada@thorsis.com>
2019-03-04 09:13:04 +02:00
Hiroyuki Yokoyama
65eef78cdb pinctrl: renesas: r8a77990: Reivse USB ID pin name
Since the datasheet Rev.1.00 has an error about the USB ID pin name,
this patch revises it.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
bf93f24c30 pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit3 when using TX0
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50,
the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected,
and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
4892e8301b pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
According to the R-Car Gen3 Hardware Manual Rev.1.50, the MOD_SEL0
bit16 is set to 0 when NFALE_A and NFRB_N_A pin functions are
selected.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
ef083ecf90 pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit2 when using RX2,TX2 and SCK2
According to the R-Car Gen3 Hardware Manual Rev 1.50, the MOD_SEL0
bit2 is set when RX2_{A,B}, TX2_{A,B} and SCK2_A pin functions are
selected.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
8b5e96d80a pinctrl: renesas: r8a77990: Fix rename RTSx_N_TANS_x to RTSx_N_x
This patch fixes the allocation name "RTSx_N_TANS_x" of IPSR /
 MOD_SEL0/1 of r8a77990 to "RTSx_N_x". This information was
confirmed in the R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
0b9af5883b pinctrl: renesas: Fix r8a779{6,65} rename sel_ndfc to sel_ndf
This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22]
of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
6eff90c3a5 pinctrl: renesas: Remove r8a779{5,6,65} CC5_OSCOUT of IP17
This patch removes CC5_OSCOUT assignment of IP17[3:0] of r8a7795
 / r8a7796 / r8a77965. This information was confirmed in the R-Car
Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
6098f41e23 pinctrl: renesas: Fix r8a779{5,6,65} rename sel_adg_ to sel_adg
This patch fixes to the correct names, and "_" is not include after
"adg" for r8a7795/r8a7796/r8a77965. This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Hiroyuki Yokoyama
9e4b529c5f pinctrl: renesas: Fix r8a779{5,6,65} assign to GP7_03/02 of GPSR7
This patch is change the bit assignment of "HDMI1_CEC" to "GP7_03",
and "HDMI0_CEC" to "GP7_02". This information was confirmed in the
R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-04 01:46:05 +01:00
Yunfeng Ding
d2c49aad51 board: Enable DHCP distro boot for LS1012a, LS1021a
Enable DHCP distro boot for Layerscape LS1012A and LS1021A.

Signed-off-by: Yunfeng Ding <yunfeng.ding@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:19 +05:30
Laurentiu Tudor
7122f79141 armv8: fsl-layerscape: avoid DT fixup warning
sec_firmware reserves JR3 for it's own usage and deletes the JR3 node
from the device tree. This causes this warning to be issued when doing
the device tree fixup:

WARNING could not find node fsl,sec-v4.0-job-ring: FDT_ERR_NOTFOUND.

Fix it by excluding the device tree fixup for the JR reserved by
sec_firmware.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:14 +05:30
Laurentiu Tudor
e82d9ee73a armv8: fsl-layerscape: fix SEC QI ICID setup
The SEC QI ICID setup in the QIIC_LS register is actually an offset
that is being added to the ICID coming from the qman portal. Setting
it with a non-zero value breaks SMMU setup as the resulting ICID is
not known. On top of that, the SEC QI ICID must match the qman portal
ICIDs in order to share the isolation context.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-03 22:01:09 +05:30