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pinctrl: renesas: Fix r8a779{6,65} rename sel_ndfc to sel_ndf

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This patch fixes the allocation name "sel_ndfc" of MOD_SEL2[22]
of r8a7796 / r8a77965 to "sel_ndf". This information was confirmed
in the R-Car Gen3 Hardware Manual Rev.1.50.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Hiroyuki Yokoyama 2019-02-13 10:22:26 +09:00 committed by Marek Vasut
parent 6eff90c3a5
commit 0b9af5883b
1 changed files with 11 additions and 11 deletions
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22
drivers/pinctrl/renesas/pfc-r8a7796.c
View file

@ -502,7 +502,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
@ -1016,35 +1016,35 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
@ -1110,20 +1110,20 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
@ -1267,7 +1267,7 @@ static const u16 pinmux_data[] = {
/* IPSR14 */
PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),