Commit graph

24814 commits

Author SHA1 Message Date
Chris Morgan
59c255ae5f board: rockchip: Correct i2c2 pinctrl for RGxx3
The pinctrl on the Anbernic RGxx3 for the i2c2 bus does not use the
default value, so explicitly define it.

Fixes: 6cf6fe2537 ("board: rockchip: add Anbernic RGXX3 Series Devices")
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28 18:45:02 +08:00
Eugen Hristev
32961c09af ARM: dts: rockchip: rk3588-rock-5b-u-boot: add USB3 support
Enable the USB3.0 host node, and gadget node.
The gadget is available through the USB type C connector on the board.
The connector is tied to a Fairchild fusb302b device, which currently
does not have a driver in U-boot, but the node is here for correct
description of the board + Linux future compatibility.
It will be easier to move the node as-is when it will be available
in the DT from Linux

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28 18:45:02 +08:00
Joseph Chen
b8bae824cc ARM: dts: rockchip: rk3588: add support for USB 3.0 devices
Add support for the USB 3.0 devices in rk3588:
- USB DRD(dual role device) 3.0 #0 as usbdrd3_0 which is available in
rk3588s
- USB DRD(dual role device) 3.0 #1 as usbdrd3_1 which is available in
rk3588 only
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #0 phy interface
as usbdp_phy0
- USB DP PHY (combo USB3.0 and DisplayPort Alt Mode ) #1 phy interface
as usbdp_phy1
- USB 2.0 phy #2 , the USB 3.0 device can work with this phy in USB 2.0
mode
- associated GRFs (general register files) for the devices.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
[eugen.hristev@collabora.com: move nodes to right place, adapt from latest
linux kernel]
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28 18:45:02 +08:00
Eugen Hristev
22a5a9724b ARM: dts: rockchip: rk3588: sync with Linux
Sync the devicetree with linux-next tag: next-20230525

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-07-28 18:45:02 +08:00
Angelo Dureghello
67d39af665 m68k: dts: add watchdog node
Add watchdog node for the implemented mcf_wdt driver.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
---
Changes for v2:
- remove unnecessary big-endian property
Changes for v3:
- none
2023-07-25 23:21:42 +02:00
Angelo Dureghello
dc3a89b8c6 m68k: move watchdog functions in mcf_wdt driver
Move watchdog functions inside a separate watchdog driver.

Signed-off-by: Angelo Dureghello <angelo@kernel-space.org>
---
Changes for v2:
- none
Changes for v3:
- none
2023-07-25 23:21:42 +02:00
Tom Rini
1f2e4027fa arm: Remove more remnants of bcmcygnus
Remove some leftover files from the bcmcygnus platform.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-25 12:44:47 -04:00
Heinrich Schuchardt
8faeb1d722 part: eliminate part_get_info_by_name_type()
Since commit 56670d6fb8 ("disk: part: use common api to lookup part
driver") part_get_info_by_name_type() ignores the part_type parameter
used to restrict the partition table type.

omap_mmc_get_part_size() and part_get_info_by_name() are the only
consumers.

omap_mmc_get_part_size() calls with part_type = PART_TYPE_EFI because at
the time of implementation a speed up could be gained by passing the
partition table type. After 5 years experience without this restriction
it looks safe to keep it that way.

part_get_info_by_name() uses PART_TYPE_ALL.

Move the logic of part_get_info_by_name_type() to part_get_info_by_name()
and replace the function in omap_mmc_get_part_size().

Fixes: 56670d6fb8 ("disk: part: use common api to lookup part driver")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-25 12:44:46 -04:00
Tom Rini
94e7cb181a Revert "Merge branch '2023-07-24-introduce-FF-A-suppport'"
This reverts commit d927d1a808, reversing
changes made to c07ad9520c.

These changes do not pass CI currently.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-24 19:51:05 -04:00
Abdellatif El Khlifi
32dd07ff46 arm_ffa: introduce sandbox FF-A support
Emulate Secure World's FF-A ABIs and allow testing U-Boot FF-A support

Features of the sandbox FF-A support:

- Introduce an FF-A emulator
- Introduce an FF-A device driver for FF-A comms with emulated Secure World
- Provides test methods allowing to read the status of the inspected ABIs

The sandbox FF-A emulator supports only 64-bit direct messaging.

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Jens Wiklander <jens.wiklander@linaro.org>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
2023-07-24 15:30:03 -04:00
Abdellatif El Khlifi
096d471a76 arm64: smccc: add support for SMCCCv1.2 x0-x17 registers
add support for x0-x17 registers used by the SMC calls

In SMCCC v1.2 [1] arguments are passed in registers x1-x17.
Results are returned in x0-x17.

This work is inspired from the following kernel commit:

arm64: smccc: Add support for SMCCCv1.2 extended input/output registers

[1]: https://documentation-service.arm.com/static/5f8edaeff86e16515cdbe4c6?token=

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2023-07-24 15:30:02 -04:00
Tom Rini
45622f3262 Merge branch '2023-07-22-TI-K3-improvements'
- Actually merge the assorted K3 platform improvements that were
  supposed to be in commit 247aa5a191 ("Merge branch
  '2023-07-21-assorted-TI-platform-updates'")
2023-07-24 13:55:59 -04:00
Tom Rini
590a6cff97 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Set up per-hart stack before any function call
- Sync visionfive2 board DTS with Linux
- Define cache line size for USB 3.0 driver for RISC-V CPU
2023-07-24 10:58:07 -04:00
Heinrich Schuchardt
6aabe229f8 riscv: define a cache line size for the generic CPU
The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
2023-07-24 13:22:24 +08:00
Xingyu Wu
6c4b50e6de riscv: dts: jh7110: Add clock source from PLL
Change the PLL clock source from syscrg to sys_syscon child node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24 13:21:06 +08:00
Xingyu Wu
005f9627d0 riscv: dts: jh7110: Add PLL clock controller node
Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24 13:21:01 +08:00
Bo Gan
28ff3f16c4 riscv: setup per-hart stack earlier
Harts need to use per-hart stack before any function call, even if that
function is a simple one. When the callee uses stack for register save/
restore, especially RA, if nested call, concurrent access by multiple
harts on the same stack will cause data-race.

This patch sets up SP before `board_init_f_alloc_reserve`. A side effect
of this is that the memory layout has changed as the following:

+----------------+        +----------------+ <----- SPL_STACK/
|  ......        |        |  hart 0 stack  |        SYS_INIT_SP_ADDR
|  malloc_base   |        +----------------+
+----------------+        |  hart 1 stack  |
|  GD            |        +----------------+ If not SMP, N=1
+----------------+        |  ......        |
|  hart 0 stack  |        +----------------+
+----------------+   ==>  |  hart N-1 stack|
|  hart 1 stack  |        +----------------+
+----------------+        |  ......        |
|  ......        |        |  malloc_base   |
+----------------+        +----------------+
|  hart N-1 stack|        |  GD            |
+----------------+        +----------------+
|                |        |                |

Signed-off-by: Bo Gan <ganboing@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Leo <ycliang@andestech.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-07-24 13:17:26 +08:00
Manorit Chawdhry
86fab11024 Kconfig: Enable FIT_SIGNATURE if ARM64
Enabling FIT_SIGNATURE required the old authentication method to be
disabled so disable this for K3 SOCs and enable FIT_SIGNATURE for K3
Platforms.

Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
[ cleanup the patch ]
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-07-21 22:07:46 -04:00
Manorit Chawdhry
175535758a k3-*-binman: dts: Pack u-boot.dtb instead of soc specific dtb
FIT signature requires the updates to u-boot.dtb and the DTB that we
pack don't get updates with the changes of the signature node.

Pack u-boot.dtb as the default DTB so that the signature node changes
can be reflected in them.

(Note, this is only packaging the primary platform and the secondary
 platform will require manual changes for the FIT signature enablement)

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
[ add additional boards that were missing ]
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-21 22:07:46 -04:00
Andrew Davis
913cea388d arm: k3: Add regex/gsub command handling
The 'gsub' setexpr sub command is using when creating the FIT image
configuration string on K3 devices. Enable this for K3.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-07-21 20:35:50 -04:00
Manorit Chawdhry
2bfd63d57b mach-k3: common: correct the calculations for determining firewalls
The background firewall calculations were wrong, fix that to determine
both the background and foreground correctly.

Fixes: 8bfce2f998 ("arm: mach-k3: common: reorder removal of firewalls")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-07-21 19:37:58 -04:00
Manorit Chawdhry
0eef2bf36e Kconfig: j721s2: Fix the scratchpad base
Fix the regression that occurred during the alignment of binman series
merges along with these HS fixes that caused silent regression in this.

Fixes: 30a7ee87fd ("Kconfig: j721s2: Change K3_MCU_SCRATCHPAD_BASE to non firewalled region")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-07-21 19:37:57 -04:00
Manorit Chawdhry
44dab78580 arch: mach-k3: security: fix the check for authentication
Fix regression occurred during refactoring for the mentioned commit.

Fixes: bd6a247593 ("arm: mach-k3: security: separate out validating binary logic")

Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
2023-07-21 19:37:57 -04:00
Neha Malcom Francis
8db194d046 k3: tools: config.mk: Update makefile and remove scripts
Since binman is used to package bootloader images for all K3 devices, we
do not have to rely on the earlier methods to package them.

Scripts that were used to generate x509 certificate for tiboot3.bin and
generate tispl.bin, u-boot.img have been removed.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:59 -04:00
Neha Malcom Francis
9da80e7917 arm: k3-am65x-iot2050: Use binman for tispl.bin for iot2050
Move to using binman to generate tispl.bin which is used to generate the
final flash.bin bootloader for iot2050 boards.

Cc: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:59 -04:00
Neha Malcom Francis
6d6228ab8f am62a: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img
Support added for HS-SE, HS-FS and GP boot binaries for AM62ax.

HS-SE:
    * tiboot3-am62ax-hs-evm.bin
    * tispl.bin
    * u-boot.img

HS-FS:
    * tiboot3-am62ax-hs-fs-evm.bin
    * tispl.bin
    * u-boot.img

GP:
    * tiboot3.bin --> tiboot3-am62ax-gp-evm.bin
    * tispl.bin_unsigned
    * u-boot.img_unsigned

It is to be noted that the bootflow followed by AM62ax requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs
	* TIFS
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* DM
	* ATF
	* OP-TEE
	* A72 SPL
	* A72 SPL dtbs

u-boot.img:
	* A72 U-Boot
	* A72 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:59 -04:00
Neha Malcom Francis
ce46f51990 am625: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img
Support added for HS-SE, HS-FS and GP boot binaries for AM62.

HS-SE:
    * tiboot3-am62x-hs-evm.bin
    * tispl.bin
    * u-boot.img

HS-FS:
    * tiboot3-am62x-hs-fs-evm.bin
    * tispl.bin
    * u-boot.img

GP:
    * tiboot3.bin --> tiboot3-am62x-gp-evm.bin
    * tispl.bin_unsigned
    * u-boot.img_unsigned

It is to be noted that the bootflow followed by AM62 requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs
	* TIFS
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* DM
	* ATF
	* OP-TEE
	* A72 SPL
	* A72 SPL dtbs

u-boot.img:
	* A72 U-Boot
	* A72 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:59 -04:00
Neha Malcom Francis
106589aae7 j721s2: dts: binman: Package tiboot3.bin, tispl.bin and u-boot.img
Support has been added for both HS-SE, HS-FS  and GP images.

HS-SE:
    * tiboot3-j721s2-hs-evm.bin
    * tispl.bin
    * u-boot.img

HS-FS:
    * tiboot3-j721s2-hs-fs-evm.bin
    * tispl.bin
    * u-boot.img

GP:
    * tiboot3.bin --> tiboot3-j721s2-gp-evm.bin
    * tispl.bin_unsigned
    * u-boot.img_unsigned

It is to be noted that the bootflow followed by J721S2 requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs
	* TIFS
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* DM
	* ATF
	* OP-TEE
	* A72 SPL
	* A72 SPL dtbs

u-boot.img:
	* A72 U-Boot
	* A72 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:58 -04:00
Neha Malcom Francis
1bc527e8f4 am64x: dts: binman: Package tiboot3.bin, tispl.bin u-boot.img
Support added for HS and GP boot binaries for AM64x.

HS-SE:
    * tiboot3-am64x_sr2-hs-evm.bin
    * tispl.bin
    * u-boot.img

HS-FS:
    * tiboot3-am64x_sr2-hs-fs-evm.bin
    * tispl.bin
    * u-boot.img

GP:
    * tiboot3.bin --> tiboot3-am64x-gp-evm.bin
    * tispl.bin_unsigned
    * u-boot.img_unsigned

Note that the bootflow followed by AM64x requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs
	* sysfw
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* ATF
	* OP-TEE
	* A53 SPL
	* A53 SPL dtbs

u-boot.img:
	* A53 U-Boot
	* A53 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:58 -04:00
Neha Malcom Francis
77c29cb1b6 am65: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img
Support has been added for both HS-SE(SR 2.0) and GP(SR 2.0) images.

HS-SE:
	* tiboot3-am65x_sr2-hs-evm.bin
	* sysfw-am65x_sr2-hs-evm.itb
	* tispl.bin
	* u-boot.img

GP:
	* tiboot3.bin --> tiboot3-am65x_sr2-gp-evm.bin
	* sysfw.itb --> sysfw-am65x_sr2-gp-evm.itb
	* tispl.bin_unsigned
	* u-boot.img_unsigned

Note that the bootflow followed by AM65x requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs
sysfw.itb:
	* sysfw
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* ATF
	* OP-TEE
	* A53 SPL
	* A53 SPL dtbs

u-boot.img:
	* A53 U-Boot
	* A53 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:58 -04:00
Neha Malcom Francis
ca5f1e25e5 j7200: dts: binman: Package tiboot3.bin, tispl.bin, u-boot.img
Support has been added for both HS-SE(SR 2.0), HS-FS(SR 2.0) and GP
images.

HS-SE:
	* tiboot3-j7200_sr2-hs-evm.bin
	* tispl.bin
	* u-boot.img

HS-FS:
	* tiboot3-j7200_sr2-hs-fs-evm.bin
	* tispl.bin
	* u-boot.img

GP:
	* tiboot3.bin --> tiboot3-j7200-gp-evm.bin
	* tispl.bin_unsigned
	* u-boot.img_unsigned

It is to be noted that the bootflow followed by J7200 requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs
	* TIFS
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* DM
	* ATF
	* OP-TEE
	* A72 SPL
	* A72 SPL dtbs

u-boot.img:
	* A72 U-Boot
	* A72 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:58 -04:00
Neha Malcom Francis
177178685a j721e: dts: binman: Package tiboot3.bin, sysfw.itb, tispl.bin, u-boot.img
By providing entries in the binman node of the device tree, binman will
be able to find and package board config artifacts generated by
TIBoardConfig with sysfw.bin and generate the final image sysfw.itb.
It will also pick out the R5 SPL and sign it with the help of TI signing
entry and generate the final tiboot3.bin.

Entries for A72 build have been added to k3-j721e-binman.dtsi to
generate tispl.bin and u-boot.img.

Support has been added for both HS-SE(SR 1.1), HS-FS(SR 2.0) and GP images
In HS-SE, the encrypted system firmware binary must be signed along with
the signed certificate binary.

HS-SE:
	* tiboot3-j721e_sr1_1-hs-evm.bin
	* sysfw-j721e_sr1_1-hs-evm.itb
	* tispl.bin
	* u-boot.img

HS-FS:
	* tiboot3-j721e_sr2-hs-fs-evm.bin
	* sysfw-j721e_sr2-hs-fs-evm.itb
	* tispl.bin
	* u-boot.img

GP:
	* tiboot3.bin -->tiboot3-j721e-gp-evm.bin
	* sysfw.itb --> sysfw-j721e-gp-evm.itb
	* tispl.bin_unsigned
	* u-boot.img_unsigned

It is to be noted that the bootflow followed by J721E requires:

tiboot3.bin:
	* R5 SPL
	* R5 SPL dtbs

sysfw.itb:
	* TIFS
	* board-cfg
	* pm-cfg
	* sec-cfg
	* rm-cfg

tispl.bin:
	* DM
	* ATF
	* OP-TEE
	* A72 SPL
	* A72 SPL dtbs

u-boot.img:
	* A72 U-Boot
	* A72 U-Boot dtbs

Reviewed-by: Simon Glass <sjg@chromium.org>
[afd@ti.com: changed output binary names appropriately]
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:58 -04:00
Neha Malcom Francis
9b03bfe105 arm: dts: k3: Add support for packaging sysfw.itb and tiboot3.bin
Board config binary artifacts must be generated to be used by binman to
package sysfw.itb and tiboot3.bin for all K3 devices.

For devices that follow combined flow, these board configuration
binaries must again be packaged into a combined board configuration
blobs to be used by binman to package tiboot3.bin.

Add common k3-binman.dtsi to generate all the board configuration
binaries needed.

Also add custMpk.pem and ti-degenerate-key.pem needed for signing GP and
HS bootloader images common to all K3 devices.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
2023-07-21 19:36:58 -04:00
Nikhil M Jain
12fdacea5a board: ti: am62x: evm: Update function calls for splash screen
Use spl_dcache_enable, in place of setup_dram, arch_reserve_mmu to set
up pagetable, initialise DRAM and enable Dcache to avoid multiple
function calls.

Check for CONFIG_SPL_VIDEO in place of CONFIG_SPL_VIDEO_TIDSS to prevent
any build failure in case video config is not defined and video related
functions are called.

Check for CONFIG_SPL_SPLASH_SCREEN and CONFIG_SPL_BMP before calling
splash_display to avoid compilation failure.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
2023-07-21 15:32:12 -04:00
Nikhil M Jain
dd5d1c5dcc arch: arm: mach-k3: common: Return a pointer after setting page table
In spl_dcache_enable after setting up page table, set gd->relocaddr
pointer to tlb_addr, to get next location to reserve memory. Align
tlb_addr with 64KB address.

Signed-off-by: Nikhil M Jain <n-jain1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
2023-07-21 15:32:12 -04:00
Bryan Brattlof
efda93c6b5 arm: mach-k3: am62a7: change some prints to debug prints
There is little need to print the devstat information or when we exit a
function during a typical boot. Remove them to reduce the noise during
typical operation

Signed-off-by: Bryan Brattlof <bb@ti.com>
2023-07-21 15:32:12 -04:00
Tom Rini
7c97b715e9 arm: omap2: Fix warning in force_emif_self_refresh
The function declaration for force_emif_self_refresh takes no parameters
but does not specify this, only the prototype in the headers do.  As
clang will warn about this, correct it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-21 15:32:12 -04:00
Emanuele Ghidoli
70aa5a94d4 arm: mach-k3: am62: Fixup CPU core, gpu and pru nodes in fdt
AM62x SoC is available in multiple variant:
- CPU cores (Cortex-A) AM62x1 (1 core), AM62x2 (2 cores), AM62x4 (4 cores)
- GPU AM625x with GPU, AM623x without GPU
- PRU (Programmable RT unit) can be present or not on AM62x2/AM62x4

Remove the relevant FDT nodes by reading the actual configuration
from the SoC registers, with that change is possible to have a single
dts/dtb file handling the different variant at runtime.
While removing GPU node and CPU nodes also the watchdog node
in the same Module Domain is removed.

A similar approach is implemented for example on i.MX8 and STM32MP1 SoC.

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2023-07-21 15:32:12 -04:00
Emanuele Ghidoli
de3db25231 arm: mach-k3: am62: Add CTRLMMR_WKUP_JTAG_DEVICE_ID register definition
Add register address and relevant bitmasks and shifts.
Allow reading these information:
- device identification
- number of cores (part of device identification)
- features (currently: PRU / no PRU)
- security
- functional safety
- speed grade
- temperature grade
- package

Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Reviewed-by: Andrew Davis <afd@ti.com>
2023-07-21 15:32:12 -04:00
Emanuele Ghidoli
7b7288df34 arm: k3: Fix ft_system_setup so it can be enabled on any SoC
ft_system_setup cannot be enabled on SoC without msmc sram otherwise
fdt_fixup_msmc_ram function fails causing system reset.

Fix by moving fdt_fixup_msmc_ram to common_fdt.c file and creating
SoC (AM654, J721E and J721S2) specific files for fdt fixups.

This change was verified to not change anything on any existing board
(all the J721S2, AM654 and J721E boards requires it,
none of the remaining k3 boards require it).

Fixes: 30e96a2401 ("arm: mach-k3: Move MSMC fixup to SoC level")
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2023-07-21 15:32:12 -04:00
Nishanth Menon
f40f54bfed arm: dts: Fix build of am62a7 dtbs
am62a7 should be built with CONFIG_SOC_K3_AM62A7 not CONFIG_SOC_K3_AM625

Fixes: 6bdfa69155 ("arm: dts: introduce am62a7 u-boot dtbs")
Cc: Bryan Brattlof <bb@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Francesco Dolcini <francesco@dolcini.it>
Cc: Sjoerd Simons <sjoerd@collabora.com>
Cc: Wadim Egorov <w.egorov@phytec.de>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2023-07-21 15:32:12 -04:00
Nishanth Menon
d50f82815d arm: mach-k3: *: dev-data: Update to use ARRAY_SIZE
Instead of hard-coding the count of entries manually, use ARRAY_SIZE
to keep the count updates appropriately.

Cc: Bryan Brattlof <bb@ti.com>
Suggested-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
2023-07-21 15:32:12 -04:00
Vignesh Raghavendra
11626a33fa arm: mach-k3: am62a7_init: Open up FSS_DAT_REG3 firewall
On security enforced (HS-SE) devices ROM firewalls OSPI data region3 that
is present in above 64bit region. Open this up in bootloader to allow
Linux to access OSPI flashes in mmap mode.

Without this kernel will crash when accessing this region due to
firewall violations on HS-SE devices.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2023-07-21 13:13:50 -04:00
Tom Rini
226ecf8be4 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
For once this adds USB support for two SoCs: the H616 and the F1C100s
series. The rest is support for LPDDR3 DRAM chips on H616 boards.

Gitlab CI passed, and I booted that briefly on an H616 and an F1C200s
board. I don't have an H616 board with LPDDR3 DRAM, but reportedly that
works for Mikhail, and doesn't regress on my DDR3 boards.
2023-07-21 10:01:11 -04:00
Tom Rini
e7f7e2e1e2 Xilinx changes for v2023.10-rc1 v2
axi_emac:
 - Change return value if RX packet is not ready
 
 cadence_qspi:
 - Enable flash reset for Versal NET
 
 dt:
 - Various DT syncups with Linux kernel
 - SOM - reserved pmufw memory location
 
 fpga:
 - Add load event
 
 mtd:
 - Add missing dependency for FLASH_CFI_MTD
 
 spi/nand:
 - Minor cleanup in Xilinx drivers
 
 versal-net:
 - Prioritize boot device in boot_targets
 - Wire mini ospi/qspi/emmc configurations
 
 watchdog:
 - Use new versal-wwdt property
 
 xilinx:
 - fix sparse warnings in various places ps7_init*
 - add missing headers
 - consolidate code around zynqmp_mmio_read/write
 - switch to amd.com email
 
 zynqmp_clk:
 - Add handling for gem rx/tsu clocks
 
 zynq_gem:
 - Configure mdio clock at run time
 
 zynq:
 - Enable fdt overlay support
 
 zynq_sdhci:
 - Call dll reset only for ZynqMP SOCs
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Merge tag 'xilinx-for-v2023.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.10-rc1 v2

axi_emac:
- Change return value if RX packet is not ready

cadence_qspi:
- Enable flash reset for Versal NET

dt:
- Various DT syncups with Linux kernel
- SOM - reserved pmufw memory location

fpga:
- Add load event

mtd:
- Add missing dependency for FLASH_CFI_MTD

spi/nand:
- Minor cleanup in Xilinx drivers

versal-net:
- Prioritize boot device in boot_targets
- Wire mini ospi/qspi/emmc configurations

watchdog:
- Use new versal-wwdt property

xilinx:
- fix sparse warnings in various places ps7_init*
- add missing headers
- consolidate code around zynqmp_mmio_read/write
- switch to amd.com email

zynqmp_clk:
- Add handling for gem rx/tsu clocks

zynq_gem:
- Configure mdio clock at run time

zynq:
- Enable fdt overlay support

zynq_sdhci:
- Call dll reset only for ZynqMP SOCs
2023-07-21 09:57:59 -04:00
Michal Simek
c310c98201 arm64: zynqmp: Remove clock-names from pcap node
Clock is not used in driver and also not described in binding.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0a0fa0ba197fa4051a2c8a24e1451cefadce7517.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Michal Simek
4c360f6cfd arm64: zynqmp: Rename ams_ps/pl node names
Fix child node names to be aligned with dt-binding available in the Linux
kernel which requires names as ams-ps@ and ams-pl@.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8f1451d614f654cb0d0da1e799e876c078fbf2c9.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Michal Simek
20beff0ddb arm64: zynqmp: Remove interrupt/reg-names for AMS
These two properties are not described in DT binding and also not used by
driver that's why remove them.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b123c7e537dcf70802e828bbcd484a761a264186.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Piyush Mehta
a876a5112e arm64: zynqmp: remove snps, enable_guctl1_resume_quirk quirk for usb
To sync with the upstream code, removed 'snps,enable_guctl1_resume_quirk'
quirk for usb. This quirk is no more available in linux after the xilinx
release 2022.2.

This functionality is taken care of by the 'snps,resume-hs-terminations'
quirk.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b7a132116bf0248cdb558e04de3b06b412c4a0f.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Radhey Shyam Pandey
7cfddb4c07 arm64: zynqmp: add pmu interrupt-affinity
Explicitly specify interrupt affinity to avoid HW perfevents
need to guess. This avoids the following error upon linux boot:
armv8-pmu pmu: hw perfevents: no interrupt-affinity property,
guessing.

Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c2f55a10cf54c6004f5dfe2ea18bcb4cf04f5723.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Michal Simek
606121cdf4 arm64: zynqmp: Sync node name address with reg (mailbox)
Address in node name should match with the first reg property in DT.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/47bea10bbc3c88727c1fe839ff20e15a0c79c339.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Radhey Shyam Pandey
a8d4b67000 arm64: zynqmp: Add L2 cache nodes
Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.

Reported-by: John Toomey <john.toomey@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c8dfabab12c97922aaad7fa91be0cbc7e4021528.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Michal Simek
1ea11e8138 arm64: zynqmp: Fix usb reset over bootmode pins on zcu100
The commit a4180c3696 ("arm64: zynqmp: Add mode-pin GPIO controller DT
node") added usb phy reset over bootmode pins by default on usb0 only.
zcu100 is using usb0 as peripheral and usb1 as host. Unfortunately reset
line is shared for both usb ulpi phys but usb_rst_b is connected to usb5744
hub which is used only in host mode. Especially this chip requires reset to
operate properly that's why better assign gpio reset to usb1 instead of
usb0.
Without this change usb start crashed when runs.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1ca80ec5bf7a595c03822f3e4e3683298205067a.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Michal Simek
58601fbb8f arm64: zynqmp: Cover K24 revB/1 SOM
Extend compatible versions for K24 SOM.
Changes are not affecting SW behavior that's why all versions are
compatible to each other.
Describing all revisions is done by purpose because user space SW is
reading compatible string for logic around DT overlays and bitstreams.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92eba01ac316e58bd2d3508b0e63bbfafbedbb73.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Michal Simek
efa1ddea07 arm64: zynqmp: Record compatible string for kv260 rev2
PCB rev2 compare to rev1 has some changes in PL side (IAS sensor AR1335
autofocus feature). PS side is completely unchanged.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/42f78dee8429eeac016d73de5c73af46fdaf4a98.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Harini Katakam
6a251f2488 arm64: zynqmp: Assign TSU clock frequency for KV and KD boards
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KV and KD carrier cards to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/4b758d503ef545e4d25d3930b0eb0793f1c415d2.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:39 +02:00
Harini Katakam
414fc91f4e arm64: zynqmp: Increase reset assert time for TI SGMII PHY
Increase reset assert time for TI SGMII PHY on KR260 CC starting
6.1 kernel. This PHY does not come out of reset with the existing
100us pulse width as per testing on multiple carrier cards. The reset
is driven via a PCA9570 I2C expander. The expander driver was updated
to an upstream version in 6.1 where gpio_chip _set was optimized.
Delays in earlier kernels may have masked this issue. This is a safe
workaround value for assert pulse width before the discussions are
resolved with TI.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8fb9f17d43a43ef504c9f29006cd686cce8ac98b.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
369d04d643 arm64: zynqmp: Fix gpio comment about No of gpios
There are total 174 gpios but from 0 - 173 that's why fix comment to
reflect it.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c7e94b334e7dd6297e0d3a36a6a3d04bd7e9e967.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Harini Katakam
f668961485 arm64: zynqmp: Assign TSU clock frequency for KR260
Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KR260 CC to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Parth Gajjar
d95fc99a74 arm64: zynqmp: Update MALI 400 interrupt and clock names
Motivation for the commit is to utilize the upstream community
device tree so that the either modified ARM Mali 400 driver
or upstream lima driver can be used.

Signed-off-by: Parth Gajjar <parth.gajjar@amd.com>
Signed-off-by: Vishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/1678181001-2327-2-git-send-email-parth.gajjar@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/89d046a9da5638e8b4918f80f3245d73ea46f99f.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Manikanta Guntupalli
28dc356e66 xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by
Linux.
"enforced open drain please flag it properly in DT/ACPI DSDT/board
file."

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Varalaxmi Bingi
39bdb96498 arm: xilinx: Setting default i2c clock frequency to 400kHz
Setting default i2c clock frequency for Zynq and ZynqMP to maximum rate of
400kHz. Current default value is 100kHz.

Signed-off-by: Varalaxmi Bingi <varalaxmi.bingi@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fb46fe911a68b79c8e4d150ca90c4e94eb5fb9e1.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
174d728471 arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
5b90412cbf xilinx: Consolidate zynqmp_mmio_read/write in zynqmp_firmware.h
zynqmp_mmio_read/write() are firmware provided hooks that's why use only
zynqmp_firmware.h for function declaration.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e7489556f9e447c737a578c169d7e1e43586a273.1687524706.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
37688da586 xilinx: versal-net: Add mini eMMC 5.1 configuration
Add support for Versal NET mini eMMC 5.1 configuration. Add device tree
and defconfig.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
38e0fc06b2 xilinx: versal-net: Add mini ospi configuration
Add support for Versal NET mini Octal SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Octal SPI
related settings are enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
96683d3436 xilinx: versal-net: Add mini qspi configuration
Add support for Versal NET mini Quad SPI flash configuration. This runs
from onchip memory, so it has to be compact. Hence only Quad SPI
related settings are enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614121351.21521-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Ashok Reddy Soma
34dec6a443 cadence_qspi: Enable flash reset for Versal NET platform
Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.

Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.

Add read_delay initialization for Versal NET also.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2023-07-21 09:00:38 +02:00
Sharath Kumar Dasari
85a2d124cd arm64: zynqmp: Fix the memory node for k26/k24 kria som boards
PMUFW requires top 1MB of the lower DDR memory reserved for its operation,
this is missing in k26/k24 sm static dts files because of which U-Boot
throws warning messages "efi_free_pool: illegal free" as EFI puts
some code to that space which shouldn't happen.

Signed-off-by: Sharath Kumar Dasari <sharath.kumar.dasari@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/57452d16df2d48593de206bebf877d2c2cfe7bf1.1685966389.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Tom Rini
e896279ac3 binman mkimage and template enhancements
misc fixes
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Merge tag 'dm-pull-20jul23' of https://source.denx.de/u-boot/custodians/u-boot-dm

binman mkimage and template enhancements
misc fixes
2023-07-20 21:31:31 -04:00
Mikhail Kalashnikov
ecb896cec7 sunxi: H616: add LPDDR3 DRAM support
The H616 SoC has support for several types of DRAM: DDR3, LPDDR3,
DDR4 and LPDDR4.
At the moment, the driver only supports DDR3 memory.
Let's extend the driver to support the LPDDR3 memory. All "magic"
values obtained from the boot0.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21 00:54:19 +01:00
Mikhail Kalashnikov
5d6f013adc sunxi: H616: add DRAM type selection
Allwinner H616 SoC supports several types of DRAM memory. To further
integrate other types of memory, we need to add this delimitation.

Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2023-07-21 00:54:13 +01:00
Andre Przywara
78aa00c38e sunxi: H616: dram: split struct dram_para
Currently there is one DRAM parameter struct for the Allwinner H616 DRAM
"driver". It contains many fields that are compile time constants
(set by Kconfig variables), though there are also some fields that are
probed and changed over the runtime of the DRAM initialisation.

Because of this mixture, the compiler cannot properly optimise the code
for size, as it does not consider constant propagation in its full
potential.

Help the compiler out by splitting that structure into two: one that only
contains values known at compile time, and another one where the values
will actually change. The former can then be declared "const", which will
let the compiler fold its values directly into the code using it.

We also add "const" tags for some new "struct dram_config" pointers, to
further increase code optimisation.
To help the compiler optimise the code further, the definition of the
now "const struct dram_para" has to happen at a file-global level, so
move that part out of sunxi_dram_init().

That results in quite some code savings (almost 2KB), and helps to keep
the code small with the LPDDR3 support added later.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
457e2cd665 sunxi: H616: dram: const-ify DRAM function parameters
There are quite some functions in the Allwinner H616 DRAM "driver", some
of them actually change the parameters in the structure passed to them,
but many are actually not.
To increase the optimisation potential for the code, mark those functions
that just read members of the passed dram_para struct as "const".
This in itself does not decrease the code size, but lays the groundwork
for future changes doing so.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
c9dd624a38 sunxi: dram: make MBUS configuration functions static
The usage of the C keyword "inline" seems to be a common
misunderstanding: it's a *hint* only, and modern compilers will inline
(or not) functions based on their own judgement and provided compiler
options.
So while marking functions as "inline" does not do much, missing the
"static" keyword will force to compiler to spell out a version of the
function for potential external callers, which actually increases the
code size (though hopefully the linker will drop the function).

Change the "inline" attribute for the mbus_configure_port() functions in
some Allwinner DRAM drivers to "static", so that the explicit version
can actually be dropped from the object file, reducing the code size.

"static inline" has a use case in header files, where it avoids a warning
if a .c file including this header does not use the particular function.
In a .c file itself "static inline" is not useful otherwise, so just use
static here as well.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-07-21 00:29:42 +01:00
Andre Przywara
fcd9220d66 sunxi: Kconfig: rework PHY_USB_SUN4I selection
At the moment we use "select" in each Allwinner SoC's Kconfig section to
include the USB PHY driver in the build. This means it cannot be disabled
via Kconfig, although USB is not really a strictly required core
functionality, and a particular board might not even include USB ports.

Rework the Kconfig part by removing the "select" lines for each SoC's
section, and instead letting it default to "y" in the PHY driver section
itself. We use "depends on !" to exclude the few SoCs we don't support
(yet). The Allwinner V3s does not enable USB (PHY) support at the moment,
even though it should work: let the PHY default to "n" to keep the
current behaviour.

Also the MUSB USB driver directly calls some functions from the PHY
driver, so let the former depend on the PHY driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Sam Edwards <CFSworks@gmail.com>
2023-07-21 00:26:36 +01:00
Simon Glass
8163907adf stm32mp15: Avoid writing symbols in SPL
These boards use SPL in a mkimage entry and apparently access the symbol
containing the image position of U-Boot, but put U-Boot in another
image. This means that binman is unable to fill in the symbol correctly
in the SPL binary.

This doesn't matter at present since mkimage doesn't support symbol
writing. But with the upcoming conversion to a section, it will. So add
a property to disable symbol writing.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-20 14:10:58 -06:00
Sergei Antonov
76e1607617 sandbox: fix a compilation error
With sandbox and sandbox64 configurations:

In file included from .../u-boot/include/test/test.h:156,
                 from .../u-boot/include/test/lib.h:9,
                 from .../u-boot/test/lib/test_crc8.c:8:
.../u-boot/arch/sandbox/include/asm/test.h: In function ‘sandbox_sdl_set_bpp’:
.../u-boot/arch/sandbox/include/asm/test.h:323:17: error: ‘ENOSYS’ undeclared (first use in this function)
  323 |         return -ENOSYS;
      |                 ^~~~~~

Per Tom Rini's suggestion:
move that function prototype over to arch/sandbox/include/asm/sdl.h
and make test/dm/video.c include <asm/sdl.h>

Cc: Simon Glass <sjg@chromium.org>
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Sergei Antonov <saproj@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-07-20 14:10:57 -06:00
Tom Rini
9ef4166ff9 arm: mx5: Correct mxc_set_clock function prototype
With gcc-13.1 we get a warning about enum vs int here, so correct the
declaration to match the implementation.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-20 14:48:20 -04:00
Tom Rini
bfbab7b27e mips: octeon: Correct types in cvmx-pko3-queue
When building with gcc-13.1 we see that the prototype for
cvmx_pko3_sq_config_children does not match the declaration. Make these
match and correct a typo in the function's version of the docs that the
prototype did not have, as part of keeping those in-sync.

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-07-20 14:48:20 -04:00
Tom Rini
5dcfc99b2b Merge tag 'fsl-qoriq-2023-7-13' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
Enable DM_SERIAL for T2080RDB, T4240RDB, T1042D4RDB, T1024RDB
2023-07-19 07:59:34 -04:00
Simon Glass
b8956425d5 x86: Switch QEMU over to use the bochs driver
This is more convenient since it does not require a video BIOS. Enable
it for QEMU.

Also drop use of video in SPL for the 64-bit QEMU, since it not needed
now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:15 +08:00
Simon Glass
dac1fa5c19 x86: Make sure that the LPC is active before SDRAM init
Some boards need to access GPIOs to determine which SDRAM is fitted to the
board, for example chromebook_link. Probe this device (if it exists) to
make sure that this works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:15 +08:00
Simon Glass
df1bb2cb0b x86: link: Support Micron memory
Add the required tag so that micron memory can be set up correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:15 +08:00
Simon Glass
e2e7de8747 x86: Convert some debug statements to use logging
Move from using debug() to log_debug() so that we don't have to use the
__func__ parameter and can access other logging features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:14 +08:00
Simon Glass
6a32489782 x86: Record the start and end of the tables
The ACPI tables are special in that they are passed to EFI as a separate
piece, independent of other tables.

Also they can be spread over two areas of memory, e.g. with QEMU we end
up with tables kept in high memory as well.

Add new global_data fields to hold this information and update the bdinfo
command to show the table areas.

Move the rom_table_end variable into the loop that uses it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:08 +08:00
Simon Glass
8856d613cb x86: Refactor table-writing code a little
The implementation of write_tables() is confusing because it uses the
rom_table_start variable as the address pointer as it progresses.

Rename it to rom_addr to make the code clearer. Move the rom_table_end
variable into the block where it is used.

Also update logging to use the ACPI category, now that it is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
e7595aa350 x86: Allow logging to be used in SPL reliably
When global_data is relocated, log_head moves in memory, meaning that
the items in that list point to the wrong place.

Disable logging when making the change, then reenable it afterwards, so
that logging works normally.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
7c10e111c1 x86: Init video in SPL if enabled
When video is required in SPL, set this up ready for use. Ignore any
problems since it may be that video is not actually available and we
still want to continue on to U-Boot proper in that case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
3525258019 x86: Ensure SPL banner is only shown once
Print the banner in SPL init only if the spl_board_init() function isn't
enabled. The spl_board_init() function is in the same file, but is called
later, by board_init_r().

This avoids printing two banners, which causes tests to fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
5345700d2a x86: Allow video-BIOS code to be built for SPL
With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e.
SPL. Add a Kconfig option for this, adjust the Makefile rules and use
CONFIG_IS_ENABLED() where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
8f015d3781 x86: Improve the trampoline in 64-bit mode
At present this leaves the stack at the pre-relocation value. This is not
ideal since we want to have U-Boot running entirely from the top of
memory.

In addition, the new global_data pointer is not actually used, since
the global_data pointer itself is relocated, then the pre-relocation value
is changed, so the effective value (after relocation) does not update.

Adjust the implementation to follow the 32-bit code more closely, with a
trampoline function which is passed the new stack and global_data pointer.
This ensures that the correct values come through even when relocating.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:07 +08:00
Simon Glass
78f24d8f34 x86: Show an error when a BIOS exception occurs
Rather than silently hanging, show an error first. This can happen when
there is something wrong with the video BIOS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
67884002f4 x86: Correct get_sp() implementation for 64-bit
Use an assembler implementation as is done for i386, so that the results
are equivalent for i386 and x86_64.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
633af11dd6 x86: Show the CPU physical address size with bdinfo
This is useful information so show it with the bdinfo command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
de94db8132 x86: Add a comment for board_init_f_r_trampoline()
Add a comment for this function in the header.

Change the function (and the one after) to use __noreturn to keep
checkpatch happy.

Add docs to board_init_f_r() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
b73dba7a83 x86: Tidy up EFI code in interrupt_init()
The ll_boot_init() check handles the EFI case so we don't need the rest
of the code. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
4fb2536e5b x86: Allow listing MTRRs in SPL
Move MTRR-listing code into a common file so it can be used from SPL.
Update the 'mtrr' command to call it.

Use this in SPL just before adjusting the MTRRs, so we can see the state
set up by the board. Only show it when debug is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
d0dfbf548d x86: zimage: Export the function to obtain the cmdline
Allow reading the command line from a zimage, so that it can be recorded
in the bootflow.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-17 13:38:35 +08:00
Simon Glass
c886557c18 x86: Add a function to boot a zimage
Add a direct interface to booting a zimage, so that bootstd can call it
without going through the command-line interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 13:38:35 +08:00
Christophe Leroy
64948e247e powerpc: Fix flush_cache() speed regression
Flushing kernel image after decompression was taking 113 milliseconds
with U-boot 2022.10. With U-boot 2023.01 and 2023.04, flushing
the same amount of memory takes approx 1.5 seconds. With
U-boot 2023.07-rc6, it takes 6.5 seconds.

powerpc flush_cache() function used to call WATCHDOG_RESET() after
flushing every cacheline. At that time WATCHDOG_RESET() was light
so the operation was almost seamless.

But commit 29caf9305b ("cyclic: Use schedule() instead of
WATCHDOG_RESET()") replaced WATCHDOG_RESET() by schedule() and that
started to hurt with U-boot 2022.10.

And in U-boot 2023.07-rc6 that's even worse after
commit 26e8ebcd7c ("watchdog: mpc8xxx: Make it generic").

In the meantime commit 729c1fe656 ("powerpc: introduce
CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD") gives us the opportinity to
only call schedule() every given chunk of data instead of every
cacheline. As explained in that commit there is no point in pinging
the watchdog after every cacheline flush, so lets define a sensible
default chunk size of 4k which matches to size of a page on most
powerpc platforms.

With that new default threshold, the culprit flushing performed after
kernel image decompression now takes 85 milliseconds on a powerpc 8xx.

Fixes: 29caf9305b ("cyclic: Use schedule() instead of WATCHDOG_RESET()")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2023-07-14 15:21:08 -04:00
Jim Liu
d136610988 arch: arm: npcm8xx: add cpu version and 4G ram support
Add npcm8xx A2 cpu version check
and add 4G RAM support

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14 15:21:07 -04:00
Jim Liu
7870043c4b ARM: dts: npcm8xx: fix dts node error
The SHA and OTP should under the ahb node

Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
2023-07-14 15:21:07 -04:00
Simon Glass
87c1a4130c expo: Add tests for the configuration editor
Add some simple tests and a helpful script to make the configuration
editor easier to set up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14 12:54:51 -04:00
Simon Glass
82cafee133 expo: Support building an expo from a description file
The only way to create an expo at present is by calling the functions to
create each object. It is useful to have more data-driven approach, where
the objects can be specified in a suitable file format and created from
that. This makes testing easier as well.

Add support for describing an expo in a devicetree node. This allows more
complex tests to be set up, as well as providing an easier format for
users. It also provides a better basis for the upcoming configuration
editor.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14 12:54:51 -04:00
Simon Glass
7230fdb383 expo: Add spacing around menus and items
It looks better if menus have a bit of an inset, rather than be drawn hard
up against the background. Also, menu items look better if they have a bit
of spacing between them.

Add theme options for these and implement the required changes.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14 12:54:51 -04:00
Simon Glass
06d3414ac7 sandbox: Fix quiting when the LCD window is closed
With recent changes to how sandbox handles reset, closing the window
currently just restarts sandbox.

Use the correct sysreset type to tell it to shut down.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-14 12:54:50 -04:00
Tom Rini
c990ecba4d Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Thecus: Misc enhancement and cleanup (Tony)
- mvebu: Add AC5X Allied Telesis x240 board support incl NAND
  controller enhancements for this SoC (Chris)
2023-07-13 20:38:50 -04:00
Tom Rini
f6da5e9273 u-boot-imx-20230713
-------------------
 
 Merge for 2023.10.
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
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Merge tag 'u-boot-imx-20230713' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20230713
-------------------

Merge for 2023.10.

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16888
2023-07-13 20:38:24 -04:00
Chris Packham
366a863e65 arm: mvebu: Remove unused alias from RC AC5X dts
The sar-reg0 alias was left over from an earlier iteration of the
patches adding support for this board. Remove the unused alias.

Fixes: 6cc8b5db40 ("arm: mvebu: Add RD-AC5X board")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13 15:54:11 +02:00
Chris Packham
4c97c4b590 arm: mvebu: Add Allied Telesis x240 board
The x240 and SE240 are a series of L2+ switches from Allied Telesis.
There are a number of them in the range but as far as U-Boot is
concerned all the CPU block components are the same so there's only one
board defined.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2023-07-13 15:53:57 +02:00
Fabio Estevam
e713364f36 mx23_olinuxino: Convert to CONFIG_DM_SERIAL
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:41 +02:00
Fabio Estevam
9a38d889a1 mx23evk: Convert to CONFIG_DM_SERIAL
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:41 +02:00
Fabio Estevam
68bad63ee0 mx28evk: Convert to CONFIG_DM_SERIAL
The conversion to CONFIG_DM_SERIAL is mandatory, so select this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:41 +02:00
Andrejs Cainikovs
214a986f13 arm64: dts: verdin-imx8mp: add ctrl_sleep_moci# hog
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.

To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13 11:29:41 +02:00
Andrejs Cainikovs
cf77093e31 arm64: dts: verdin-imx8mm: add ctrl_sleep_moci# hog
Drive CTRL_SLEEP_MOCI# high at boot (SPL) using a GPIO hog, this signal
may be used to control some power-rails on the carrier board, therefore
it should be set to high when the module is booting.

To do this as early as possible is generally a good idea and the issue
was noticed on the Yavia carrier board where it is needed to power the
I2C EEPROM on the carrier board.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13 11:29:41 +02:00
Marcel Ziswiler
cd9a3e3f90 verdin-imx8mm/verdin-imx8mp: synchronise device trees with linux
Synchronise device trees with linux v6.5-rc1.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2023-07-13 11:29:40 +02:00
Adam Ford
788ff422e5 arm: dts: imx8mp-beacon-kit: Enable USB Power domains
The USB Power domains should not have been removed as it causes
the board to hang if the USB is started.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:40 +02:00
Adam Ford
451799a6ce arm: dts: imx8mp: Sync the DT with kernel 6.4-rc4
Several changes have been made to the device tree
in the kernel, so update that as well as the
corresponding imx8mp-u-boot.dtsi files to prevent
breaking the booting.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2023-07-13 11:29:40 +02:00
Hugo Villeneuve
1b4c3e6125 imx8mn-var-som: adjust PHY reset gpios according to hardware configuration
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.

For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.

The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.

To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
2023-07-13 11:29:40 +02:00
Marek Vasut
cb5fe9e336 ARM: imx: romapi: Fix signed integer bitwise ops misuse
Bitwise operations on signed integers are not defined,
replace them with per-call checks.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
2023-07-13 11:29:40 +02:00
Tim Harvey
c8645e7411 configs: imx8m: Prepare imx8m-venice boards for HAB support
In order to enable HAB, FSL_CAAM, ARCH_MISC_INIT and
SPL_CRYPTO should be enabled in Kconfig like other i.MX8M
boards.

This also needs to occur in the SPL so enable CONFIG_SPL_BOARD_INIT and
add a void spl_board_init function which calls arch_misc_init to probe
the CAAM driver.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Maximus Sun
2159f7d9b6 imx: priblob: Update to use structure
Use structure to avoid define CAAM_SCFGR for each platform

Signed-off-by: Maximus Sun <maximus.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
14d7eedf77 imx: imx8m: add CAAM_BASE_ADDR
Add CAAM_BASE_ADDR which will be used by priblob.c

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Gaurav Jain
d7b5fba9a5 imx: imx8: ahab: sha256: enable image verification using ARMv8 crypto extension
add support for SHA-256 secure hash algorithm using the ARM v8
SHA-256 instructions for verifying image hash.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
00ce4153fb imx: ahab: Update AHAB for iMX8 and iMX8ULP
Abstract common interfaces for AHAB authentication operations.
Then share some common codes for AHAB and SPL container authentication

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Nitin Garg
6e81ca220e imx: parse-container: Use malloc for container processing
If the container has image which conflicts with
spl_get_load_buffer address, there are processing failures.
Use malloc instead of spl_get_load_buffer.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
dc2d49209e imx: imx8m: clock: not configure reserved SRC register
i.MX8M[M,N,P] SRC not has 0x1004 offset register, so drop it.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
e8cd1f60d9 imx: imx8: bootaux: Add i.MX8 M4 boot support
1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download
   M4 image to any DDR address first. Then use the
   "bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0
   or CM4_1, the default core id is 0 for CM4_0.

   Since current M4 only supports running in TCM. The bootaux will copy
   the M4 image from DDR to its TCML.

2. Implment bootaux for HIFI on QXP
   command: bootaux 0x81000000 1

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
8d84a8f487 imx: bootaux: Fix bootaux issue when running on ARM64
The bootaux uses ulong to read private data and write to M4 TCM,
this cause problem on ARM64 platform where the ulong is 8bytes.
Fix it by using u32 to replace ulong.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
9395eb05ee imx: bootaux: change names of MACROs used to boot MCU on iMX devices
The current bootaux supports i.MX8M and i.MX93, but the name "_M4_"
implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4,
i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place
of "_M4_" to simplify the naming.

Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
455ebf8f45 imx: iamge-container: support secondary container
Add the support for loading image from secondary container set on
iMX8QM B0, iMX8QXP C0.

Using the SCFW API to get container set index, if it is the secondary
boot, get the offset from fuse and apply to offset of current container
set beginning for loading.

Also override the emmc boot partition to check secondary boot and switch
to the other boot part.

This patch is modified from NXP downstream:
imx8: Fix the fuse used by secondary container offset
imx: container: Skip container set check for ROM API
imx8: spl: Support booting from secondary container set

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
3b5c1d0ea1 imx: image-container: Fix container header checking
Checking container header tag and version is wrong, it causes to fail
to bypass invalid container

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
b645f95da9 imx: hab: Fix coverity issue in HAB event decoding
Fix below coverity issues caused by get_idx function where "-1" is
compared with uint8_t "element"
343336 Unsigned compared with neg
343337 Operands don't affect result

Additional, this function returns "-1" will cause overflow to
event string array.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
1c3f5df259 imx: imx8ulp: start the ELE RNG at boot
On the imx8ulp A1 SoC, the ELE RNG needs to be manually started.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Clement Faure
859f4e02a8 imx: cmd_dek: add ELE DEK Blob generation support
Add ELE DEK Blob generation for the cmd_dek command.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Ye Li
f0e974e1e4 imx: cmd_dek: Fix Uninitialized pointer read
Fix Coverity (CID 21143558).
When tee_shm_register returns failure, the shm_input pointer is
invalid, should not free it. Same issue also exists on registering
shm_output.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
d0e2a012a3 imx: ele_api: add DEK Blob generation
- Add crc computation.
- Add ele_generate_dek_blob API for encrypted boot support.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
31e5ec2323 imx: ele_api: support program secure fuse and return lifecycle
Add two ELE API: ele_return_lifecycle_update and ele_write_secure_fuse
Add two cmd: ahab_return_lifecycle and ahab_sec_fuse_prog

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
ef5bdfc273 imx: ele_ahab: use hextoul
Use hextoul which looks a bit simpler.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
914ede6978 imx: parse-container: fix build warning
Fix build warning:
warning: format ‘%x’ expects argument of type ‘unsigned int’, but argument 3
has type ‘u64’ {aka ‘long long unsigned int’} [-Wformat=]
         printf("can't find memreg for image %d load address 0x%x, error %d\n",
warning: format ‘%lx’ expects argument of type ‘long unsigned int’, but
argument 3 has type ‘sc_faddr_t’ {aka ‘long long unsigned int’} [-Wformat=]
          debug("memreg %u 0x%lx -- 0x%lx\n", mr, start, end);

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
d3ee9dbd59 imx: use generic name ele(EdgeLockSecure Enclave)
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave
code including comment, folder and API name to ELE to align.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Peng Fan
dd654caac0 imx: mach: correct SCU API usage
The return value is int type, not sc_err_t(u8), correct the usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 11:29:40 +02:00
Camelia Groza
eab4cf5d64 powerpc: dts: t1024rdb: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 16:54:59 +08:00
Camelia Groza
51f976d40d powerpc: dts: t1024rdb: add serial nodes
Add the serial node descriptions similar to Linux v6.4 for the
t1024rdb board and its dependencies.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 16:54:56 +08:00
Camelia Groza
8cfb187681 powerpc: dts: t1042d4rdb: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 16:54:44 +08:00
Camelia Groza
014bad7b60 powerpc: dts: t1042d4rdb: add serial nodes
Add the serial node descriptions similar to Linux v6.4 for the
t1042d4rdb board and its dependencies.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 16:54:41 +08:00
Camelia Groza
cd94430087 powerpc: dts: t4240rdb: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 16:54:32 +08:00
Camelia Groza
7da20e7889 powerpc: dts: t4240rdb: add serial nodes
Add the serial node descriptions similar to Linux v6.4 for the t4240rdb
board and its dependencies.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 16:54:30 +08:00
Camelia Groza
9e97755387 powerpc: dts: t2080rdb: tag serial nodes with bootph-all
Make sure the serial driver is initialized before relocation by tagging
the serial nodes with "bootph-all". Add these u-boot specific properties
to an *-u-boot.dtsi file.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2023-07-13 16:54:18 +08:00