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riscv: define a cache line size for the generic CPU

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The USB 3.0 driver xhci-mem.c requires CONFIG_SYS_CACHELINE_SIZE to be set.

Define the cache line size for QEMU on RISC-V to be 64 bytes.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
This commit is contained in:
Heinrich Schuchardt 2023-07-21 18:01:18 +02:00 committed by Leo Yu-Chi Liang
parent 9070496794
commit 6aabe229f8
1 changed files with 1 additions and 0 deletions
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1
arch/riscv/cpu/generic/Kconfig
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@ -6,6 +6,7 @@ config GENERIC_RISCV
bool
select BINMAN if SPL
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)