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imx: bootaux: change names of MACROs used to boot MCU on iMX devices

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The current bootaux supports i.MX8M and i.MX93, but the name "_M4_"
implies that the SoCs have Cortex-M4. Actually i.MX8MM/Q use Cortex-M4,
i.MX8MN/P use Cortex-M7, i.MX93 use Cortex-M33, so use "_MCU_" in place
of "_M4_" to simplify the naming.

Signed-off-by: faqiang.zhu <faqiang.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Peng Fan 2023-06-15 18:09:18 +08:00 committed by Stefano Babic
parent 455ebf8f45
commit 9395eb05ee
10 changed files with 25 additions and 25 deletions
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2
arch/arm/include/asm/arch-imx8m/imx-regs.h
View file

@ -13,7 +13,7 @@
#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
#define M4_BOOTROM_BASE_ADDR 0x007E0000
#define MCU_BOOTROM_BASE_ADDR 0x007E0000
#define GPIO1_BASE_ADDR 0X30200000
#define GPIO2_BASE_ADDR 0x30210000

2
arch/arm/include/asm/arch-mx6/imx-regs.h
View file

@ -23,7 +23,7 @@
#define GPU_ARB_END_ADDR 0x01803FFF
#define APBH_DMA_ARB_BASE_ADDR 0x01804000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
#define MCU_BOOTROM_BASE_ADDR 0x007F8000
#elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x00100000

2
arch/arm/include/asm/arch-mx7/imx-regs.h
View file

@ -18,7 +18,7 @@
#define GIC400_ARB_END_ADDR 0x31007FFF
#define APBH_DMA_ARB_BASE_ADDR 0x33000000
#define APBH_DMA_ARB_END_ADDR 0x33007FFF
#define M4_BOOTROM_BASE_ADDR 0x00180000
#define MCU_BOOTROM_BASE_ADDR 0x00180000
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)

6
arch/arm/mach-imx/imx9/imx_bootaux.c
View file

@ -13,7 +13,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
{
struct arm_smccc_res res;
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0,
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0,
0, 0, 0, 0, &res);
return res.a0;
@ -25,7 +25,7 @@ int arch_auxiliary_core_down(u32 core_id)
printf("## Stopping auxiliary core\n");
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STOP, 0, 0,
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STOP, 0, 0,
0, 0, 0, 0, &res);
return 0;
@ -40,7 +40,7 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
printf("## Starting auxiliary core addr = 0x%08lX...\n", addr);
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, addr, 0,
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, addr, 0,
0, 0, 0, 0, &res);
return 0;

24
arch/arm/mach-imx/imx_bootaux.c
View file

@ -124,15 +124,15 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr)
printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n",
stack, pc);
/* Set the stack and pc to M4 bootROM */
writel(stack, M4_BOOTROM_BASE_ADDR);
writel(pc, M4_BOOTROM_BASE_ADDR + 4);
/* Set the stack and pc to MCU bootROM */
writel(stack, MCU_BOOTROM_BASE_ADDR);
writel(pc, MCU_BOOTROM_BASE_ADDR + 4);
flush_dcache_all();
/* Enable M4 */
/* Enable MCU */
if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, 0, 0, 0, 0, NULL);
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0, 0, 0, NULL);
} else {
clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET,
SRC_M4C_NON_SCLR_RST_MASK, SRC_M4_ENABLE_MASK);
@ -147,7 +147,7 @@ int arch_auxiliary_core_check_up(u32 core_id)
unsigned int val;
if (IS_ENABLED(CONFIG_IMX8M)) {
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, 0, 0, 0, 0, &res);
arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res);
return res.a0;
}
@ -164,13 +164,13 @@ int arch_auxiliary_core_check_up(u32 core_id)
* the reset vector at the head for the image, with SP and PC
* as the first two words.
*
* Per the cortex-M reference manual, the reset vector of M4 needs
* to exist at 0x0 (TCMUL). The PC and SP are the first two addresses
* of that vector. So to boot M4, the A core must build the M4's reset
* Per the cortex-M reference manual, the reset vector of M4/M7 needs
* to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses
* of that vector. So to boot M4/M7, the A core must build the M4/M7's reset
* vector with getting the PC and SP from image and filling them to
* TCMUL. When M4 is kicked, it will load the PC and SP by itself.
* The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for
* accessing the M4 TCMUL.
* TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself.
* The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for
* accessing the M4/M7 TCMUL/IDTCM.
*/
static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])

2
board/kontron/sl-mx8mm/sl-mx8mm.c
View file

@ -37,7 +37,7 @@ struct efi_capsule_update_info update_info = {
int board_phys_sdram_size(phys_size_t *size)
{
u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
u32 ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
if (ddr_size == 4) {
*size = 0x100000000;

2
board/kontron/sl-mx8mm/spl.c
View file

@ -106,7 +106,7 @@ static void spl_dram_init(void)
}
gd->ram_size = size;
writel(size, M4_BOOTROM_BASE_ADDR);
writel(size, MCU_BOOTROM_BASE_ADDR);
}
int do_board_detect(void)

2
board/technexion/pico-imx8mq/pico-imx8mq.c
View file

@ -54,7 +54,7 @@ int board_early_init_f(void)
int board_phys_sdram_size(phys_size_t *size)
{
int ddr_size = readl(M4_BOOTROM_BASE_ADDR);
int ddr_size = readl(MCU_BOOTROM_BASE_ADDR);
if (ddr_size == 0x4) {
*size = 0x100000000;

2
board/technexion/pico-imx8mq/spl.c
View file

@ -89,7 +89,7 @@ static void spl_dram_init(void)
printf("%s: LPDDR4 %d GiB\n", __func__, size);
ddr_init(dram_timing);
writel(size, M4_BOOTROM_BASE_ADDR);
writel(size, MCU_BOOTROM_BASE_ADDR);
}
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)

6
include/imx_sip.h
View file

@ -13,8 +13,8 @@
#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
#define IMX_SIP_SRC 0xC2000005
#define IMX_SIP_SRC_M4_START 0x00
#define IMX_SIP_SRC_M4_STARTED 0x01
#define IMX_SIP_SRC_M4_STOP 0x02
#define IMX_SIP_SRC_MCU_START 0x00
#define IMX_SIP_SRC_MCU_STARTED 0x01
#define IMX_SIP_SRC_MCU_STOP 0x02
#endif