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Merge tag 'fsl-qoriq-2023-7-13' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq

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Enable DM_SERIAL for T2080RDB, T4240RDB, T1042D4RDB, T1024RDB
This commit is contained in:
Tom Rini 2023-07-19 07:59:34 -04:00
commit 5dcfc99b2b
25 changed files with 153 additions and 19 deletions
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4
arch/powerpc/dts/t1023si-post.dtsi
View file

@ -3,13 +3,15 @@
* T1023 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2019-2020 NXP
* Copyright 2019-2023 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"

12
arch/powerpc/dts/t1024rdb-u-boot.dtsi Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2023 NXP */
&serial0 {
bootph-all;
};
&serial1 {
bootph-all;
};
#include "u-boot.dtsi"

6
arch/powerpc/dts/t1024rdb.dts
View file

@ -3,7 +3,7 @@
* T1024RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2020 NXP
* Copyright 2019-2023 NXP
*/
/include/ "t102x.dtsi"
@ -17,6 +17,10 @@
aliases {
sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
spi0 = &espi0;
};

12
arch/powerpc/dts/t1042d4rdb-u-boot.dtsi Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2023 NXP */
&serial0 {
bootph-all;
};
&serial1 {
bootph-all;
};
#include "u-boot.dtsi"

6
arch/powerpc/dts/t1042d4rdb.dts
View file

@ -3,7 +3,7 @@
* T1042D4RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2021 NXP
* Copyright 2019-2023 NXP
*/
/include/ "t104x.dtsi"
@ -17,6 +17,10 @@
aliases {
spi0 = &espi0;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
};
};

4
arch/powerpc/dts/t1042si-post.dtsi
View file

@ -3,11 +3,13 @@
* T1042 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 - 2014 Freescale Semiconductor Inc.
* Copyright 2021 NXP
* Copyright 2021-2023 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"

12
arch/powerpc/dts/t2080rdb-u-boot.dtsi Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2023 NXP */
&serial0 {
bootph-all;
};
&serial1 {
bootph-all;
};
#include "u-boot.dtsi"

6
arch/powerpc/dts/t2080rdb.dts
View file

@ -3,7 +3,7 @@
* T2080RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2021 NXP
* Copyright 2019-2023 NXP
*/
/include/ "t2080.dtsi"
@ -17,6 +17,10 @@
aliases {
spi0 = &espi0;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
};
};

4
arch/powerpc/dts/t2080si-post.dtsi
View file

@ -3,12 +3,14 @@
* T2080 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2021 NXP
* Copyright 2021-2023 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"

12
arch/powerpc/dts/t4240rdb-u-boot.dtsi Normal file
View file

@ -0,0 +1,12 @@
// SPDX-License-Identifier: GPL-2.0+
/* Copyright 2023 NXP */
&serial0 {
bootph-all;
};
&serial1 {
bootph-all;
};
#include "u-boot.dtsi"

6
arch/powerpc/dts/t4240rdb.dts
View file

@ -3,7 +3,7 @@
* T4240RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019-2021 NXP
* Copyright 2019-2023 NXP
*/
/include/ "t4240.dtsi"
@ -17,6 +17,10 @@
aliases {
spi0 = &espi0;
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
};
};

4
arch/powerpc/dts/t4240si-post.dtsi
View file

@ -3,11 +3,13 @@
* T4240 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2021 NXP
* Copyright 2021-2023 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-duart-0.dtsi"
/include/ "qoriq-duart-1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"

12
board/freescale/t102xrdb/t102xrdb.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
* Copyright 2020-2023 NXP
*/
#include <common.h>
@ -20,6 +20,7 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <clock_legacy.h>
#include <fm_eth.h>
#include "t102xrdb.h"
#ifdef CONFIG_TARGET_T1024RDB
@ -45,6 +46,13 @@ enum {
};
#endif
#if CONFIG_IS_ENABLED(DM_SERIAL)
int get_serial_clock(void)
{
return get_bus_freq(0) / 2;
}
#endif
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
@ -159,6 +167,8 @@ int board_early_init_r(void)
board_mux_lane();
#endif
pci_init();
return 0;
}

12
board/freescale/t104xrdb/t104xrdb.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2023 NXP
*/
#include <common.h>
@ -22,6 +23,7 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <clock_legacy.h>
#include <fm_eth.h>
#include "../common/sleep.h"
#include "t104xrdb.h"
@ -29,6 +31,13 @@
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(DM_SERIAL)
int get_serial_clock(void)
{
return get_bus_freq(0) / 2;
}
#endif
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
@ -88,6 +97,9 @@ int board_early_init_r(void)
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
pci_init();
return 0;
}

13
board/freescale/t208xrdb/t208xrdb.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2009-2013 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
* Copyright 2021-2023 NXP
*/
#include <common.h>
@ -20,6 +20,7 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <clock_legacy.h>
#include <fm_eth.h>
#include "t208xrdb.h"
#include "cpld.h"
@ -42,6 +43,13 @@ u8 get_hw_revision(void)
}
}
#if CONFIG_IS_ENABLED(DM_SERIAL)
int get_serial_clock(void)
{
return get_bus_freq(0) / 2;
}
#endif
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
@ -106,6 +114,9 @@ int board_early_init_r(void)
*/
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
pci_init();
return 0;
}

11
board/freescale/t4rdb/t4240rdb.c
View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2023 NXP
*/
#include <common.h>
@ -20,6 +21,7 @@
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <clock_legacy.h>
#include <fm_eth.h>
#include "t4rdb.h"
@ -28,6 +30,13 @@
DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(DM_SERIAL)
int get_serial_clock(void)
{
return get_bus_freq(0) / 2;
}
#endif
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
@ -86,6 +95,8 @@ int board_early_init_r(void)
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
pci_init();
return 0;
}

4
configs/T1024RDB_defconfig
View file

@ -101,7 +101,9 @@ CONFIG_SYS_QE_FW_ADDR=0xEFE00000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1337=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y

4
configs/T1042D4RDB_defconfig
View file

@ -101,7 +101,9 @@ CONFIG_SYS_QE_FW_ADDR=0xEFF10000
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1337=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y

4
configs/T2080RDB_defconfig
View file

@ -106,7 +106,9 @@ CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y

4
configs/T2080RDB_revD_defconfig
View file

@ -108,7 +108,9 @@ CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1307=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y

4
configs/T4240RDB_defconfig
View file

@ -96,7 +96,9 @@ CONFIG_MII=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550_SERIAL=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y

4
include/configs/T102xRDB.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020-2021 NXP
* Copyright 2020-2023 NXP
*/
/*
@ -283,7 +283,9 @@
#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* Serial Port */
#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#endif
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

4
include/configs/T104xRDB.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020-2021 NXP
* Copyright 2020-2023 NXP
*/
#ifndef __CONFIG_H
@ -238,7 +238,9 @@
* open - index 2
* shorted - index 1
*/
#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#endif
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

4
include/configs/T208xRDB.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020-2021 NXP
* Copyright 2020-2023 NXP
*/
/*
@ -215,7 +215,9 @@
/*
* Serial Port
*/
#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#endif
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)

4
include/configs/T4240RDB.h
View file

@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2020-2021 NXP
* Copyright 2020-2023 NXP
*/
/*
@ -77,7 +77,9 @@
* open - index 2
* shorted - index 1
*/
#if !CONFIG_IS_ENABLED(DM_SERIAL)
#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
#endif
#define CFG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}