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x86: Make sure that the LPC is active before SDRAM init

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Some boards need to access GPIOs to determine which SDRAM is fitted to the
board, for example chromebook_link. Probe this device (if it exists) to
make sure that this works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2023-07-15 21:39:13 -06:00 committed by Bin Meng
parent df1bb2cb0b
commit dac1fa5c19
1 changed files with 9 additions and 0 deletions
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9
arch/x86/lib/spl.c
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@ -65,6 +65,8 @@ static int set_max_freq(void)
static int x86_spl_init(void)
{
struct udevice *dev;
#ifndef CONFIG_TPL
/*
* TODO(sjg@chromium.org): We use this area of RAM for the stack
@ -114,6 +116,13 @@ static int x86_spl_init(void)
return ret;
}
#endif
/* probe the LPC so we get the GPIO_BASE set up correctly */
ret = uclass_first_device_err(UCLASS_LPC, &dev);
if (ret && ret != -ENODEV) {
log_debug("lpc probe failed\n");
return ret;
}
ret = dram_init();
if (ret) {
log_debug("dram_init() failed (err=%d)\n", ret);