Commit graph

56 commits

Author SHA1 Message Date
Tom Rini
4e05c167a7 binman support for FIT
new UCLASS_SOC
 patman switch 'test' command
 minor fdt fixes
 patman usability improvements
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Merge tag 'dm-pull-20jul20-take2a' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

binman support for FIT
new UCLASS_SOC
patman switch 'test' command
minor fdt fixes
patman usability improvements
2020-07-27 11:15:37 -04:00
Masahiro Yamada
8613c8d897 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.

One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:

    priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
    if (!priv->regs)
            return -EINVAL;

devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.

dev_read_addr_ptr() returns NULL on error, so this error check
will work.

I generated this commit by the following command:

 $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
   xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'

I manually fixed drivers/usb/host/ehci-mx6.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-25 14:46:57 -06:00
Adam Ford
e9a52c4439 clk: renesas: Add R8A774A1 clock tables
This sync's the clock tables with the official release from
Linux 5.8-RC2 and update r8a774a1_mstp_table from Ref Manual
v1.00.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25 11:16:39 +02:00
Tom Rini
7208396bbf Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit 5d3a21df66, reversing
changes made to 56d37f1c56.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24 08:42:06 -04:00
Masahiro Yamada
3c12c62ba5 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr()
Use the _ptr suffixed variant instead of casting. Also, convert it to
dev_read_addr_ptr(), which is safe to CONFIG_OF_LIVE.

One curious part is an error check like follows in
drivers/watchdog/omap_wdt.c:

    priv->regs = (struct wd_timer *)devfdt_get_addr(dev);
    if (!priv->regs)
            return -EINVAL;

devfdt_get_addr() returns FDT_ADDR_T_NONE (i.e. -1) on error.
So, this code does not catch any error in DT parsing.

dev_read_addr_ptr() returns NULL on error, so this error check
will work.

I generated this commit by the following command:

 $ find . -name .git -prune -o -name '*.[ch]' -type f -print | \
   xargs sed -i -e 's/([^*)]*\*)devfdt_get_addr(/dev_read_addr_ptr(/'

I manually fixed drivers/usb/host/ehci-mx6.c

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Marek Vasut
061ef41fcf clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2
The fdtdec_get_addr() does not take into account values set in #address-cells
and #size-cells , but assumes them to be 1 for 32bit systems and 2 for 64bit
systems. This is true for most DTs, however there are exceptions. Switch to
fdtdec_get_addr_size_auto_noparent(), which takes the #address/size-cells
values into consideration, otherwise the reset controller node register
offset is incorrectly parsed.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30 03:49:23 +02:00
Marek Vasut
ca6da6dd93 clk: renesas: Add R8A77980 V3H clock tables
Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-08-09 23:15:01 +02:00
Marek Vasut
72242e5439 clk: renesas: Synchronize Gen3 tables with Linux 5.0
Synchronize R-Car Gen3 clock tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
a3c31e98a1 clk: renesas: Synchronize Gen2 tables with Linux 5.0
Synchronize R-Car Gen2 clock tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
933143997b clk: renesas: Add R8A77965 clock tables
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-04-09 18:19:10 +02:00
Marek Vasut
3cb2849c76 clk: renesas: Add support for setting MMCIF clock divider on Gen2
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
4b135d5464 clk: renesas: Fix swapped div and mul in debug output on Gen2
The $div and $mul values were swapped in the debug output,
fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
45b01b462f clk: renesas: Fix SDH clock divider decoding on Gen2
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
18a37a5a8b clk: rmobile: Drop def_bool per SoC
Drop per SoC def_bool on each driver, since this is now implied by
SoC Kconfig option instead.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-02-25 16:07:41 +01:00
Marek Vasut
f58d6771a2 clk: renesas: Allow reconfiguring SDHI clock on Gen3
The SDHI clock must be configured differently for HS200/HS400/SDR104
modes. Add support for reconfiguring the SDHI clock settings into the
clock driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-12-03 12:51:16 +01:00
Marek Vasut
6995fc3aca clk: rmobile: Add R8A77995 RPC clock
Add missing RPC entry into the R8A77995 clock driver tables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00
Marek Vasut
0f4ab201fa clk: rmobile: Add R8A77990 RPC clock
Add missing RPC entry into the R8A77990 clock driver tables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00
Tom Rini
040b2583c3 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-06-02 16:58:27 -04:00
Marek Vasut
0d218efe2b clk: renesas: Add R8A77990 E3 clock tables
Add clock tables for R8A77990 E3 SoC .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:01 +02:00
Marek Vasut
716d775286 clk: renesas: Add PE clock handling
The PE clock have two parents, add support for picking the correct
one and deriving the clock from it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Marek Vasut
f0f1de75c9 clk: renesas: Add PLL1 and PLL3 dividers
Add and use the PLL1 and PLL3 dividers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Marek Vasut
8376e0e6f7 clk: renesas: Pass clock rate around as 64bit number internally
The PLL rate could be in the GHz range, which could overflow a 32bit
data type. Since the hardware is 64bit anyway, pass the clock rates
as 64bit number internally to avoid this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Marek Vasut
15e0918285 clk: renesas: Fix swapped arguments in debug message
The mul and div arguments were reported in reverse order in the debug
message, swap them to fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Marek Vasut
424060dae4 clk: renesas: Drop USB extal from the R8A7792 clock driver
The R8A7792 does not have the USB extal, so drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-05-02 10:49:58 +02:00
Marek Vasut
010bbe7331 clk: renesas: Minor clean up of the R8A7794 clock driver
The initconst is not used in U-Boot, drop it. The r8a7794_crit_mod_clks
is also not used in U-Boot, so drop it too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-21 18:00:00 +02:00
Marek Vasut
841feae985 clk: renesas: Minor clean up of the R8A7792 clock driver
The initconst is not used in U-Boot, drop it. The r8a7792_crit_mod_clks
is also not used in U-Boot, so drop it too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-21 18:00:00 +02:00
Marek Vasut
cc64a51546 clk: renesas: Minor clean up of the R8A7790 clock driver
The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks
is also not used in U-Boot, so drop it too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-04-13 23:41:44 +02:00
Marek Vasut
c6d99986f0 clk: renesas: Add R8A77965 M3N entries
Add entries for the R8A77965 M3N SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-03-05 10:59:37 +01:00
Marek Vasut
fd5577ce26 clk: rmobile: Assure SD-IF clock are configured correctly
The SD driver calls clk_set_rate() before clk_enable(), yet clk_set_rate()
implementation in the clock driver does not set the SD-IF divider. Fix it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-02-16 16:43:09 +01:00
Tom Rini
9c486e7cb0 Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh 2018-01-27 18:25:00 -05:00
Marek Vasut
19b1a8b7a7 clk: renesas: Import R8A7794 E2 clock tables
Import clock tables for R8A7794 E2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
ce43893d4d clk: renesas: Import R8A7792 V2H clock tables
Import clock tables for R8A7792 V2H SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
67dbebe203 clk: renesas: Import R8A7791/R8A7793 M2 clock tables
Import clock tables for R8A7791 M2W and R8A7793 M2N SoC from upstream Linux
kernel v4.15-rc8, commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
75a5096da4 clk: renesas: Import R8A7790 H2 clock tables
Import clock tables for R8A7790 H2 SoC from upstream Linux kernel v4.15-rc8,
commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
dedb60fb5b clk: renesas: Add Gen2 clock core
Add common clock code for Renesas RCar Gen2 platforms.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
28b8f225b4 clk: renesas: Add DIV6P1 clock type
Add macros for the DIV6P1 clock type, which is used on Gen2
and optionally also on Gen3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
d26286715f clk: renesas: Split out code shared between Gen2 and Gen3
Pull code which is common for RCar Gen2 and RCar Gen3 into
separate source file. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
65f1bbf678 clk: renesas: Make clock tables Kconfig configurable
Add Kconfig entries for each SoC clock table, so they can be
compiled in or out at build time. This can reduce the size of
the binary if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
ff50b323b3 clk: renesas: Split SMSTPCR and RMSTPCR tables
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this
is thus far always zero. Split the tables so the RMSTPCR can be set
too.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
58f1788f47 clk: renesas: Pull Gen3 specific bits into separate header
Extract the macros specific to Gen3 clock into a separate header.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:22 +01:00
Marek Vasut
7c88556323 clk: renesas: Make PLL configurations per-SoC
Not all SoCs have the same PLL configuration options,
so make those PLL configuraion tables per-SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Marek Vasut
f11c9679ab clk: renesas: Make clk_ids per-driver
Not all drivers use the same IDs, so make those IDs per-driver.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Marek Vasut
f77b5a4cd1 clk: renesas: Split RCar Gen3 driver
Split the massive driver into smaller per-SoC drivers and pull the
common code into a separate file. This would allow configuring out
unnecessary clock drivers once the Kconfig changes are in and also
allow adding more clock tables easily.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-01-24 23:27:21 +01:00
Álvaro Fernández Rojas
48263504c8 wait_bit: use wait_for_bit_le32 and remove wait_for_bit
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Marek Vasut
2c150950b0 clk: rmobile: Add R8A77995 D3 clock tables
Add clock tables for R8A77995 D3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:25 +01:00
Marek Vasut
7691ff2ada clk: rmobile: Add R8A77970 V3M clock tables
Add clock tables for R8A77970 V3M SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:25 +01:00
Marek Vasut
894ee0575f clk: rmobile: Fix typo in R8A7796 RPC clock table entry
Fix a copy-paste typo in the clock table entry, s/7795/7796/.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2017-12-09 13:36:25 +01:00