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https://github.com/AsahiLinux/u-boot
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clk: renesas: Split SMSTPCR and RMSTPCR tables
The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
parent
58f1788f47
commit
ff50b323b3
6 changed files with 57 additions and 30 deletions
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@ -500,10 +500,11 @@ int gen3_clk_remove(struct udevice *dev)
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/* Stop module clock */
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for (i = 0; i < info->mstp_table_size; i++) {
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clrsetbits_le32(priv->base + SMSTPCR(i),
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info->mstp_table[i].dis,
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info->mstp_table[i].en);
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info->mstp_table[i].sdis,
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info->mstp_table[i].sen);
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clrsetbits_le32(priv->base + RMSTPCR(i),
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info->mstp_table[i].dis, 0x0);
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info->mstp_table[i].rdis,
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info->mstp_table[i].ren);
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}
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return 0;
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@ -316,12 +316,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
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};
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static const struct mstp_stop_table r8a7795_mstp_table[] = {
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{ 0x00640800, 0x0 }, { 0xF3EE9390, 0x0 },
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{ 0x340FAFDC, 0x2040 }, { 0xD80C7CDF, 0x400 },
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{ 0x80000184, 0x180 }, { 0x40BFFF46, 0x0 },
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{ 0xE5FBEECF, 0x0 }, { 0x39FFFF0E, 0x0 },
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{ 0x01F19FF4, 0x0 }, { 0xFFDFFFFF, 0x0 },
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{ 0xFFFEFFE0, 0x0 }, { 0x00000000, 0x0 },
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{ 0x00640800, 0x0, 0x00640800, 0 },
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{ 0xF3EE9390, 0x0, 0xF3EE9390, 0 },
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{ 0x340FAFDC, 0x2040, 0x340FAFDC, 0 },
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{ 0xD80C7CDF, 0x400, 0xD80C7CDF, 0 },
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{ 0x80000184, 0x180, 0x80000184, 0 },
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{ 0x40BFFF46, 0x0, 0x40BFFF46, 0 },
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{ 0xE5FBEECF, 0x0, 0xE5FBEECF, 0 },
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{ 0x39FFFF0E, 0x0, 0x39FFFF0E, 0 },
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{ 0x01F19FF4, 0x0, 0x01F19FF4, 0 },
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{ 0xFFDFFFFF, 0x0, 0xFFDFFFFF, 0 },
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{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
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{ 0x00000000, 0x0, 0x00000000, 0 },
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};
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static const void *r8a7795_get_pll_config(const u32 cpg_mode)
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@ -289,12 +289,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
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};
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static const struct mstp_stop_table r8a7796_mstp_table[] = {
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{ 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
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{ 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
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{ 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
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{ 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
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{ 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
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{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
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{ 0x00200000, 0x0, 0x00200000, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
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{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
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{ 0x80000184, 0x180, 0x80000184, 0 },
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{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
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{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
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{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
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{ 0x000000B7, 0x0, 0x000000B7, 0 },
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};
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static const void *r8a7796_get_pll_config(const u32 cpg_mode)
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@ -180,12 +180,18 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
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};
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static const struct mstp_stop_table r8a77970_mstp_table[] = {
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{ 0x00230000, 0x0 }, { 0xFFFFFFFF, 0x0 },
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{ 0x14062FD8, 0x2040 }, { 0xFFFFFFDF, 0x400 },
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{ 0x80000184, 0x180 }, { 0x83FFFFFF, 0x0 },
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{ 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
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{ 0x7FF3FFF4, 0x0 }, { 0xFBF7FF97, 0x0 },
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{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
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{ 0x00230000, 0x0, 0x00230000, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0x14062FD8, 0x2040, 0x14062FD8, 0 },
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{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
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{ 0x80000184, 0x180, 0x80000184, 0 },
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{ 0x83FFFFFF, 0x0, 0x83FFFFFF, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0x7FF3FFF4, 0x0, 0x7FF3FFF4, 0 },
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{ 0xFBF7FF97, 0x0, 0xFBF7FF97, 0 },
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{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
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{ 0x000000B7, 0x0, 0x000000B7, 0 },
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};
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static const void *r8a77970_get_pll_config(const u32 cpg_mode)
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@ -182,19 +182,25 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
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*/
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#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
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/* EXTAL div PLL1 mult/div PLL3 mult/div */
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{ 1, 100, 3, 100, 3, },
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{ 1, 100, 3, 116, 6, },
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};
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static const struct mstp_stop_table r8a77995_mstp_table[] = {
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{ 0x00200000, 0x0 }, { 0xFFFFFFFF, 0x0 },
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{ 0x340E2FDC, 0x2040 }, { 0xFFFFFFDF, 0x400 },
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{ 0x80000184, 0x180 }, { 0xC3FFFFFF, 0x0 },
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{ 0xFFFFFFFF, 0x0 }, { 0xFFFFFFFF, 0x0 },
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{ 0x01F1FFF7, 0x0 }, { 0xFFFFFFFE, 0x0 },
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{ 0xFFFEFFE0, 0x0 }, { 0x000000B7, 0x0 },
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{ 0x00200000, 0x0, 0x00200000, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0x340E2FDC, 0x2040, 0x340E2FDC, 0 },
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{ 0xFFFFFFDF, 0x400, 0xFFFFFFDF, 0 },
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{ 0x80000184, 0x180, 0x80000184, 0 },
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{ 0xC3FFFFFF, 0x0, 0xC3FFFFFF, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0xFFFFFFFF, 0x0, 0xFFFFFFFF, 0 },
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{ 0x01F1FFF7, 0x0, 0x01F1FFF7, 0 },
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{ 0xFFFFFFFE, 0x0, 0xFFFFFFFE, 0 },
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{ 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0 },
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{ 0x000000B7, 0x0, 0x000000B7, 0 },
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};
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static const void *r8a77995_get_pll_config(const u32 cpg_mode)
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@ -86,8 +86,10 @@ struct mssr_mod_clk {
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{ .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
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struct mstp_stop_table {
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u32 dis;
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u32 en;
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u32 sdis;
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u32 sen;
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u32 rdis;
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u32 ren;
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};
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#define TSTR0 0x04
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