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8376e0e6f7
The PLL rate could be in the GHz range, which could overflow a 32bit data type. Since the hardware is 64bit anyway, pass the clock rates as 64bit number internally to avoid this. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
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.. | ||
clk-rcar-gen2.c | ||
clk-rcar-gen3.c | ||
Kconfig | ||
Makefile | ||
r8a7790-cpg-mssr.c | ||
r8a7791-cpg-mssr.c | ||
r8a7792-cpg-mssr.c | ||
r8a7794-cpg-mssr.c | ||
r8a7795-cpg-mssr.c | ||
r8a7796-cpg-mssr.c | ||
r8a77970-cpg-mssr.c | ||
r8a77995-cpg-mssr.c | ||
rcar-gen2-cpg.h | ||
rcar-gen3-cpg.h | ||
renesas-cpg-mssr.c | ||
renesas-cpg-mssr.h |