Commit graph

129 commits

Author SHA1 Message Date
Hans de Goede
c13f60d92a sunxi: Add a GMAC Transmit Clock Delay Chain Kconfig option
And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-02-02 13:55:14 +01:00
Hans de Goede
1a800f7af3 sunxi: Hookup OTG USB controller support
Hookup OTG USB controller support and enable the otg controller + USB-keyb
on various tablets.

This allows tablet owners to interact with u-boot without needing to solder
a serial console onto their tablet PCB.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:56 +01:00
Hans de Goede
7cd6f92d41 sunxi: video: Use frontend for dma on sun4i to fix memory bandwidth problems
Testing has shown that on sun4i the display backend engine does not have
deep enough fifo-s causing flickering / tearing in full-hd mode due to
fifo underruns. On sun4i use the display frontend engine to do the dma from
memory, as the frontend does have deep enough fifo-s.

As added advantage of this is that it results in much better memory bandwidth
as it reduces the amount of dram bank switches, for more details see:

http://ssvb.github.io/2014/11/11/revisiting-fullhd-x11-desktop-performance-of-the-allwinner-a10.html

Note that this changes the pipeline searched for in the simplefb node, we can
get away with doing this now, since no kernel has yet shipped with simplefb
dtb nodes, and I will make sure to get a simplefb node with the new pipeline
into 3.19 before it ships.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:56 +01:00
Hans de Goede
8ffc487c75 sunxi: Stop differentiating between 512M and 1G variants of the same board
While working on adding more boards I noticed that we lack a config for
the 512M cubieboard, and that some of the new boards which I want to add also
have 512M and 1G variants, rather then adding 2 defconfig's for all of these,
lets switch the exising boards which have both a 512M and 1024M variant over
to the sun4i dram autoconfig code.

This also drops the foo_RAMSIZE_defconfig variants of boards where we currently
have 2 separate configs already.

Note:
1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with
a value other then its default for now, but we need this to be configurable
to support some new boards with auto dram config.

2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match
the defaults, this is done to make it more clear what values are used for a
certain board.

This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G
variants, the dram autoconfig code has also been tested on a 512M mk802
(a defconfig for the mk802 is added in a later patch).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:56 +01:00
Hans de Goede
daf22636c2 sunxi: mmc: Add support for sun9i (A80)
The clocks on the A80 are hooked up slightly different, add support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
e35377d726 sun9i: Add clock_sun9i.h with ccu register layout for sun9i
Add a headerfile with the sun9i ccu register layout.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
ee74fec845 sun9i: Add cpu_sun9i.h with iomem defines
Add a headerfile with all the base addresses from the sun9i blocks.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
9803e4e1db sunxi: Rename cpu.h to cpu_sun4i.h
sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite
different, so add a wrapper cpu.h which includes the right mach specific
cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
cc67a0b6e5 sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headers
Which pll-s are available depends on the machine type, move the
clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files
so that we only declare what is actually available. e.g. clock_get_pll5p()
is not available on sun6i / sun8i, and with sun9i we get a completely
different set of plls.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
6515032e3b sunxi: display: Make lcd display clk phase configurable
While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.

This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.

This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.

The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-22 12:34:55 +01:00
Hans de Goede
4458b7a6e1 sunxi: usbc: Add support for usb0 to the common usbc code
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
0eccec4ef1 sunxi: Move usb-controller init code out of ehci-sunxi.c for reuse for otg
Most of the usb-controller init code found in ehci-sunxi.c also is necessary
to init the otg usb controller, so move it to a common place.

While at it also update various #ifdefs / defines for sun8i support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:40 +01:00
Hans de Goede
213480e12d sunxi: video: Add lvds support
Add support for lvds lcd panels

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:40 +01:00
Hans de Goede
d9786d2380 sunxi: video: Add VGA output support
Add support for VGA directly from the sunxi SoC / display engine.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:39 +01:00
Hans de Goede
2dae800f1e sunxi: video: Add lcd output support
Add lcd output support, see the new Kconfig entries and doc/README.video for
how to enable / configure this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:39 +01:00
Hans de Goede
5489ebc7af sunxi: video: Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1
Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1, this is a
preparation patch for adding lcd support.

While at it also swap the divider search order, searching from low to
high, as the comment above the code says we should do. In cases where there
are multiple solutions this will result in picking a lower pll clock and
divider, which is more stable and saves power.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:39 +01:00
Hans de Goede
6c727e09a0 sunxi: gpio: Add support for gpio pins on the AXP209 pmic
Some boards use GPIO-s on the pmic, one example of this is the A13-OLinuXino
board, which uses gpio0 of the axp209 for the lcd-power signal.

This commit adds support for gpio pins on the AXP209 pmic, the sunxi_gpio.c
changes are universal, adding gpio support for the other AXP pmics (when
necessary) should be a matter of adding the necessary axp_gpio_foo functions
to their resp. drivers, and add "#define AXP_GPIO" to their header file.

Note this commit only adds support for the non device-model version of the
gpio code, patches for adding support to the device-model version are very
welcome.

The string representation for these gpio-s is AXP0-#, the 0 in the AXP0 prefix
is there in case we need to support gpio-s on more then 1 pmic in the future.
At least A80 boards have 2 pmics, and we may end up needing to support gpio-s
on both.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:38 +01:00
Hans de Goede
d27f7d14ea sunxi: gpio: Properly sort mux defines by port number
Move a few mux defines around so that all the mux defines are properly sorted
by port number.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:38 +01:00
Hans de Goede
876aaafdbd sunxi: video: Set input sync enable
Add a write to the "unknown" (*) register to enable auto input sync, when
initially adding sunxi hdmi output support this magic write from the android
kernel code was missed, causing lcdc -> hdmi encoder sync problems.

With this write added, we can drop the modesetting retries and the extra
delays added to work around these sync problems.

With the retries dropped there also is no need to 0 all the enable flags at
the beginning of the modeset, as they are initialized to 0 already by
engines_init.

*) "unknown" is the actual name of this register in the android kernel sources

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
5ee0bea49a sunxi: video: Add hdmi support
So far we've been programming the hdmi-encoder to send out dvi data over the
hdmi connector. This works well for most devices, including hdmi devices, but
not all devices accept dvi data on a hdmi input.

Add support for sending proper hdmi data over the hdmi output found on most
sunxi boards. This can be turned on by adding monitor=hdmi as option to the
video-mode env. variable.

A follow up patch will determine whether to send dvi or hdmi automatically when
EDID is used.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
75481607c7 sunxi: video: Add DDC & EDID support
Add DDC & EDID support and use it to automatically select the native mode of
the attached monitor. This can be disabled by adding edid=0 as option
to the video-mode env. variable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-01-14 14:56:38 +01:00
Hans de Goede
25508ab26c sunxi: Fix PLL1 running at half speed on sun8i
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Siarhei Siamashka
c3d2b963c6 sunxi: Fix buggy sun6i/sun8i DRAM size detection logic
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).

The current sun6i/sun8i DRAM size detection logic, which is
inherited from the Allwinner code, relies on using a large magic
signature with the hope that it is unique enough and unlikely to
ever accidentally match this leftover garbage data in RAM. But
this approach is inherently unsafe, as can be demonstrated using
the following test program:

/***** A testcase for reproducing the problem ******/

void main(int argc, char *argv[])
{
    size_t size, i;
    uint32_t *buf;
    /* Allocate the buffer */
    if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) ||
                    !(buf = malloc(size))) {
        printf("Need buffer size in MiB as a cmdline argument\n");
        exit(1);
    }
    /* Fill it with the Allwinner DRAM "magic" values */
    for (i = 0; i < size / 4; i++)
        buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64;
    /* Try to reboot */
    system("reboot");
    /* And wait */
    for (;;) {}
}
/***************************************************/

If this test program is run on the device (giving it a large
chunk of memory), then the DRAM size detection logic in u-boot
gets confused after reboot and fails to initialize DRAM properly.

A better approach is not to rely on luck and abstain from making
any assumptions about the properties of the leftover garbage
data in RAM. Instead just use a more reliable code for testing
whether two different addresses refer to the same memory location.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-01-14 14:56:37 +01:00
Hans de Goede
08fd1479c7 sun8i: Add dram initialization support
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
2367b44d0f sunxi: Use memcmp for mctl_mem_matches
Use memcmp for mctl_mem_matches instead of DIY.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
5665f50e81 sunxi: Fill memory before comparing it when doing dram init on sun6i
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, instead relying on the memory contents being random enough
to begin with for the memcmp to properly detect the wrap-around address, iow
it is working purely by chance. Since our sun6i dram code was modelled after
the boot0 code it contained the same issue.

This commit fixes this by filling the memory with a unique, distinct pattern.

The new mctl_mem_fill function this introduces is added as an inline helper
in dram.h, so that it can be shared with the sun8i dram code.

While at it move mctl_mem_matches to dram.h for re-use in sun8i too.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
07f4fe7d7d sunxi: Move await_completion dram helper to dram.h
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
5af741f1e9 sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:37 +01:00
Hans de Goede
66ebea06f7 sunxi: Add support for the rsb (Reduced Serial Bus)
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.

This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
ce881076fc sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/
The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
cac5b1cc0d sunxi: Add sunxi_get_sid helper function
On sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a helper function to abstract this away.

This makes our MAC address generation code also work on sun6i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
fc3a832576 sunxi: mmc: Properly setup mod-clk and clock sampling phases
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.

The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).

For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.

This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
10191ed098 sun6i: Add sunxi_get_ss_bonding_id() function
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-01-14 14:56:36 +01:00
Hans de Goede
eafec32000 sun6i: Add gmac support for sun6i boards
Hookup the gmac found on the sun6i / A31 SoCs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Luc Verhaegen
2d7a084ba0 sunxi: video: Add simplefb support
Add simplefb support, note this depends on the kernel having support for
the clocks property which has recently been added to the simplefb devicetree
binding.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Use pre-populated simplefb node under /chosen as
 disussed on the devicetree list]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>.
2014-11-25 13:38:46 +01:00
Luc Verhaegen
7f2c521f90 sunxi: video: Add cfb console driver for sunxi
This adds a fixed mode hdmi driver for the sunxi platform. The fixed
mode is a relatively safe 1024x768, more complete EDID handling is
currently not provided. Only HDMI is supported today.

This code is enabled when HPD detects an attached monitor.

Current config is such that 8MB is shaved off at the top of the RAM.
This avoids several memory handling issues, most significant is the fact
that on linux on ARM you are not allowed to remap known RAM as IO. A
clued in display driver will be able to recycle this reserved RAM in
future though.

cfbconsole was chosen as it provides the most important functionality: a
working u-boot console, allowing for the debugging of certain issues
without the need for a UART.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
[hdegoede@redhat.com: Major cleanups and some small bugfixes]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Hans de Goede
0bd5125133 sunxi: Add video pll clock functions
This is a preparation patch for adding support for HDMI out.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Hans de Goede
9d4b7d0bc8 sun4i: Rename dram_clk_cfg to dram_clk_gate
The data sheet just calls it DRAM_CLK_REG, and on sun6i we've both a
dram_clk_cfg and dram_clk_gate, and the sun4i reg matches dram_clk_gate on
sun6i, so name it the same on sun4i.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-25 13:38:46 +01:00
Hans de Goede
76946dfe69 sun6i: ehci: Add sun6i ehci support
Add support for the 2 ehci controllers found on the sun6i (A31) soc.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Marek Vasut <marex@denx.de>
2014-11-13 14:49:02 +01:00
Hans de Goede
9a07eb0ba0 sun6i: Add dram initialization code
Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).

This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Hans de Goede
bec72c7994 sun4i: Rename dram files to dram_sun4i.x
In preparation for adding sun6i dram support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Hans de Goede
9d8a533e3f sun6i: Add cpucfg register definitions
Not used atm, for future use (e.g. PSCI).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Hans de Goede
62c87ef2e9 sun6i: Add clock functions needed for SPL / DRAM init
Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).

Also add some extra clock register constant defines.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Oliver Schinagl
3b10e6eb68 sun6i: Add new p2wi controller driver
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-11-13 14:49:01 +01:00
Simon Glass
bf38891af2 dm: sunxi: Add pinmux functions which take a bank parameter
With driver model we will have access to a bank pointer, so we want to
use it rather than converting back to a number, and then back to a
bank pointer. Add functions to provide this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-05 13:09:58 +01:00
Ian Campbell
ed41e62f51 sunxi: Use CONFIG_MACH_SUN?I from Kconfig instead of CONFIG_SUN?I
Mostly automatic with:
    sed -i -e 's/CONFIG_\(SUN[45678]I\)/CONFIG_MACH_\1/g' $(git grep -l CONFIG_SUN[45678]I)
followed by removing the relevant #defines from include/configs/sun?i.h by
hand.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-11-05 13:09:58 +01:00
Hans de Goede
9e54f6ee01 sunxi: Add clock_get_pll5p() function
This is a preparation patch for making the pll5 "p" divisor configurable
through Kconfig.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:37:24 +02:00
Chen-Yu Tsai
c757a50bd1 ARM: sunxi: Add support for using R_UART as console
The A23 only has UART0 muxed with MMC0. Some of the boards we
encountered expose R_UART as a set of pads.

Add support for R_UART so we can have a console while using mmc.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
472ed0641e ARM: sunxi: Allow specifying module in prcm apb0 init function
The prcm apb0 controls multiple modules. Allow specifying which
modules to enable clocks and de-assert resets so the function
can be reused.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Hans de Goede
e373aad32a ARM: sunxi: Add support for R_PIO gpio banks
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO
or R_PIO, which handles pin banks L and beyond.

Also add a clear description about SUNXI_GPIO_BANKS, stating it only
counts the number of pin banks in the _main_ pin controller.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: expanded commit message]
[wens@csie.org: add pin bank M and expand comments]
[wens@csie.org: add comment on SUNXI_GPIO_BANKS macro]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
8ebe4f4292 ARM: sunxi: Add basic A23 support
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.

There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
e637b30b9c mmc: sunxi: Add support for sun8i (A23)
The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.

Re-use code added for sun6i.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:39 +02:00
Chen-Yu Tsai
7f87ad354b ARM: sunxi: Add sun8i (A23) UART0 pin mux support
UART0 pin muxes on the A23 have a different function value.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
78c396a113 ARM: sunxi: Fix reset command on sun6i/sun8i
The watchdog on sun6i/sun8i has a different layout.

Add the new layout and fix up the setup functions so that reset works.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
[ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
4cdefba86d ARM: sunxi: Add sun6i/sun8i timer block register definition
The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.

Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or have been moved out.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
2b679f9fa4 ARM: sunxi: Move watchdog register definitions to separate file
On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.

Move the register definitions to a separate file to facilitate
supporting newer SoCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Hans de Goede
bbff84b3b0 sunxi: Use PG3 - PG8 as io-pins for mmc1
None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Hans de Goede
e79c7c8810 sunxi: When we've both mmc0 and mmc2, detect from which one we're booting
sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.

When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Chen-Yu Tsai
ba1e40fdd3 ARM: sun6i: Define UART0 pins for A31
UART0 is the default debug/console UART on the A31.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:38 +02:00
Hans de Goede
1d1bd42eb0 ARM: sunxi-mmc: Add mmc support for sun6i / A31
The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
		rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Chen-Yu Tsai
14177e47e8 ARM: sun6i: Add clock support
This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Oliver Schinagl
174deb768c ARM: sun6i: Add support for the power reset control module found on the A31
The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.

This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[wens@csie.org: spacing fixes reported by checkpatch.pl]
[wens@csie.org: Use setbits helper in PRCM init function]
[wens@csie.org: rephrase commit message to explain what the hardware
		supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Oliver Schinagl
93ce1e9dad ARM: sun6i: Add base address for the new controllers in A31
A31 has several new and changed memory address. This patch adds them.

Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-10-24 09:35:37 +02:00
Siarhei Siamashka
d755a5fb20 sunxi: dram: Configurable DQS gating window mode and delay
The hardware DQS gate training is a bit unreliable and does not
always find the best delay settings.

So we introduce a 32-bit 'dqs_gating_delay' variable, where each
byte encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle.

Also we allow to enable the active DQS gating window mode, which
works better than the passive mode in practice. The DDR3 spec
says that there is a 0.9 cycles preamble and 0.3 cycle postamble.
The DQS window has to be opened during preamble and closed during
postamble. In the passive window mode, the gating window is opened
and closed by just using the gating delay settings. And because
of the 1/4 cycle delay granularity, accurately hitting the 0.3
cycle long postamble is a bit tough. In the active window mode,
the gating window is auto-closing with the help of monitoring
the DQS line, which relaxes the gating delay accuracy requirements.

But the hardware DQS gate training is still performed in the passive
window mode. It is a more strict test, which is reducing the results
variance compared to the training with active window mode.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
e044daa33e sunxi: dram: Add a helper function 'mctl_get_number_of_lanes'
It is going to be useful in more than one place.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
b8f7cb6ae3 sunxi: dram: Improve DQS gate data training error handling
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors ("found no result" and "found more than one
possible result"). Both are handled now.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
1a9717cbb3 sunxi: dram: Configurable MBUS clock speed (use PLL5 or PLL6)
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock
speed. Allwinner A13 uses only 16-bit data bus width to connect the
external DRAM, which is halved compared to the 32-bit data bus of sun4i
(Allwinner A10), so it does not make much sense to clock a wider
internal bus at a very high speed. The Allwinner A13 manual specifies
300 MHz MBUS clock speed limit and 533 MHz DRAM clock speed limit. Newer
sun7i hardware (Allwinner A20) has a full width 32-bit external memory
interface again, but still keeps the MBUS clock speed configurable.
Clocking MBUS too low inhibits memory performance and one has to find
the optimal MBUS/DRAM clock speed ratio, which may depend on many
factors:
    http://linux-sunxi.org/A10_DRAM_Controller_Performance

This patch introduces a new 'mbus_clock' parameter for the 'dram_para'
struct and uses it as a desired MBUS clock speed target. If 'mbus_clock'
is not set, 300 MHz is used by default to match the older hardcoded
settings.

PLL5P and PLL6 are both evaluated as possible clock sources. Preferring
the one, which can provide higher clock frequency that is lower or
equal to the 'mbus_clock' target. In the case of a tie, PLL5P has
higher priority.

Attempting to set the MBUS clock speed has no effect on sun4i, but does
no harm either.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Siarhei Siamashka
5c18384dea sunxi: dram: Re-introduce the impedance calibration ond ODT
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:

    http://linux-sunxi.org/A10_DRAM_Controller_Register_Guide#SDR_ZQCR0

The new code supports both of the impedance configuration modes:
   - If the higher bits of the 'zq' parameter in the 'dram_para' struct
     are zero, then the lowest 8 bits are used as the ZPROG value, where
     two divisors encoded in lower and higher 4 bits. One divisor is
     used for calibrating the termination impedance, and another is used
     for the output impedance.
   - If bits 27:8 in the 'zq' parameters are non-zero, then they are
     used as the pre-defined ZDATA value instead of performing the ZQ
     calibration.

Two lowest bits in the 'odt_en' parameter enable ODT for the DQ and DQS
lines individually. Enabling ODT for both DQ and DQS means that the
'odt_en' parameter needs to be set to 3.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12 08:42:33 +02:00
Roman Byshko
06cdd94077 sunxi: add defines to control USB Host clocks/resets
The commit adds three defines which will be used in
the EHCI driver to enable USB clock and assert
reset controllers of the corresponding PHYs.

Signed-off-by: Roman Byshko <rbyshko@gmail.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Ian Campbell
a6e50a88d8 ahci: provide sunxi SATA driver using AHCI platform framework
This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done
for sun7i only since I don't have access to any other sunxi platforms
with sata included.

The PHY setup is derived from the Alwinner releases and Linux, but is mostly
undocumented.

The Allwinner AHCI controller also requires some magic (and, again,
undocumented) DMA initialisation when starting a port.  This is added under a
suitable ifdef.

This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on
contents of Linux DTS files, including SATA power pin config taken from the
DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-07-31 15:37:22 +02:00
Ian Campbell
abce2c6220 sunxi: add gpio driver
This patch enables CONFIG_CMD_GPIO for the Allwinner (sunxi) platform as well
as providing the common gpio API (gpio_request/free, direction in/out, get/set
etc).

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Henrik Nordström <henrik@henriknordstrom.net>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-07-18 19:42:25 +01:00
Hans de Goede
6620377e4b sunxi: Add i2c support
Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
[ ijc -- updated u-boot-spl-fel.lds ]
2014-07-18 19:41:30 +01:00
Hans de Goede
c7e79dec85 sunxi: Implement reset_cpu
There is no way to reset the cpu, so use the watchdog for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-06 20:12:44 +01:00
Jeroen Hofstee
ed6c7f7f6e arm: spl: fix include guard
cc: Tom Rini <trini@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-07-05 09:28:21 +02:00
Ian Campbell
e24ea55c04 sunxi: mmc support
On Mon, 2014-05-05 at 14:18 +0200, Stefan Roese wrote:
> > +	case 1:
> > +#if CONFIG_MMC1_PG

> Are you sure that this is correct and shouldn't be:
>
> +#ifdef CONFIG_MMC1_PG
>
> ?

It's "correct" in so far as it works (the boards.cfg config stuff
#defines things to 1), but I think you are right that it isn't the
preferred style. But...

> A quick scan through this patch series shows that this define
> is not set at all. Perhaps its outdated? Or is it used to support
> some other sunxi SoC? Not sure, perhaps it should be removed for
> now.

...I had thought that it was to support some other board which wasn't
being upstreamed right now, so eventually useful and harmless for now,
but I've just checked and it isn't actually used by any of the boards in
u-boot-sunxi.git. So rather than fix it to use #ifdef lets drop it.
Rather than resend the entire series, here is v5.1 of this patch.

> Other than this please add my:
>
> Reviewed-by: Stefan Roese <sr@denx.de>

Thanks!

8<---------------------------------

>From 20704e35a41664de5f516ed0e02981ac06085102 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ijc@hellion.org.uk>
Date: Fri, 7 Mar 2014 04:29:39 +0000
Subject: [PATCH v5.1 7/8] sunxi: mmc support

This adds support for the MMC controller on the Allwinner A20 (sun7i)
processor.

Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Cc: Aaron Maoye <leafy.myeh@allwinnertech.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:26:43 +02:00
Ian Campbell
cba69eeeaa sunxi: add sun7i cpu, board and start of day support
This patch adds generic board, start of day and basic build system support for
the Allwinner A20 (sun7i) processor. This code will not been compiled until the
build is hooked up in a later patch. It has been split out to keep the patches
manageable.

Signed-off-by: Adam Sampson <ats@offog.org>
Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Patrick Wood <patrickhwood@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wills Wang <wills.wang.open@gmail.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:40 +02:00
Ian Campbell
286c3c3a5e sunxi: add sun7i dram setup support
This patch adds DRAM initialisation support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:30 +02:00
Ian Campbell
fe1b4db05e sunxi: add sun7i pinmux and gpio support
This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i)
processor. This code will not been compiled until the build is hooked up in a
later patch. It has been split out to keep the patches manageable.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Ma Haijun <mahaijuns@gmail.com>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:21 +02:00
Ian Campbell
643cf0ea02 sunxi: add sun7i clocks and timer support.
This patch adds the basic clocks and timer support for the Allwinner A20
(sun7i) processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

Some of the code here is common to multiple sunxi subarchtectures, hence files
are named sun4i which is the earliest similar variant.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Luke Leighton <lkcl@lkcl.net>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Reviewed-by: Tom Rini <trini@ti.com>
2014-05-25 16:12:12 +02:00